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Iglesias" Cc: qemu-devel@nongnu.org, Anton Johansson , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?UTF-8?Q?Marc-Andr=C3=A9_Lureau?= , Paolo Bonzini , Jason Wang , Richard Henderson , Luc Michel References: <20241105130431.22564-1-philmd@linaro.org> <20241105130431.22564-10-philmd@linaro.org> <1625bc6b-8951-414c-88c0-62061289fdb5@linaro.org> Content-Language: en-US From: Michal Simek Autocrypt: addr=michal.simek@amd.com; keydata= xsFNBFFuvDEBEAC9Amu3nk79+J+4xBOuM5XmDmljuukOc6mKB5bBYOa4SrWJZTjeGRf52VMc howHe8Y9nSbG92obZMqsdt+d/hmRu3fgwRYiiU97YJjUkCN5paHXyBb+3IdrLNGt8I7C9RMy svSoH4WcApYNqvB3rcMtJIna+HUhx8xOk+XCfyKJDnrSuKgx0Svj446qgM5fe7RyFOlGX/wF Ae63Hs0RkFo3I/+hLLJP6kwPnOEo3lkvzm3FMMy0D9VxT9e6Y3afe1UTQuhkg8PbABxhowzj SEnl0ICoqpBqqROV/w1fOlPrm4WSNlZJunYV4gTEustZf8j9FWncn3QzRhnQOSuzTPFbsbH5 WVxwDvgHLRTmBuMw1sqvCc7CofjsD1XM9bP3HOBwCxKaTyOxbPJh3D4AdD1u+cF/lj9Fj255 Es9aATHPvoDQmOzyyRNTQzupN8UtZ+/tB4mhgxWzorpbdItaSXWgdDPDtssJIC+d5+hskys8 B3jbv86lyM+4jh2URpnL1gqOPwnaf1zm/7sqoN3r64cml94q68jfY4lNTwjA/SnaS1DE9XXa XQlkhHgjSLyRjjsMsz+2A4otRLrBbumEUtSMlPfhTi8xUsj9ZfPIUz3fji8vmxZG/Da6jx/c a0UQdFFCL4Ay/EMSoGbQouzhC69OQLWNH3rMQbBvrRbiMJbEZwARAQABzSlNaWNoYWwgU2lt ZWsgKEFNRCkgPG1pY2hhbC5zaW1la0BhbWQuY29tPsLBlAQTAQgAPgIbAwULCQgHAgYVCgkI CwIEFgIDAQIeAQIXgBYhBGc1DJv1zO6bU2Q1ajd8fyH+PR+RBQJkK9VOBQkWf4AXAAoJEDd8 fyH+PR+ROzEP/1IFM7J4Y58SKuvdWDddIvc7JXcal5DpUtMdpuV+ZiHSOgBQRqvwH4CVBK7p ktDCWQAoWCg0KhdGyBjfyVVpm+Gw4DkZovcvMGUlvY5p5w8XxTE5Xx+cj/iDnj83+gy+0Oyz VFU9pew9rnT5YjSRFNOmL2dsorxoT1DWuasDUyitGy9iBegj7vtyAsvEObbGiFcKYSjvurkm MaJ/AwuJehZouKVfWPY/i4UNsDVbQP6iwO8jgPy3pwjt4ztZrl3qs1gV1F4Zrak1k6qoDP5h 19Q5XBVtq4VSS4uLKjofVxrw0J+sHHeTNa3Qgk9nXJEvH2s2JpX82an7U6ccJSdNLYbogQAS BW60bxq6hWEY/afbT+tepEsXepa0y04NjFccFsbECQ4DA3cdA34sFGupUy5h5la/eEf3/8Kd BYcDd+aoxWliMVmL3DudM0Fuj9Hqt7JJAaA0Kt3pwJYwzecl/noK7kFhWiKcJULXEbi3Yf/Y pwCf691kBfrbbP9uDmgm4ZbWIT5WUptt3ziYOWx9SSvaZP5MExlXF4z+/KfZAeJBpZ95Gwm+ FD8WKYjJChMtTfd1VjC4oyFLDUMTvYq77ABkPeKB/WmiAoqMbGx+xQWxW113wZikDy+6WoCS MPXfgMPWpkIUnvTIpF+m1Nyerqf71fiA1W8l0oFmtCF5oTMkzsFNBFFuvDEBEACXqiX5h4IA 03fJOwh+82aQWeHVAEDpjDzK5hSSJZDE55KP8br1FZrgrjvQ9Ma7thSu1mbr+ydeIqoO1/iM fZA+DDPpvo6kscjep11bNhVa0JpHhwnMfHNTSHDMq9OXL9ZZpku/+OXtapISzIH336p4ZUUB 5asad8Ux70g4gmI92eLWBzFFdlyR4g1Vis511Nn481lsDO9LZhKyWelbif7FKKv4p3FRPSbB vEgh71V3NDCPlJJoiHiYaS8IN3uasV/S1+cxVbwz2WcUEZCpeHcY2qsQAEqp4GM7PF2G6gtz IOBUMk7fjku1mzlx4zP7uj87LGJTOAxQUJ1HHlx3Li+xu2oF9Vv101/fsCmptAAUMo7KiJgP Lu8TsP1migoOoSbGUMR0jQpUcKF2L2jaNVS6updvNjbRmFojK2y6A/Bc6WAKhtdv8/e0/Zby iVA7/EN5phZ1GugMJxOLHJ1eqw7DQ5CHcSQ5bOx0Yjmhg4PT6pbW3mB1w+ClAnxhAbyMsfBn XxvvcjWIPnBVlB2Z0YH/gizMDdM0Sa/HIz+q7JR7XkGL4MYeAM15m6O7hkCJcoFV7LMzkNKk OiCZ3E0JYDsMXvmh3S4EVWAG+buA+9beElCmXDcXPI4PinMPqpwmLNcEhPVMQfvAYRqQp2fg 1vTEyK58Ms+0a9L1k5MvvbFg9QARAQABwsF8BBgBCAAmAhsMFiEEZzUMm/XM7ptTZDVqN3x/ If49H5EFAmQr1YsFCRZ/gFoACgkQN3x/If49H5H6BQ//TqDpfCh7Fa5v227mDISwU1VgOPFK eo/+4fF/KNtAtU/VYmBrwT/N6clBxjJYY1i60ekFfAEsCb+vAr1W9geYYpuA+lgR3/BOkHlJ eHf4Ez3D71GnqROIXsObFSFfZWGEgBtHBZ694hKwFmIVCg+lqeMV9nPQKlvfx2n+/lDkspGi epDwFUdfJLHOYxFZMQsFtKJX4fBiY85/U4X2xSp02DxQZj/N2lc9OFrKmFJHXJi9vQCkJdIj S6nuJlvWj/MZKud5QhlfZQsixT9wCeOa6Vgcd4vCzZuptx8gY9FDgb27RQxh/b1ZHalO1h3z kXyouA6Kf54Tv6ab7M/fhNqznnmSvWvQ4EWeh8gddpzHKk8ixw9INBWkGXzqSPOztlJbFiQ3 YPi6o9Pw/IxdQJ9UZ8eCjvIMpXb4q9cZpRLT/BkD4ttpNxma1CUVljkF4DuGydxbQNvJFBK8 ywyA0qgv+Mu+4r/Z2iQzoOgE1SymrNSDyC7u0RzmSnyqaQnZ3uj7OzRkq0fMmMbbrIvQYDS/ y7RkYPOpmElF2pwWI/SXKOgMUgigedGCl1QRUio7iifBmXHkRrTgNT0PWQmeGsWTmfRit2+i l2dpB2lxha72cQ6MTEmL65HaoeANhtfO1se2R9dej57g+urO9V2v/UglZG1wsyaP/vOrgs+3 3i3l5DA= In-Reply-To: <1625bc6b-8951-414c-88c0-62061289fdb5@linaro.org> Content-Type: text/plain; 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envelope-from=michal.simek@amd.com; helo=NAM11-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.12, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: 7NneFc36VPNN On 11/14/24 23:43, Philippe Mathieu-Daudé wrote: > +Michal for Linux driver > > On 5/11/24 23:08, Edgar E. Iglesias wrote: >> On Tue, Nov 05, 2024 at 02:04:21PM +0100, Philippe Mathieu-Daudé wrote: >>> Per the datasheet (reference added in file header, p.9) >>> 'Programming Model' -> 'Register Data Types and Organization': >>> >>>      "The XPS INTC registers are read as big-endian data" >> >> Hi Phil, >> >> Some of these devices exist in both big and little endian versions. >> So far we've reused the same model by using DEVICE_NATIVE_ENDIAN. >> >> Here's the little endian version: >> https://docs.amd.com/v/u/en-US/ds747_axi_intc > > This model is specified as: > > - https://docs.amd.com/v/u/en-US/xps_intc >   LogiCORE IP XPS Interrupt Controller (v2.01a) >   DS572 April 19, 2010 > > Spec is from 2010, you added it in 2009: > >   commit 17628bc642260df3a07b9df8b8a9ca7da2e7e87c >   Author: Edgar E. Iglesias >   Date:   Wed May 20 20:11:30 2009 +0200 > >       xilinx: Add interrupt controller. > > The spec is explicit: > >   "The XPS INTC registers are read as big-endian data" > > > The other model you mention is: > > - https://docs.amd.com/v/u/en-US/ds747_axi_intc >   LogiCORE IP AXI INTC (v1.04a) >   DS747 June 19, 2013 > > The spec is more recent than your addition, and contains > the Interrupt Vector Address Register (IVAR) which is not > present in our model. > > > Indeed the latter seems to extend the former, but they are > not the same and we need some work to model the latter. > > The endianness explicit for each model (and is not listed > in the "IP Configurable Design Parameters" tables). > > > That said, let's look at Linux use. Driver was added in: > >   commit eedbdab99fffb8ed71cac75a722088b8ace2583c >   Author: Michal Simek >   Date:   Fri Mar 27 14:25:49 2009 +0100 > >       microblaze_v8: Interrupt handling and timer support > > Using explicit big-endian API: > >   +void __init init_IRQ(void) >   +{ >   ... >   +       /* >   +        * Disable all external interrupts until they are >   +        * explicity requested. >   +        */ >   +       out_be32(intc_baseaddr + IER, 0); >   + >   +       /* Acknowledge any pending interrupts just in case. */ >   +       out_be32(intc_baseaddr + IAR, 0xffffffff); >   + >   +       /* Turn on the Master Enable. */ >   +       out_be32(intc_baseaddr + MER, MER_HIE | MER_ME); > > Then the driver became clever in: > >   commit 1aa1243c339d4c902c0f9c1ced45742729a86e6a >   Author: Michal Simek >   Date:   Mon Feb 24 14:56:32 2014 +0100 > >       microblaze: Make intc driver endian aware > >       Detect endianess directly on the hardware and use >       ioread/iowrite functions. > >   +static void intc_write32(u32 val, void __iomem *addr) >   +{ >   +       iowrite32(val, addr); >   +} >   + >   +static void intc_write32_be(u32 val, void __iomem *addr) >   +{ >   +       iowrite32be(val, addr); >   +} > > @@ -140,17 +163,25 @@ static int __init xilinx_intc_of_init(struct device_node > *intc, > >   +       write_fn = intc_write32; >   +       read_fn = intc_read32; >   + >           /* >            * Disable all external interrupts until they are >            * explicity requested. >            */ >   -       out_be32(intc_baseaddr + IER, 0); >   +       write_fn(0, intc_baseaddr + IER); > >           /* Acknowledge any pending interrupts just in case. */ >   -       out_be32(intc_baseaddr + IAR, 0xffffffff); >   +       write_fn(0xffffffff, intc_baseaddr + IAR); > >           /* Turn on the Master Enable. */ >   -       out_be32(intc_baseaddr + MER, MER_HIE | MER_ME); >   +       write_fn(MER_HIE | MER_ME, intc_baseaddr + MER); >   +       if (!(read_fn(intc_baseaddr + MER) & (MER_HIE | MER_ME))) { >   +               write_fn = intc_write32_be; >   +               read_fn = intc_read32_be; >   +               write_fn(MER_HIE | MER_ME, intc_baseaddr + MER); >   +       } > > Interestingly little endianness became the default, although > the driver detect it on init. > > This is from 2014, maybe to work with the "LogiCORE IP AXI INTC" > you mentioned, which spec date is 2013. > > Indeed when forcing different endianness [*], the Linux kernel used > in our tests (tests/functional/test_microblaze*) does the check > and ends up using the correct INTC endianness: > > LE CPU, LE INTC model > pic_write addr=8 val=0 > pic_write addr=c val=ffffffff > pic_write addr=1c val=3           <- LE > pic_read 1c=3 > pic_write addr=c val=1 > pic_write addr=10 val=1 > pic_read 18=0 > > LE CPU, BE INTC model > pic_write addr=8 val=0 > pic_write addr=c val=ffffffff > pic_write addr=1c val=3000000     <- LE test > pic_read 1c=0 > pic_write addr=1c val=3           <- BE > pic_write addr=c val=1 > pic_write addr=10 val=1 > pic_read 18=0 > > BE CPU, BE INTC model > pic_write addr=8 val=0 > pic_write addr=c val=ffffffff > pic_write addr=1c val=3000000     <- LE test > pic_read 1c=0 > pic_write addr=1c val=3           <- BE > pic_write addr=c val=1 > pic_write addr=10 val=1 > pic_read 18=0 > > BE CPU, LE INTC model > pic_write addr=8 val=0 > pic_write addr=c val=ffffffff > pic_write addr=1c val=3           <- LE > pic_read 1c=3 > pic_write addr=c val=1 > pic_write addr=10 val=1 > pic_read 18=0 > > > IMHO this patch behavior is correct. Besides, I don't expect > firmwares to be as clever as Linux. > >> Can we have add property to select the endianess? >> For the Xilinx use-cases I think it may be a good idea to default it >> to little endian and have the big-endian machines explicitly set it. > > What you suggested is implemented in v3: > https://lore.kernel.org/qemu-devel/20241108154317.12129-4-philmd@linaro.org/ > but after the analysis, I wonder if it isn't safer to not > make the endianness configurable, but expose as 2 models: > - xlnx,xps_intc (2010) in BE > - xlnx,axi_intc (2013) in LE It is a little bit more complicated. In past everything started as big endian on OPB bus. Then PLB bus still big endian and then AXI came and things have been moved to little endian. That's from bus perspective. From CPU perspective itself till AXI microblaze was big endian only. With AXI cpu started to be by default little endian but still today you can still configured cpu to be big endian (C_ENDIANNESS config) with using AXI bus. Truth is that I am not aware about anybody configuring MB to big endian and we are on AXI for quite a long time. There is still code in Linux kernel for it but I can't see any reason to keep it around. I don't think that make sense to keep big endian configurations alive at all. Thanks, Michal