From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
To: Ivan Vecera <ivecera@redhat.com>, netdev@vger.kernel.org
Cc: Prathosh Satish <Prathosh.Satish@microchip.com>,
Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
Jiri Pirko <jiri@resnulli.us>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH net] dpll: zl3073x: Fix output pin phase adjustment sign
Date: Fri, 6 Feb 2026 14:04:24 +0000 [thread overview]
Message-ID: <d3f6c71c-133d-443a-adee-3430936ff8c5@linux.dev> (raw)
In-Reply-To: <20260205181055.129768-1-ivecera@redhat.com>
On 05/02/2026 18:10, Ivan Vecera wrote:
> The output pin phase adjustment functions incorrectly negate the phase
> compensation value.
>
> Per the ZL3073x datasheet, the output phase compensation register is
> simply a signed two's complement integer where:
> - Positive values move the phase later in time
> - Negative values move the phase earlier in time
>
> No negation is required. The erroneous negation caused phase adjustments
> to be applied in the wrong direction.
>
> Note that input pin phase adjustment correctly uses negation because the
> hardware has an inverted convention for input references (positive moves
> phase earlier, negative moves phase later).
Is it common for DPLLs to act this way?
>
> Fixes: 6287262f761e ("dpll: zl3073x: Add support to adjust phase")
> Signed-off-by: Ivan Vecera <ivecera@redhat.com>
Anyways, with datasheet info being correctly read, the change LGTM
Reviewed-by: Vadim Fedorenko <vadim.fedorenko@linux.dev>
next prev parent reply other threads:[~2026-02-06 14:04 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-05 18:10 [PATCH net] dpll: zl3073x: Fix output pin phase adjustment sign Ivan Vecera
2026-02-06 14:04 ` Vadim Fedorenko [this message]
2026-02-06 15:02 ` Ivan Vecera
2026-02-07 4:50 ` patchwork-bot+netdevbpf
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