[U-Boot] [PATCH] spl: fpga: Implement fpga bistream loading with fpga_load

[Michal Simek <michal.simek@xilinx.com>]

On 18.7.2018 14:54, Marek Vasut wrote:
> On 07/18/2018 02:51 PM, Michal Simek wrote:
>> There shouldn't be a need to call private spl_load_fpga_image()
>> because the whole sequence should be already handled by fpga_load().
>> The patch let spl_load_fit_image() to load data to right location based
>> on "load" property in FIT and then call fpga_load().
> 
> NAK
> 
> This breaks Arria10, sorry. The private loading function is needed on
> Arria10 as the whole bitstream is not available in RAM and needs to be
> loaded piece by piece, see [1]
> 
> [1]
> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=blobdiff;f=arch/arm/mach-socfpga/spl.c;h=82adb5dfb8de62e3d928f6f4405705f3f32a780c;hp=7ee988a2d59831ec6bff927b2a5fdad7f57da055;hb=21f835ebf2b40fc8a3e8b818c5c5ba2555dd7c65;hpb=bd198801cb95b5a8460c95a762cc4a9a44ca85ef

We are discussing this over IRC and it is clear that current solution
for altera A10 is one ugly hack which is just going over current flow.
Load address from ITS is ignored, the same for hashes.
With small changes compression could be also possible to use without big
problem which should very beneficial to speedup load from slower memories.

What we are missing is do fit image reading by chunks to feed fpga.

Currently spl_load_fpga_image() is dummy function which none is calling
that's why the first solution could be to simply revert this patch
because there is no functionality behind.

The second solution is to check if load address is not 0 and call
fpga_load only for that. In this case there is a need to check size for SPL.

Thanks,
Michal