Re: [PATCH 2/2] arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2

[Dinh Nguyen <dinguyen@kernel.org>]

On 6/25/26 23:31, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] Incomplete DT update: gmac0 is left with an invalid interrupt count that will fail dtbs validation.
> --
> 
> commit ce31f4c657e3508e9aef68e6da54a09c1d243026
> Author: Dinh Nguyen <dinguyen@kernel.org>
> 
> arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2
> 
> Populate the gmac1 and gmac2 interrupt list to support 8 TX/RX queue
> pairs.
> 
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> index 02e62d954e949..140e4bf9fb155 100644
>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> @@ -670,8 +670,40 @@ gmac1: ethernet@10820000 {
>>   			compatible = "altr,socfpga-stmmac-agilex5",
>>   				     "snps,dwxgmac-2.10";
>>   			reg = <0x10820000 0x3500>;
> 
> [Severity: Medium]
> Should gmac0 also be updated to include 17 interrupts?
> 

There was an earlier patch that updatee gmac0 to 17 interrupts:

https://lore.kernel.org/all/20260609131641.28476-1-muhammad.nazim.amirul.nazle.asmade@altera.com/

Dinh