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Mon, 03 Aug 2026 04:03:35 -0700 (PDT) X-Received: by 2002:a05:6a21:103:b0:3c0:9c1b:d0c0 with SMTP id adf61e73a8af0-3c92a99a476mr9183285637.75.1785755014787; Mon, 03 Aug 2026 04:03:34 -0700 (PDT) Received: from [10.218.15.172] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3153e04491dsm49107229eec.16.2026.08.03.04.03.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 03 Aug 2026 04:03:34 -0700 (PDT) Message-ID: Date: Mon, 3 Aug 2026 16:33:28 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/7] irqchip/irq-qcom-mpm: Program wakeup timer when CPU cluster goes to LPM To: Marc Zyngier Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Shawn Guo , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260713-b4-shikra_lpm_addition-v1-0-3d858df2cbbf@oss.qualcomm.com> <20260713-b4-shikra_lpm_addition-v1-4-3d858df2cbbf@oss.qualcomm.com> <87h5m26hqv.wl-maz@kernel.org> Content-Language: en-US From: Sneh Mankad In-Reply-To: <87h5m26hqv.wl-maz@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwODAzMDA5OSBTYWx0ZWRfX3GkFUfz+9oQq ZvJr6lSozZ6BbV5+rKPpMiziHK3Y+VH5q77zgRM1I/1w94NWCCn9Y5A9vbIugFTyxz1xS34xLXx cMYa5jmj2fcHgJJu1WXSRiyGsrNthgE= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODAzMDA5OSBTYWx0ZWRfXzvMf/Ekj4U64 G6FkNHmJGJ9qqCn+lN+GXUBBwgln1rMsEfmaBm0CN4RWrAT6prKRx1T7CwMvm8hVX5z8rnQn4Bw fZ2Rx3T41zrdDF2IozelUkx++C7FFy5XZhsNJzuA3ACD3BT43XC3khgNyqmMdXq6ghZQjcQnkv+ QPUHn/5wMhr4SntgoU7ulIiKYYdvumzQqkdLKMxqZTu5sVJQgXxJPp2R2YkHRJJEk5GG3r6A6Xp VrINMK/F2KiVfMmi2mt75lweDvykVRFPswyu4RPTKnl1TEW86O0xy6U/9jYz/q6KS427yG4g4H/ ZHXURX69AupsqS7ceq5ufkv9Bdbx5Tb67LhCgkk1wesHRTm4XqFRjgVhiw+PmWJIhkKxainFLyc KxjN+Ej4X9m9GlssAwKYUaDAWCHK4+FVOy8Nes+CuFDOz2oCFi73AqZTyaem0wJ1HOKVVGyYkQQ Krnck8xwbxf0zBqh1Og== X-Authority-Analysis: v=2.4 cv=Zest8MVA c=1 sm=1 tr=0 ts=6a707587 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=2w1JuJCqnWd_qW_YTkwA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-GUID: 4b-61GpwaPePMHpLXUl1u_zq8m1jz2ud X-Proofpoint-ORIG-GUID: 4b-61GpwaPePMHpLXUl1u_zq8m1jz2ud X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-02_06,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608030099 On 13-Jul-26 8:48 PM, Marc Zyngier wrote: > On Mon, 13 Jul 2026 11:25:44 +0100, > Sneh Mankad wrote: >> >> The next wakeup timer value needs to be set in MPM timer as the arch timer >> interrupt can not wakeup the SoC if after the deepest CPUidle states the >> SoC also enters deepest low power state. >> >> To wakeup the SoC in such scenarios the earliest wakeup time is set in MPM >> timer and the Resource Power Manager (RPM processor) takes care of setting >> the timer in HW. >> >> Add MPM timer programming when CPU cluster enters power collapse. >> >> Signed-off-by: Sneh Mankad >> --- >> drivers/irqchip/irq-qcom-mpm.c | 44 ++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 44 insertions(+) >> >> diff --git a/drivers/irqchip/irq-qcom-mpm.c b/drivers/irqchip/irq-qcom-mpm.c >> index 763eddee99dc4cdd5edab22ce54808528f9ef165..f43c4a1c35f78b6cdae194dc7ae88c5c307ada94 100644 >> --- a/drivers/irqchip/irq-qcom-mpm.c >> +++ b/drivers/irqchip/irq-qcom-mpm.c >> @@ -13,6 +13,7 @@ >> #include >> #include >> #include >> +#include >> #include >> #include >> #include >> @@ -25,6 +26,8 @@ >> #include >> #include >> >> +#include >> + >> /* >> * This is the driver for Qualcomm MPM (MSM Power Manager) interrupt controller, >> * which is commonly found on Qualcomm SoCs built on the RPM architecture. >> @@ -77,6 +80,13 @@ enum qcom_mpm_reg { >> MPM_REG_STATUS, >> }; >> >> +#define USECS_TO_CYCLES(time_usecs) xloops_to_cycles((time_usecs) * 0x10C7UL) >> + >> +static inline unsigned long xloops_to_cycles(u64 xloops) >> +{ >> + return (xloops * loops_per_jiffy * HZ) >> 32; >> +} >> + > > Do we really need arch-specific code to be literally copied from > arm64's delay.c, without any comment or attempt at making it generic? > > Specially after having added the same stuff to rpmh-rsc.c 4 years ago? > > See a pattern here? Agreed Marc, there should be a more generic way to get this information. I will work on it and post. Thanks, Sneh