From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m49225.qiye.163.com (mail-m49225.qiye.163.com [45.254.49.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3B4B524B0; Tue, 13 Aug 2024 07:54:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.225 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723535698; cv=none; b=gXnalSbyNFf4q0FlQtiZYkxLGjUXpOJ/6aiiS/0veqpNEjAzhybjnwBba/ZrdQP/mNCm6yPjJPg/OLYFWONYGUXGHzsKeVp1Ec6saKpBDJVlel7rd+EOl/W+DMFRXT/NdgvGkteYh8mQ9btnS7qDdCHdmK5/KauDappEPJDUQMQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723535698; c=relaxed/simple; bh=QRgfS5FzFQ9nWby74gZ+onoRz/PbMPAyH0vBKL6WPEI=; h=Message-ID:Date:MIME-Version:Cc:Subject:To:References:From: In-Reply-To:Content-Type; b=AzGTI1E/fPLaAcIP0xT/dVGSrxqrlvQW1mEUkuyltRs40fM2ej8rVchO0undQizk/I1/xsp822JAwK640avE7Vch5W2aukiasj0hqzHMLO/tJSxC5+LvKaztKVpgA2WS0BgLHIJvIHXXC3bf+8Daf7dqJUUcMODNZwKK5NCqdR4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=BZheOnnp; arc=none smtp.client-ip=45.254.49.225 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="BZheOnnp" DKIM-Signature: a=rsa-sha256; b=BZheOnnpdPhgXm0LM85wZhawyWDnNS2PmQ7fs4Rd8IWDRuNvmDdFKUCiQC/1l2Ps6ZR6Bf/pzlHYb0nVC7HByvYMVVpDlqzuuH7YX6MW1LgklEnCfOq/Q9O18yFNRYUlCuLuyASBVzcXH6pnp6hyMxkOWTi/AcFscSdZfPY679A=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=+eGUbbqfyIAVWNh2RbP2Of+Y0aBF87hxxFFq/iXNQFA=; h=date:mime-version:subject:message-id:from; Received: from [172.16.12.45] (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTPA id A436D460573; Tue, 13 Aug 2024 15:46:51 +0800 (CST) Message-ID: Date: Tue, 13 Aug 2024 15:46:50 +0800 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Cc: shawn.lin@rock-chips.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Philipp Zabel , Elaine Zhang , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@collabora.com, Finley Xiao , YouMin Chen , Liang Chen , Sugar Zhang Subject: Re: [PATCH v4 3/3] clk: rockchip: Add clock controller for the RK3576 To: Detlev Casanova , linux-kernel@vger.kernel.org References: <20240809125553.3889-1-detlev.casanova@collabora.com> <20240809125553.3889-4-detlev.casanova@collabora.com> Content-Language: en-GB From: Shawn Lin In-Reply-To: <20240809125553.3889-4-detlev.casanova@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQxpOTlZNGBpJH01DHkofQkJWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a914ab4416f03aekunma436d460573 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Mzo6Kgw*FjI#E0o5TDhRKAg0 Sz0KCUtVSlVKTElITkhOSUpIQ0NCVTMWGhIXVQgTGgwVVRcSFTsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUpISkxLQjcG 在 2024/8/9 20:54, Detlev Casanova 写道: > From: Elaine Zhang > > Add the clock and reset tree definitions for the new RK3576 > SoC. > > Signed-off-by: Elaine Zhang > Signed-off-by: Finley Xiao > Signed-off-by: YouMin Chen > Signed-off-by: Liang Chen > Signed-off-by: Sugar Zhang > [rebase, squash and renumber resets] > Signed-off-by: Detlev Casanova Tested-by: Shawn Lin > --- > drivers/clk/rockchip/Kconfig | 7 + > drivers/clk/rockchip/Makefile | 1 + > drivers/clk/rockchip/clk-rk3576.c | 1819 +++++++++++++++++++++++++++++ > drivers/clk/rockchip/clk.h | 53 + > drivers/clk/rockchip/rst-rk3576.c | 652 +++++++++++ > 5 files changed, 2532 insertions(+) > create mode 100644 drivers/clk/rockchip/clk-rk3576.c > create mode 100644 drivers/clk/rockchip/rst-rk3576.c > > diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig > index 9aad86925cd28..f8eb16f170d48 100644 > --- a/drivers/clk/rockchip/Kconfig > +++ b/drivers/clk/rockchip/Kconfig > @@ -100,6 +100,13 @@ config CLK_RK3568 > help > Build the driver for RK3568 Clock Driver. > > +config CLK_RK3576 > + tristate "Rockchip RK3576 clock controller support" > + depends on ARM64 || COMPILE_TEST > + default y > + help > + Build the driver for RK3576 Clock Driver. > + > config CLK_RK3588 > bool "Rockchip RK3588 clock controller support" > depends on ARM64 || COMPILE_TEST > diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile > index 36894f6a7022d..af2ade54a7efa 100644 > --- a/drivers/clk/rockchip/Makefile > +++ b/drivers/clk/rockchip/Makefile > @@ -28,4 +28,5 @@ obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o > obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o > obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o > obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o > +obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o > obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o > diff --git a/drivers/clk/rockchip/clk-rk3576.c b/drivers/clk/rockchip/clk-rk3576.c > new file mode 100644 > index 0000000000000..a578dd88fa931 > --- /dev/null > +++ b/drivers/clk/rockchip/clk-rk3576.c > @@ -0,0 +1,1819 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2023 Rockchip Electronics Co. Ltd. > + * Author: Elaine Zhang > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include "clk.h" > + > +#define RK3576_GRF_SOC_STATUS0 0x600 > +#define RK3576_PMU0_GRF_OSC_CON6 0x18 > + > +enum rk3576_plls { > + bpll, lpll, vpll, aupll, cpll, gpll, ppll, > +}; > + > +static struct rockchip_pll_rate_table rk3576_pll_rates[] = { > + /* _mhz, _p, _m, _s, _k */ > + RK3588_PLL_RATE(2520000000, 2, 210, 0, 0), > + RK3588_PLL_RATE(2496000000, 2, 208, 0, 0), > + RK3588_PLL_RATE(2472000000, 2, 206, 0, 0), > + RK3588_PLL_RATE(2448000000, 2, 204, 0, 0), > + RK3588_PLL_RATE(2424000000, 2, 202, 0, 0), > + RK3588_PLL_RATE(2400000000, 2, 200, 0, 0), > + RK3588_PLL_RATE(2376000000, 2, 198, 0, 0), > + RK3588_PLL_RATE(2352000000, 2, 196, 0, 0), > + RK3588_PLL_RATE(2328000000, 2, 194, 0, 0), > + RK3588_PLL_RATE(2304000000, 2, 192, 0, 0), > + RK3588_PLL_RATE(2280000000, 2, 190, 0, 0), > + RK3588_PLL_RATE(2256000000, 2, 376, 1, 0), > + RK3588_PLL_RATE(2232000000, 2, 372, 1, 0), > + RK3588_PLL_RATE(2208000000, 2, 368, 1, 0), > + RK3588_PLL_RATE(2184000000, 2, 364, 1, 0), > + RK3588_PLL_RATE(2160000000, 2, 360, 1, 0), > + RK3588_PLL_RATE(2136000000, 2, 356, 1, 0), > + RK3588_PLL_RATE(2112000000, 2, 352, 1, 0), > + RK3588_PLL_RATE(2088000000, 2, 348, 1, 0), > + RK3588_PLL_RATE(2064000000, 2, 344, 1, 0), > + RK3588_PLL_RATE(2040000000, 2, 340, 1, 0), > + RK3588_PLL_RATE(2016000000, 2, 336, 1, 0), > + RK3588_PLL_RATE(1992000000, 2, 332, 1, 0), > + RK3588_PLL_RATE(1968000000, 2, 328, 1, 0), > + RK3588_PLL_RATE(1944000000, 2, 324, 1, 0), > + RK3588_PLL_RATE(1920000000, 2, 320, 1, 0), > + RK3588_PLL_RATE(1896000000, 2, 316, 1, 0), > + RK3588_PLL_RATE(1872000000, 2, 312, 1, 0), > + RK3588_PLL_RATE(1848000000, 2, 308, 1, 0), > + RK3588_PLL_RATE(1824000000, 2, 304, 1, 0), > + RK3588_PLL_RATE(1800000000, 2, 300, 1, 0), > + RK3588_PLL_RATE(1776000000, 2, 296, 1, 0), > + RK3588_PLL_RATE(1752000000, 2, 292, 1, 0), > + RK3588_PLL_RATE(1728000000, 2, 288, 1, 0), > + RK3588_PLL_RATE(1704000000, 2, 284, 1, 0), > + RK3588_PLL_RATE(1680000000, 2, 280, 1, 0), > + RK3588_PLL_RATE(1656000000, 2, 276, 1, 0), > + RK3588_PLL_RATE(1632000000, 2, 272, 1, 0), > + RK3588_PLL_RATE(1608000000, 2, 268, 1, 0), > + RK3588_PLL_RATE(1584000000, 2, 264, 1, 0), > + RK3588_PLL_RATE(1560000000, 2, 260, 1, 0), > + RK3588_PLL_RATE(1536000000, 2, 256, 1, 0), > + RK3588_PLL_RATE(1512000000, 2, 252, 1, 0), > + RK3588_PLL_RATE(1488000000, 2, 248, 1, 0), > + RK3588_PLL_RATE(1464000000, 2, 244, 1, 0), > + RK3588_PLL_RATE(1440000000, 2, 240, 1, 0), > + RK3588_PLL_RATE(1416000000, 2, 236, 1, 0), > + RK3588_PLL_RATE(1392000000, 2, 232, 1, 0), > + RK3588_PLL_RATE(1320000000, 2, 220, 1, 0), > + RK3588_PLL_RATE(1200000000, 2, 200, 1, 0), > + RK3588_PLL_RATE(1188000000, 2, 198, 1, 0), > + RK3588_PLL_RATE(1100000000, 3, 550, 2, 0), > + RK3588_PLL_RATE(1008000000, 2, 336, 2, 0), > + RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), > + RK3588_PLL_RATE(983040000, 4, 655, 2, 23592), > + RK3588_PLL_RATE(955520000, 3, 477, 2, 49806), > + RK3588_PLL_RATE(903168000, 6, 903, 2, 11009), > + RK3588_PLL_RATE(900000000, 2, 300, 2, 0), > + RK3588_PLL_RATE(816000000, 2, 272, 2, 0), > + RK3588_PLL_RATE(786432000, 2, 262, 2, 9437), > + RK3588_PLL_RATE(786000000, 1, 131, 2, 0), > + RK3588_PLL_RATE(785560000, 3, 392, 2, 51117), > + RK3588_PLL_RATE(722534400, 8, 963, 2, 24850), > + RK3588_PLL_RATE(600000000, 2, 200, 2, 0), > + RK3588_PLL_RATE(594000000, 2, 198, 2, 0), > + RK3588_PLL_RATE(408000000, 2, 272, 3, 0), > + RK3588_PLL_RATE(312000000, 2, 208, 3, 0), > + RK3588_PLL_RATE(216000000, 2, 288, 4, 0), > + RK3588_PLL_RATE(96000000, 2, 256, 5, 0), > + { /* sentinel */ }, > +}; > + > +static struct rockchip_pll_rate_table rk3576_ppll_rates[] = { > + /* _mhz, _p, _m, _s, _k */ > + RK3588_PLL_RATE(1300000000, 3, 325, 2, 0), > + { /* sentinel */ }, > +}; > + > +#define RK3576_ACLK_M_BIGCORE_DIV_MASK 0x1f > +#define RK3576_ACLK_M_BIGCORE_DIV_SHIFT 0 > +#define RK3576_ACLK_M_LITCORE_DIV_MASK 0x1f > +#define RK3576_ACLK_M_LITCORE_DIV_SHIFT 8 > +#define RK3576_PCLK_DBG_LITCORE_DIV_MASK 0x1f > +#define RK3576_PCLK_DBG_LITCORE_DIV_SHIFT 0 > +#define RK3576_ACLK_CCI_DIV_MASK 0x1f > +#define RK3576_ACLK_CCI_DIV_SHIFT 7 > +#define RK3576_ACLK_CCI_MUX_MASK 0x3 > +#define RK3576_ACLK_CCI_MUX_SHIFT 12 > + > +#define RK3576_BIGCORE_CLKSEL2(_amcore) \ > +{ \ > + .reg = RK3576_BIGCORE_CLKSEL_CON(2), \ > + .val = HIWORD_UPDATE(_amcore - 1, RK3576_ACLK_M_BIGCORE_DIV_MASK, \ > + RK3576_ACLK_M_BIGCORE_DIV_SHIFT), \ > +} > + > +#define RK3576_LITCORE_CLKSEL1(_amcore) \ > +{ \ > + .reg = RK3576_LITCORE_CLKSEL_CON(1), \ > + .val = HIWORD_UPDATE(_amcore - 1, RK3576_ACLK_M_LITCORE_DIV_MASK, \ > + RK3576_ACLK_M_LITCORE_DIV_SHIFT), \ > +} > + > +#define RK3576_LITCORE_CLKSEL2(_pclkdbg) \ > +{ \ > + .reg = RK3576_LITCORE_CLKSEL_CON(2), \ > + .val = HIWORD_UPDATE(_pclkdbg - 1, RK3576_PCLK_DBG_LITCORE_DIV_MASK, \ > + RK3576_PCLK_DBG_LITCORE_DIV_SHIFT), \ > +} > + > +#define RK3576_CCI_CLKSEL4(_ccisel, _div) \ > +{ \ > + .reg = RK3576_CCI_CLKSEL_CON(4), \ > + .val = HIWORD_UPDATE(_ccisel, RK3576_ACLK_CCI_MUX_MASK, \ > + RK3576_ACLK_CCI_MUX_SHIFT) | \ > + HIWORD_UPDATE(_div - 1, RK3576_ACLK_CCI_DIV_MASK, \ > + RK3576_ACLK_CCI_DIV_SHIFT), \ > +} > + > +#define RK3576_CPUBCLK_RATE(_prate, _amcore) \ > +{ \ > + .prate = _prate##U, \ > + .divs = { \ > + RK3576_BIGCORE_CLKSEL2(_amcore), \ > + }, \ > +} > + > +#define RK3576_CPULCLK_RATE(_prate, _amcore, _pclkdbg, _ccisel) \ > +{ \ > + .prate = _prate##U, \ > + .divs = { \ > + RK3576_LITCORE_CLKSEL1(_amcore), \ > + RK3576_LITCORE_CLKSEL2(_pclkdbg), \ > + }, \ > + .pre_muxs = { \ > + RK3576_CCI_CLKSEL4(2, 2), \ > + }, \ > + .post_muxs = { \ > + RK3576_CCI_CLKSEL4(_ccisel, 2), \ > + }, \ > +} > + > +static struct rockchip_cpuclk_rate_table rk3576_cpubclk_rates[] __initdata = { > + RK3576_CPUBCLK_RATE(2496000000, 2), > + RK3576_CPUBCLK_RATE(2400000000, 2), > + RK3576_CPUBCLK_RATE(2304000000, 2), > + RK3576_CPUBCLK_RATE(2208000000, 2), > + RK3576_CPUBCLK_RATE(2184000000, 2), > + RK3576_CPUBCLK_RATE(2088000000, 2), > + RK3576_CPUBCLK_RATE(2040000000, 2), > + RK3576_CPUBCLK_RATE(2016000000, 2), > + RK3576_CPUBCLK_RATE(1992000000, 2), > + RK3576_CPUBCLK_RATE(1896000000, 2), > + RK3576_CPUBCLK_RATE(1800000000, 2), > + RK3576_CPUBCLK_RATE(1704000000, 2), > + RK3576_CPUBCLK_RATE(1608000000, 2), > + RK3576_CPUBCLK_RATE(1584000000, 2), > + RK3576_CPUBCLK_RATE(1560000000, 2), > + RK3576_CPUBCLK_RATE(1536000000, 2), > + RK3576_CPUBCLK_RATE(1512000000, 2), > + RK3576_CPUBCLK_RATE(1488000000, 2), > + RK3576_CPUBCLK_RATE(1464000000, 2), > + RK3576_CPUBCLK_RATE(1440000000, 2), > + RK3576_CPUBCLK_RATE(1416000000, 2), > + RK3576_CPUBCLK_RATE(1392000000, 2), > + RK3576_CPUBCLK_RATE(1368000000, 2), > + RK3576_CPUBCLK_RATE(1344000000, 2), > + RK3576_CPUBCLK_RATE(1320000000, 2), > + RK3576_CPUBCLK_RATE(1296000000, 2), > + RK3576_CPUBCLK_RATE(1272000000, 2), > + RK3576_CPUBCLK_RATE(1248000000, 2), > + RK3576_CPUBCLK_RATE(1224000000, 2), > + RK3576_CPUBCLK_RATE(1200000000, 2), > + RK3576_CPUBCLK_RATE(1104000000, 2), > + RK3576_CPUBCLK_RATE(1008000000, 2), > + RK3576_CPUBCLK_RATE(912000000, 2), > + RK3576_CPUBCLK_RATE(816000000, 2), > + RK3576_CPUBCLK_RATE(696000000, 2), > + RK3576_CPUBCLK_RATE(600000000, 2), > + RK3576_CPUBCLK_RATE(408000000, 2), > + RK3576_CPUBCLK_RATE(312000000, 2), > + RK3576_CPUBCLK_RATE(216000000, 2), > + RK3576_CPUBCLK_RATE(96000000, 2), > +}; > + > +static const struct rockchip_cpuclk_reg_data rk3576_cpubclk_data = { > + .core_reg[0] = RK3576_BIGCORE_CLKSEL_CON(1), > + .div_core_shift[0] = 7, > + .div_core_mask[0] = 0x1f, > + .num_cores = 1, > + .mux_core_alt = 1, > + .mux_core_main = 0, > + .mux_core_shift = 12, > + .mux_core_mask = 0x3, > +}; > + > +static struct rockchip_cpuclk_rate_table rk3576_cpulclk_rates[] __initdata = { > + RK3576_CPULCLK_RATE(2400000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(2304000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(2208000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(2184000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(2088000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(2040000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(2016000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1992000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1896000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1800000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1704000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1608000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1584000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1560000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1536000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1512000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1488000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1464000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1440000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1416000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1392000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1368000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1344000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1320000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1296000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1272000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1248000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1224000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1200000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(1104000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(1008000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(912000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(816000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(696000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(600000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(408000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(312000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(216000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(96000000, 2, 6, 2), > +}; > + > +static const struct rockchip_cpuclk_reg_data rk3576_cpulclk_data = { > + .core_reg[0] = RK3576_LITCORE_CLKSEL_CON(0), > + .div_core_shift[0] = 7, > + .div_core_mask[0] = 0x1f, > + .num_cores = 1, > + .mux_core_alt = 1, > + .mux_core_main = 0, > + .mux_core_shift = 12, > + .mux_core_mask = 0x3, > +}; > + > +#define MFLAGS CLK_MUX_HIWORD_MASK > +#define DFLAGS CLK_DIVIDER_HIWORD_MASK > +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) > + > +PNAME(mux_pll_p) = { "xin24m", "xin32k" }; > +PNAME(mux_24m_32k_p) = { "xin24m", "xin_osc0_div" }; > +PNAME(mux_armclkl_p) = { "xin24m", "pll_lpll", "lpll" }; > +PNAME(mux_armclkb_p) = { "xin24m", "pll_bpll", "bpll" }; > +PNAME(gpll_24m_p) = { "gpll", "xin24m" }; > +PNAME(cpll_24m_p) = { "cpll", "xin24m" }; > +PNAME(gpll_cpll_p) = { "gpll", "cpll" }; > +PNAME(gpll_spll_p) = { "gpll", "spll" }; > +PNAME(gpll_cpll_aupll_p) = { "gpll", "cpll", "aupll" }; > +PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m" }; > +PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" }; > +PNAME(gpll_cpll_aupll_24m_p) = { "gpll", "cpll", "aupll", "xin24m" }; > +PNAME(gpll_cpll_aupll_spll_p) = { "gpll", "cpll", "aupll", "spll" }; > +PNAME(gpll_cpll_aupll_spll_lpll_p) = { "gpll", "cpll", "aupll", "spll", "lpll_dummy" }; > +PNAME(gpll_cpll_spll_bpll_p) = { "gpll", "cpll", "spll", "bpll_dummy" }; > +PNAME(gpll_cpll_lpll_bpll_p) = { "gpll", "cpll", "lpll_dummy", "bpll_dummy" }; > +PNAME(gpll_spll_cpll_bpll_lpll_p) = { "gpll", "spll", "cpll", "bpll_dummy", "lpll_dummy" }; > +PNAME(gpll_cpll_vpll_aupll_24m_p) = { "gpll", "cpll", "vpll", "aupll", "xin24m" }; > +PNAME(gpll_cpll_spll_aupll_bpll_p) = { "gpll", "cpll", "spll", "aupll", "bpll_dummy" }; > +PNAME(gpll_cpll_spll_bpll_lpll_p) = { "gpll", "cpll", "spll", "bpll_dummy", "lpll_dummy" }; > +PNAME(gpll_cpll_spll_lpll_bpll_p) = { "gpll", "cpll", "spll", "lpll_dummy", "bpll_dummy" }; > +PNAME(gpll_cpll_vpll_bpll_lpll_p) = { "gpll", "cpll", "vpll", "bpll_dummy", "lpll_dummy" }; > +PNAME(gpll_spll_aupll_bpll_lpll_p) = { "gpll", "spll", "aupll", "bpll_dummy", "lpll_dummy" }; > +PNAME(gpll_spll_isppvtpll_bpll_lpll_p) = { "gpll", "spll", "isp_pvtpll", "bpll_dummy", "lpll_dummy" }; > +PNAME(gpll_cpll_spll_aupll_lpll_24m_p) = { "gpll", "cpll", "spll", "aupll", "lpll_dummy", "xin24m" }; > +PNAME(gpll_cpll_spll_vpll_bpll_lpll_p) = { "gpll", "cpll", "spll", "vpll", "bpll_dummy", "lpll_dummy" }; > +PNAME(cpll_vpll_lpll_bpll_p) = { "cpll", "vpll", "lpll_dummy", "bpll_dummy" }; > +PNAME(mux_24m_ccipvtpll_gpll_lpll_p) = { "xin24m", "cci_pvtpll", "gpll", "lpll" }; > +PNAME(mux_24m_spll_gpll_cpll_p) = {"xin24m", "spll", "gpll", "cpll" }; > +PNAME(audio_frac_int_p) = { "xin24m", "clk_audio_frac_0", "clk_audio_frac_1", "clk_audio_frac_2", > + "clk_audio_frac_3", "clk_audio_int_0", "clk_audio_int_1", "clk_audio_int_2" }; > +PNAME(audio_frac_p) = { "clk_audio_frac_0", "clk_audio_frac_1", "clk_audio_frac_2", "clk_audio_frac_3" }; > +PNAME(mux_100m_24m_p) = { "clk_cpll_div10", "xin24m" }; > +PNAME(mux_100m_50m_24m_p) = { "clk_cpll_div10", "clk_cpll_div20", "xin24m" }; > +PNAME(mux_100m_24m_lclk0_p) = { "clk_cpll_div10", "xin24m", "lclk_asrc_src_0" }; > +PNAME(mux_100m_24m_lclk1_p) = { "clk_cpll_div10", "xin24m", "lclk_asrc_src_1" }; > +PNAME(mux_150m_100m_50m_24m_p) = { "clk_gpll_div8", "clk_cpll_div10", "clk_cpll_div20", "xin24m" }; > +PNAME(mux_200m_100m_50m_24m_p) = { "clk_gpll_div6", "clk_cpll_div10", "clk_cpll_div20", "xin24m" }; > +PNAME(mux_400m_200m_100m_24m_p) = { "clk_gpll_div3", "clk_gpll_div6", "clk_cpll_div10", "xin24m" }; > +PNAME(mux_500m_250m_100m_24m_p) = { "clk_cpll_div2", "clk_cpll_div4", "clk_cpll_div10", "xin24m" }; > +PNAME(mux_600m_400m_300m_24m_p) = { "clk_gpll_div2", "clk_gpll_div3", "clk_gpll_div4", "xin24m" }; > +PNAME(mux_350m_175m_116m_24m_p) = { "clk_spll_div2", "clk_spll_div4", "clk_spll_div6", "xin24m" }; > +PNAME(mux_175m_116m_58m_24m_p) = { "clk_spll_div4", "clk_spll_div6", "clk_spll_div12", "xin24m" }; > +PNAME(mux_116m_58m_24m_p) = { "clk_spll_div6", "clk_spll_div12", "xin24m" }; > +PNAME(mclk_sai0_8ch_p) = { "mclk_sai0_8ch_src", "sai0_mclkin", "sai1_mclkin" }; > +PNAME(mclk_sai1_8ch_p) = { "mclk_sai1_8ch_src", "sai1_mclkin" }; > +PNAME(mclk_sai2_2ch_p) = { "mclk_sai2_2ch_src", "sai2_mclkin", "sai1_mclkin" }; > +PNAME(mclk_sai3_2ch_p) = { "mclk_sai3_2ch_src", "sai3_mclkin", "sai1_mclkin" }; > +PNAME(mclk_sai4_2ch_p) = { "mclk_sai4_2ch_src", "sai4_mclkin", "sai1_mclkin" }; > +PNAME(mclk_sai5_8ch_p) = { "mclk_sai5_8ch_src", "sai1_mclkin" }; > +PNAME(mclk_sai6_8ch_p) = { "mclk_sai6_8ch_src", "sai1_mclkin" }; > +PNAME(mclk_sai7_8ch_p) = { "mclk_sai7_8ch_src", "sai1_mclkin" }; > +PNAME(mclk_sai8_8ch_p) = { "mclk_sai8_8ch_src", "sai1_mclkin" }; > +PNAME(mclk_sai9_8ch_p) = { "mclk_sai9_8ch_src", "sai1_mclkin" }; > +PNAME(uart1_p) = { "clk_uart1_src_top", "xin24m" }; > +PNAME(pdm0_p) = { "clk_pdm0_src_top", "xin24m" }; > +PNAME(mclk_pdm0_p) = { "mclk_pdm0_src_top", "xin24m" }; > +PNAME(clk_gmac1_ptp_ref_src_p) = { "gpll", "cpll", "gmac1_ptp_refclk_in" }; > +PNAME(clk_gmac0_ptp_ref_src_p) = { "gpll", "cpll", "gmac0_ptp_refclk_in" }; > +PNAME(dclk_ebc_p) = { "gpll", "cpll", "vpll", "aupll", "lpll_dummy", > + "dclk_ebc_frac", "xin24m" }; > +PNAME(dclk_vp0_p) = { "dclk_vp0_src", "clk_hdmiphy_pixel0" }; > +PNAME(dclk_vp1_p) = { "dclk_vp1_src", "clk_hdmiphy_pixel0" }; > +PNAME(dclk_vp2_p) = { "dclk_vp2_src", "clk_hdmiphy_pixel0" }; > +PNAME(clk_uart_p) = { "gpll", "cpll", "aupll", "xin24m", "clk_uart_frac_0", > + "clk_uart_frac_1", "clk_uart_frac_2"}; > +PNAME(clk_freq_pwm1_p) = { "sai0_mclkin", "sai1_mclkin", "sai2_mclkin", > + "sai3_mclkin", "sai4_mclkin", "sai_sclkin_freq"}; > +PNAME(clk_counter_pwm1_p) = { "sai0_mclkin", "sai1_mclkin", "sai2_mclkin", > + "sai3_mclkin", "sai4_mclkin", "sai_sclkin_counter"}; > +PNAME(sai_sclkin_freq_p) = { "sai0_sclk_in", "sai1_sclk_in", "sai2_sclk_in", > + "sai3_sclk_in", "sai4_sclk_in"}; > +PNAME(clk_ref_pcie0_phy_p) = { "clk_pcie_100m_src", "clk_pcie_100m_nduty_src", > + "xin24m"}; > +PNAME(hclk_vi_root_p) = { "clk_gpll_div6", "clk_cpll_div10", > + "aclk_vi_root_inter", "xin24m"}; > +PNAME(clk_ref_osc_mphy_p) = { "xin24m", "clk_gpio_mphy_i", "clk_ref_mphy_26m"}; > +PNAME(mux_pmu200m_pmu100m_pmu50m_24m_p) = { "clk_200m_pmu_src", "clk_100m_pmu_src", > + "clk_50m_pmu_src", "xin24m" }; > +PNAME(mux_pmu100m_pmu50m_24m_p) = { "clk_100m_pmu_src", "clk_50m_pmu_src", "xin24m" }; > +PNAME(mux_pmu100m_24m_32k_p) = { "clk_100m_pmu_src", "xin24m", "xin_osc0_div" }; > +PNAME(clk_phy_ref_src_p) = { "xin24m", "clk_pmuphy_ref_src" }; > +PNAME(clk_usbphy_ref_src_p) = { "usbphy0_24m", "usbphy1_24m" }; > +PNAME(clk_cpll_ref_src_p) = { "xin24m", "clk_usbphy_ref_src" }; > +PNAME(clk_aupll_ref_src_p) = { "xin24m", "clk_aupll_ref_io" }; > + > +static struct rockchip_pll_clock rk3576_pll_clks[] __initdata = { > + [bpll] = PLL(pll_rk3588_core, PLL_BPLL, "bpll", mux_pll_p, > + 0, RK3576_PLL_CON(0), > + RK3576_BPLL_MODE_CON0, 0, 15, 0, rk3576_pll_rates), > + [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p, > + 0, RK3576_LPLL_CON(16), > + RK3576_LPLL_MODE_CON0, 0, 15, 0, rk3576_pll_rates), > + [vpll] = PLL(pll_rk3588, PLL_VPLL, "vpll", mux_pll_p, > + 0, RK3576_PLL_CON(88), > + RK3576_MODE_CON0, 4, 15, 0, rk3576_pll_rates), > + [aupll] = PLL(pll_rk3588, PLL_AUPLL, "aupll", mux_pll_p, > + 0, RK3576_PLL_CON(96), > + RK3576_MODE_CON0, 6, 15, 0, rk3576_pll_rates), > + [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p, > + CLK_IGNORE_UNUSED, RK3576_PLL_CON(104), > + RK3576_MODE_CON0, 8, 15, 0, rk3576_pll_rates), > + [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p, > + CLK_IGNORE_UNUSED, RK3576_PLL_CON(112), > + RK3576_MODE_CON0, 2, 15, 0, rk3576_pll_rates), > + [ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p, > + CLK_IGNORE_UNUSED, RK3576_PMU_PLL_CON(128), > + RK3576_MODE_CON0, 10, 15, 0, rk3576_ppll_rates), > +}; > + > +static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = { > + /* > + * CRU Clock-Architecture > + */ > + /* fixed */ > + FACTOR(0, "xin12m", "xin24m", 0, 1, 2), > + > + COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IS_CRITICAL, > + RK3576_PMU_CLKSEL_CON(21), 0, > + RK3576_PMU_CLKGATE_CON(7), 11, GFLAGS), > + > + FACTOR(0, "clk_spll_div12", "spll", 0, 1, 12), > + FACTOR(0, "clk_spll_div6", "spll", 0, 1, 6), > + FACTOR(0, "clk_spll_div4", "spll", 0, 1, 4), > + FACTOR(0, "lpll_div2", "lpll", 0, 1, 2), > + FACTOR(0, "bpll_div4", "bpll", 0, 1, 4), > + > + /* top */ > + COMPOSITE(CLK_CPLL_DIV20, "clk_cpll_div20", gpll_cpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 0, GFLAGS), > + COMPOSITE(CLK_CPLL_DIV10, "clk_cpll_div10", gpll_cpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 1, GFLAGS), > + COMPOSITE(CLK_GPLL_DIV8, "clk_gpll_div8", gpll_cpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 2, GFLAGS), > + COMPOSITE(CLK_GPLL_DIV6, "clk_gpll_div6", gpll_cpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 3, GFLAGS), > + COMPOSITE(CLK_CPLL_DIV4, "clk_cpll_div4", gpll_cpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 4, GFLAGS), > + COMPOSITE(CLK_GPLL_DIV4, "clk_gpll_div4", gpll_cpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 5, GFLAGS), > + COMPOSITE(CLK_SPLL_DIV2, "clk_spll_div2", gpll_cpll_spll_bpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(3), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 6, GFLAGS), > + COMPOSITE(CLK_GPLL_DIV3, "clk_gpll_div3", gpll_cpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(3), 12, 1, MFLAGS, 7, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 7, GFLAGS), > + COMPOSITE(CLK_CPLL_DIV2, "clk_cpll_div2", gpll_cpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 9, GFLAGS), > + COMPOSITE(CLK_GPLL_DIV2, "clk_gpll_div2", gpll_cpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 10, GFLAGS), > + COMPOSITE(CLK_SPLL_DIV1, "clk_spll_div1", gpll_cpll_spll_bpll_lpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(6), 5, 3, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 12, GFLAGS), > + COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(8), 7, 2, MFLAGS, > + RK3576_CLKGATE_CON(1), 1, GFLAGS), > + COMPOSITE(ACLK_TOP, "aclk_top", gpll_cpll_aupll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(9), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(1), 3, GFLAGS), > + COMPOSITE(ACLK_TOP_MID, "aclk_top_mid", gpll_cpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(10), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(1), 6, GFLAGS), > + COMPOSITE(ACLK_SECURE_HIGH, "aclk_secure_high", gpll_spll_aupll_bpll_lpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(10), 11, 3, MFLAGS, 6, 5, DFLAGS, > + RK3576_CLKGATE_CON(1), 7, GFLAGS), > + COMPOSITE_NODIV(HCLK_TOP, "hclk_top", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(19), 2, 2, MFLAGS, > + RK3576_CLKGATE_CON(1), 14, GFLAGS), > + COMPOSITE_NODIV(HCLK_VO0VOP_CHANNEL, "hclk_vo0vop_channel", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(19), 6, 2, MFLAGS, > + RK3576_CLKGATE_CON(2), 0, GFLAGS), > + COMPOSITE(ACLK_VO0VOP_CHANNEL, "aclk_vo0vop_channel", gpll_cpll_lpll_bpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(19), 12, 2, MFLAGS, 8, 4, DFLAGS, > + RK3576_CLKGATE_CON(2), 1, GFLAGS), > + MUX(CLK_AUDIO_FRAC_0_SRC, "clk_audio_frac_0_src", gpll_cpll_aupll_24m_p, 0, > + RK3576_CLKSEL_CON(13), 0, 2, MFLAGS), > + COMPOSITE_FRAC(CLK_AUDIO_FRAC_0, "clk_audio_frac_0", "clk_audio_frac_0_src", 0, > + RK3576_CLKSEL_CON(12), 0, > + RK3576_CLKGATE_CON(1), 10, GFLAGS), > + MUX(CLK_AUDIO_FRAC_1_SRC, "clk_audio_frac_1_src", gpll_cpll_aupll_24m_p, 0, > + RK3576_CLKSEL_CON(15), 0, 2, MFLAGS), > + COMPOSITE_FRAC(CLK_AUDIO_FRAC_1, "clk_audio_frac_1", "clk_audio_frac_1_src", 0, > + RK3576_CLKSEL_CON(14), 0, > + RK3576_CLKGATE_CON(1), 11, GFLAGS), > + MUX(CLK_AUDIO_FRAC_2_SRC, "clk_audio_frac_2_src", gpll_cpll_aupll_24m_p, 0, > + RK3576_CLKSEL_CON(17), 0, 2, MFLAGS), > + COMPOSITE_FRAC(CLK_AUDIO_FRAC_2, "clk_audio_frac_2", "clk_audio_frac_2_src", 0, > + RK3576_CLKSEL_CON(16), 0, > + RK3576_CLKGATE_CON(1), 12, GFLAGS), > + MUX(CLK_AUDIO_FRAC_3_SRC, "clk_audio_frac_3_src", gpll_cpll_aupll_24m_p, 0, > + RK3576_CLKSEL_CON(19), 0, 2, MFLAGS), > + COMPOSITE_FRAC(CLK_AUDIO_FRAC_3, "clk_audio_frac_3", "clk_audio_frac_3_src", 0, > + RK3576_CLKSEL_CON(18), 0, > + RK3576_CLKGATE_CON(1), 13, GFLAGS), > + MUX(0, "clk_uart_frac_0_src", gpll_cpll_aupll_24m_p, 0, > + RK3576_CLKSEL_CON(22), 0, 2, MFLAGS), > + COMPOSITE_FRAC(CLK_UART_FRAC_0, "clk_uart_frac_0", "clk_uart_frac_0_src", 0, > + RK3576_CLKSEL_CON(21), 0, > + RK3576_CLKGATE_CON(2), 5, GFLAGS), > + MUX(0, "clk_uart_frac_1_src", gpll_cpll_aupll_24m_p, 0, > + RK3576_CLKSEL_CON(24), 0, 2, MFLAGS), > + COMPOSITE_FRAC(CLK_UART_FRAC_1, "clk_uart_frac_1", "clk_uart_frac_1_src", 0, > + RK3576_CLKSEL_CON(23), 0, > + RK3576_CLKGATE_CON(2), 6, GFLAGS), > + MUX(0, "clk_uart_frac_2_src", gpll_cpll_aupll_24m_p, 0, > + RK3576_CLKSEL_CON(26), 0, 2, MFLAGS), > + COMPOSITE_FRAC(CLK_UART_FRAC_2, "clk_uart_frac_2", "clk_uart_frac_2_src", 0, > + RK3576_CLKSEL_CON(25), 0, > + RK3576_CLKGATE_CON(2), 7, GFLAGS), > + COMPOSITE(CLK_UART1_SRC_TOP, "clk_uart1_src_top", clk_uart_p, 0, > + RK3576_CLKSEL_CON(27), 13, 3, MFLAGS, 5, 8, DFLAGS, > + RK3576_CLKGATE_CON(2), 13, GFLAGS), > + COMPOSITE_NOMUX(CLK_AUDIO_INT_0, "clk_audio_int_0", "gpll", 0, > + RK3576_CLKSEL_CON(28), 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(2), 14, GFLAGS), > + COMPOSITE_NOMUX(CLK_AUDIO_INT_1, "clk_audio_int_1", "cpll", 0, > + RK3576_CLKSEL_CON(28), 5, 5, DFLAGS, > + RK3576_CLKGATE_CON(2), 15, GFLAGS), > + COMPOSITE_NOMUX(CLK_AUDIO_INT_2, "clk_audio_int_2", "aupll", 0, > + RK3576_CLKSEL_CON(28), 10, 5, DFLAGS, > + RK3576_CLKGATE_CON(3), 0, GFLAGS), > + COMPOSITE(CLK_PDM0_SRC_TOP, "clk_pdm0_src_top", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(29), 9, 3, MFLAGS, 0, 9, DFLAGS, > + RK3576_CLKGATE_CON(3), 2, GFLAGS), > + COMPOSITE_NOMUX(CLK_GMAC0_125M_SRC, "clk_gmac0_125m_src", "cpll", 0, > + RK3576_CLKSEL_CON(30), 10, 5, DFLAGS, > + RK3576_CLKGATE_CON(3), 6, GFLAGS), > + COMPOSITE_NOMUX(CLK_GMAC1_125M_SRC, "clk_gmac1_125m_src", "cpll", 0, > + RK3576_CLKSEL_CON(31), 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(3), 7, GFLAGS), > + COMPOSITE(LCLK_ASRC_SRC_0, "lclk_asrc_src_0", audio_frac_p, 0, > + RK3576_CLKSEL_CON(31), 10, 2, MFLAGS, 5, 5, DFLAGS, > + RK3576_CLKGATE_CON(3), 10, GFLAGS), > + COMPOSITE(LCLK_ASRC_SRC_1, "lclk_asrc_src_1", audio_frac_p, 0, > + RK3576_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(3), 11, GFLAGS), > + COMPOSITE(REF_CLK0_OUT_PLL, "ref_clk0_out_pll", gpll_cpll_spll_aupll_lpll_24m_p, 0, > + RK3576_CLKSEL_CON(33), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(4), 1, GFLAGS), > + COMPOSITE(REF_CLK1_OUT_PLL, "ref_clk1_out_pll", gpll_cpll_spll_aupll_lpll_24m_p, 0, > + RK3576_CLKSEL_CON(34), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(4), 2, GFLAGS), > + COMPOSITE(REF_CLK2_OUT_PLL, "ref_clk2_out_pll", gpll_cpll_spll_aupll_lpll_24m_p, 0, > + RK3576_CLKSEL_CON(35), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(4), 3, GFLAGS), > + COMPOSITE(REFCLKO25M_GMAC0_OUT, "refclko25m_gmac0_out", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 7, DFLAGS, > + RK3576_CLKGATE_CON(5), 10, GFLAGS), > + COMPOSITE(REFCLKO25M_GMAC1_OUT, "refclko25m_gmac1_out", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(36), 15, 1, MFLAGS, 8, 7, DFLAGS, > + RK3576_CLKGATE_CON(5), 11, GFLAGS), > + COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0, > + RK3576_CLKSEL_CON(37), 8, 2, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(5), 12, GFLAGS), > + GATE(CLK_GMAC0_RMII_CRU, "clk_gmac0_rmii_cru", "clk_cpll_div20", 0, > + RK3576_CLKGATE_CON(5), 13, GFLAGS), > + GATE(CLK_GMAC1_RMII_CRU, "clk_gmac1_rmii_cru", "clk_cpll_div20", 0, > + RK3576_CLKGATE_CON(5), 14, GFLAGS), > + GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0, > + RK3576_CLKGATE_CON(5), 15, GFLAGS), > + COMPOSITE(CLK_MIPI_CAMERAOUT_M0, "clk_mipi_cameraout_m0", mux_24m_spll_gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(38), 8, 2, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(6), 3, GFLAGS), > + COMPOSITE(CLK_MIPI_CAMERAOUT_M1, "clk_mipi_cameraout_m1", mux_24m_spll_gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(39), 8, 2, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(6), 4, GFLAGS), > + COMPOSITE(CLK_MIPI_CAMERAOUT_M2, "clk_mipi_cameraout_m2", mux_24m_spll_gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(40), 8, 2, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(6), 5, GFLAGS), > + COMPOSITE(MCLK_PDM0_SRC_TOP, "mclk_pdm0_src_top", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(41), 7, 3, MFLAGS, 2, 5, DFLAGS, > + RK3576_CLKGATE_CON(6), 8, GFLAGS), > + > + /* bus */ > + COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(55), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(11), 0, GFLAGS), > + COMPOSITE_NODIV(PCLK_BUS_ROOT, "pclk_bus_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(55), 2, 2, MFLAGS, > + RK3576_CLKGATE_CON(11), 1, GFLAGS), > + COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(55), 9, 1, MFLAGS, 4, 5, DFLAGS, > + RK3576_CLKGATE_CON(11), 2, GFLAGS), > + GATE(HCLK_CAN0, "hclk_can0", "hclk_bus_root", 0, > + RK3576_CLKGATE_CON(11), 6, GFLAGS), > + COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_24m_p, 0, > + RK3576_CLKSEL_CON(56), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(11), 7, GFLAGS), > + GATE(HCLK_CAN1, "hclk_can1", "hclk_bus_root", 0, > + RK3576_CLKGATE_CON(11), 8, GFLAGS), > + COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_24m_p, 0, > + RK3576_CLKSEL_CON(56), 12, 2, MFLAGS, 7, 5, DFLAGS, > + RK3576_CLKGATE_CON(11), 9, GFLAGS), > + GATE(CLK_KEY_SHIFT, "clk_key_shift", "xin24m", CLK_IS_CRITICAL, > + RK3576_CLKGATE_CON(11), 15, GFLAGS), > + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 0, GFLAGS), > + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 1, GFLAGS), > + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 2, GFLAGS), > + GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 3, GFLAGS), > + GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 4, GFLAGS), > + GATE(PCLK_I2C6, "pclk_i2c6", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 5, GFLAGS), > + GATE(PCLK_I2C7, "pclk_i2c7", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 6, GFLAGS), > + GATE(PCLK_I2C8, "pclk_i2c8", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 7, GFLAGS), > + GATE(PCLK_I2C9, "pclk_i2c9", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 8, GFLAGS), > + GATE(PCLK_WDT_BUSMCU, "pclk_wdt_busmcu", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 9, GFLAGS), > + GATE(TCLK_WDT_BUSMCU, "tclk_wdt_busmcu", "xin24m", 0, > + RK3576_CLKGATE_CON(12), 10, GFLAGS), > + GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL, > + RK3576_CLKGATE_CON(12), 11, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(57), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(12), 12, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(57), 2, 2, MFLAGS, > + RK3576_CLKGATE_CON(12), 13, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(57), 4, 2, MFLAGS, > + RK3576_CLKGATE_CON(12), 14, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(57), 6, 2, MFLAGS, > + RK3576_CLKGATE_CON(12), 15, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(57), 8, 2, MFLAGS, > + RK3576_CLKGATE_CON(13), 0, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(57), 10, 2, MFLAGS, > + RK3576_CLKGATE_CON(13), 1, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(57), 12, 2, MFLAGS, > + RK3576_CLKGATE_CON(13), 2, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C8, "clk_i2c8", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(57), 14, 2, MFLAGS, > + RK3576_CLKGATE_CON(13), 3, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C9, "clk_i2c9", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(58), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(13), 4, GFLAGS), > + GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(13), 6, GFLAGS), > + COMPOSITE(CLK_SARADC, "clk_saradc", gpll_24m_p, 0, > + RK3576_CLKSEL_CON(58), 12, 1, MFLAGS, 4, 8, DFLAGS, > + RK3576_CLKGATE_CON(13), 7, GFLAGS), > + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(13), 8, GFLAGS), > + COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0, > + RK3576_CLKSEL_CON(59), 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(13), 9, GFLAGS), > + GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(13), 10, GFLAGS), > + GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(13), 11, GFLAGS), > + GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(13), 12, GFLAGS), > + GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(13), 13, GFLAGS), > + GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(13), 14, GFLAGS), > + GATE(PCLK_UART6, "pclk_uart6", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(13), 15, GFLAGS), > + GATE(PCLK_UART7, "pclk_uart7", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(14), 0, GFLAGS), > + GATE(PCLK_UART8, "pclk_uart8", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(14), 1, GFLAGS), > + GATE(PCLK_UART9, "pclk_uart9", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(14), 2, GFLAGS), > + GATE(PCLK_UART10, "pclk_uart10", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(14), 3, GFLAGS), > + GATE(PCLK_UART11, "pclk_uart11", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(14), 4, GFLAGS), > + COMPOSITE(SCLK_UART0, "sclk_uart0", clk_uart_p, 0, > + RK3576_CLKSEL_CON(60), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(14), 5, GFLAGS), > + COMPOSITE(SCLK_UART2, "sclk_uart2", clk_uart_p, 0, > + RK3576_CLKSEL_CON(61), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(14), 6, GFLAGS), > + COMPOSITE(SCLK_UART3, "sclk_uart3", clk_uart_p, 0, > + RK3576_CLKSEL_CON(62), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(14), 9, GFLAGS), > + COMPOSITE(SCLK_UART4, "sclk_uart4", clk_uart_p, 0, > + RK3576_CLKSEL_CON(63), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(14), 12, GFLAGS), > + COMPOSITE(SCLK_UART5, "sclk_uart5", clk_uart_p, 0, > + RK3576_CLKSEL_CON(64), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(14), 15, GFLAGS), > + COMPOSITE(SCLK_UART6, "sclk_uart6", clk_uart_p, 0, > + RK3576_CLKSEL_CON(65), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(15), 2, GFLAGS), > + COMPOSITE(SCLK_UART7, "sclk_uart7", clk_uart_p, 0, > + RK3576_CLKSEL_CON(66), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(15), 5, GFLAGS), > + COMPOSITE(SCLK_UART8, "sclk_uart8", clk_uart_p, 0, > + RK3576_CLKSEL_CON(67), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(15), 8, GFLAGS), > + COMPOSITE(SCLK_UART9, "sclk_uart9", clk_uart_p, 0, > + RK3576_CLKSEL_CON(68), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(15), 9, GFLAGS), > + COMPOSITE(SCLK_UART10, "sclk_uart10", clk_uart_p, 0, > + RK3576_CLKSEL_CON(69), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(15), 10, GFLAGS), > + COMPOSITE(SCLK_UART11, "sclk_uart11", clk_uart_p, 0, > + RK3576_CLKSEL_CON(70), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(15), 11, GFLAGS), > + GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(15), 13, GFLAGS), > + GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(15), 14, GFLAGS), > + GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(15), 15, GFLAGS), > + GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(16), 0, GFLAGS), > + GATE(PCLK_SPI4, "pclk_spi4", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(16), 1, GFLAGS), > + COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(70), 13, 2, MFLAGS, > + RK3576_CLKGATE_CON(16), 2, GFLAGS), > + COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(71), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(16), 3, GFLAGS), > + COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(71), 2, 2, MFLAGS, > + RK3576_CLKGATE_CON(16), 4, GFLAGS), > + COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(71), 4, 2, MFLAGS, > + RK3576_CLKGATE_CON(16), 5, GFLAGS), > + COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(71), 6, 2, MFLAGS, > + RK3576_CLKGATE_CON(16), 6, GFLAGS), > + GATE(PCLK_WDT0, "pclk_wdt0", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(16), 7, GFLAGS), > + GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0, > + RK3576_CLKGATE_CON(16), 8, GFLAGS), > + GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(16), 10, GFLAGS), > + COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(71), 8, 2, MFLAGS, > + RK3576_CLKGATE_CON(16), 11, GFLAGS), > + GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0, > + RK3576_CLKGATE_CON(16), 13, GFLAGS), > + GATE(CLK_RC_PWM1, "clk_rc_pwm1", "clk_pvtm_clkout", 0, > + RK3576_CLKGATE_CON(16), 15, GFLAGS), > + GATE(PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(17), 3, GFLAGS), > + GATE(PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(17), 4, GFLAGS), > + COMPOSITE_NODIV(CLK_TIMER0_ROOT, "clk_timer0_root", mux_100m_24m_p, 0, > + RK3576_CLKSEL_CON(71), 14, 1, MFLAGS, > + RK3576_CLKGATE_CON(17), 5, GFLAGS), > + GATE(CLK_TIMER0, "clk_timer0", "clk_timer0_root", 0, > + RK3576_CLKGATE_CON(17), 6, GFLAGS), > + GATE(CLK_TIMER1, "clk_timer1", "clk_timer0_root", 0, > + RK3576_CLKGATE_CON(17), 7, GFLAGS), > + GATE(CLK_TIMER2, "clk_timer2", "clk_timer0_root", 0, > + RK3576_CLKGATE_CON(17), 8, GFLAGS), > + GATE(CLK_TIMER3, "clk_timer3", "clk_timer0_root", 0, > + RK3576_CLKGATE_CON(17), 9, GFLAGS), > + GATE(CLK_TIMER4, "clk_timer4", "clk_timer0_root", 0, > + RK3576_CLKGATE_CON(17), 10, GFLAGS), > + GATE(CLK_TIMER5, "clk_timer5", "clk_timer0_root", 0, > + RK3576_CLKGATE_CON(17), 11, GFLAGS), > + GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(17), 13, GFLAGS), > + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(17), 15, GFLAGS), > + GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0, > + RK3576_CLKGATE_CON(18), 0, GFLAGS), > + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(18), 1, GFLAGS), > + GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0, > + RK3576_CLKGATE_CON(18), 2, GFLAGS), > + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(18), 3, GFLAGS), > + GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0, > + RK3576_CLKGATE_CON(18), 4, GFLAGS), > + GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(18), 5, GFLAGS), > + GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0, > + RK3576_CLKGATE_CON(18), 6, GFLAGS), > + GATE(ACLK_DECOM, "aclk_decom", "aclk_bus_root", 0, > + RK3576_CLKGATE_CON(18), 7, GFLAGS), > + GATE(PCLK_DECOM, "pclk_decom", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(18), 8, GFLAGS), > + COMPOSITE(DCLK_DECOM, "dclk_decom", gpll_spll_p, 0, > + RK3576_CLKSEL_CON(72), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(18), 9, GFLAGS), > + COMPOSITE_NODIV(CLK_TIMER1_ROOT, "clk_timer1_root", mux_100m_24m_p, 0, > + RK3576_CLKSEL_CON(72), 6, 1, MFLAGS, > + RK3576_CLKGATE_CON(18), 10, GFLAGS), > + GATE(CLK_TIMER6, "clk_timer6", "clk_timer1_root", 0, > + RK3576_CLKGATE_CON(18), 11, GFLAGS), > + COMPOSITE(CLK_TIMER7, "clk_timer7", mux_100m_24m_lclk0_p, 0, > + RK3576_CLKSEL_CON(72), 12, 2, MFLAGS, 7, 5, DFLAGS, > + RK3576_CLKGATE_CON(18), 12, GFLAGS), > + COMPOSITE(CLK_TIMER8, "clk_timer8", mux_100m_24m_lclk1_p, 0, > + RK3576_CLKSEL_CON(73), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(18), 13, GFLAGS), > + GATE(CLK_TIMER9, "clk_timer9", "clk_timer1_root", 0, > + RK3576_CLKGATE_CON(18), 14, GFLAGS), > + GATE(CLK_TIMER10, "clk_timer10", "clk_timer1_root", 0, > + RK3576_CLKGATE_CON(18), 15, GFLAGS), > + GATE(CLK_TIMER11, "clk_timer11", "clk_timer1_root", 0, > + RK3576_CLKGATE_CON(19), 0, GFLAGS), > + GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0, > + RK3576_CLKGATE_CON(19), 1, GFLAGS), > + GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0, > + RK3576_CLKGATE_CON(19), 2, GFLAGS), > + GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 0, > + RK3576_CLKGATE_CON(19), 3, GFLAGS), > + GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", 0, > + RK3576_CLKGATE_CON(19), 4, GFLAGS), > + GATE(HCLK_I3C0, "hclk_i3c0", "hclk_bus_root", 0, > + RK3576_CLKGATE_CON(19), 7, GFLAGS), > + GATE(HCLK_I3C1, "hclk_i3c1", "hclk_bus_root", 0, > + RK3576_CLKGATE_CON(19), 9, GFLAGS), > + COMPOSITE_NODIV(HCLK_BUS_CM0_ROOT, "hclk_bus_cm0_root", mux_400m_200m_100m_24m_p, 0, > + RK3576_CLKSEL_CON(73), 13, 2, MFLAGS, > + RK3576_CLKGATE_CON(19), 10, GFLAGS), > + GATE(FCLK_BUS_CM0_CORE, "fclk_bus_cm0_core", "hclk_bus_cm0_root", 0, > + RK3576_CLKGATE_CON(19), 12, GFLAGS), > + COMPOSITE(CLK_BUS_CM0_RTC, "clk_bus_cm0_rtc", mux_24m_32k_p, 0, > + RK3576_CLKSEL_CON(74), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(19), 14, GFLAGS), > + GATE(PCLK_PMU2, "pclk_pmu2", "pclk_bus_root", CLK_IS_CRITICAL, > + RK3576_CLKGATE_CON(19), 15, GFLAGS), > + GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(20), 4, GFLAGS), > + COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(74), 6, 2, MFLAGS, > + RK3576_CLKGATE_CON(20), 5, GFLAGS), > + GATE(CLK_OSC_PWM2, "clk_osc_pwm2", "xin24m", 0, > + RK3576_CLKGATE_CON(20), 7, GFLAGS), > + GATE(CLK_RC_PWM2, "clk_rc_pwm2", "clk_pvtm_clkout", 0, > + RK3576_CLKGATE_CON(20), 6, GFLAGS), > + COMPOSITE_NODIV(CLK_FREQ_PWM1, "clk_freq_pwm1", clk_freq_pwm1_p, 0, > + RK3576_CLKSEL_CON(74), 8, 3, MFLAGS, > + RK3576_CLKGATE_CON(20), 8, GFLAGS), > + COMPOSITE_NODIV(CLK_COUNTER_PWM1, "clk_counter_pwm1", clk_counter_pwm1_p, 0, > + RK3576_CLKSEL_CON(74), 11, 3, MFLAGS, > + RK3576_CLKGATE_CON(20), 9, GFLAGS), > + COMPOSITE_NODIV(SAI_SCLKIN_FREQ, "sai_sclkin_freq", sai_sclkin_freq_p, 0, > + RK3576_CLKSEL_CON(75), 0, 3, MFLAGS, > + RK3576_CLKGATE_CON(20), 10, GFLAGS), > + COMPOSITE_NODIV(SAI_SCLKIN_COUNTER, "sai_sclkin_counter", sai_sclkin_freq_p, 0, > + RK3576_CLKSEL_CON(75), 3, 3, MFLAGS, > + RK3576_CLKGATE_CON(20), 11, GFLAGS), > + COMPOSITE(CLK_I3C0, "clk_i3c0", gpll_cpll_aupll_spll_p, 0, > + RK3576_CLKSEL_CON(78), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(20), 12, GFLAGS), > + COMPOSITE(CLK_I3C1, "clk_i3c1", gpll_cpll_aupll_spll_p, 0, > + RK3576_CLKSEL_CON(78), 12, 2, MFLAGS, 7, 5, DFLAGS, > + RK3576_CLKGATE_CON(20), 13, GFLAGS), > + GATE(PCLK_CSIDPHY1, "pclk_csidphy1", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(40), 2, GFLAGS), > + > + /* cci */ > + COMPOSITE(PCLK_CCI_ROOT, "pclk_cci_root", mux_24m_ccipvtpll_gpll_lpll_p, CLK_IS_CRITICAL, > + RK3576_CCI_CLKSEL_CON(4), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CCI_CLKGATE_CON(1), 10, GFLAGS), > + COMPOSITE(ACLK_CCI_ROOT, "aclk_cci_root", mux_24m_ccipvtpll_gpll_lpll_p, CLK_IS_CRITICAL, > + RK3576_CCI_CLKSEL_CON(4), 12, 2, MFLAGS, 7, 5, DFLAGS, > + RK3576_CCI_CLKGATE_CON(1), 11, GFLAGS), > + > + /* center */ > + COMPOSITE_DIV_OFFSET(ACLK_CENTER_ROOT, "aclk_center_root", gpll_cpll_spll_aupll_bpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(168), 5, 3, MFLAGS, > + RK3576_CLKSEL_CON(167), 9, 5, DFLAGS, > + RK3576_CLKGATE_CON(72), 0, GFLAGS), > + COMPOSITE_NODIV(ACLK_CENTER_LOW_ROOT, "aclk_center_low_root", mux_500m_250m_100m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(168), 8, 2, MFLAGS, > + RK3576_CLKGATE_CON(72), 1, GFLAGS), > + COMPOSITE_NODIV(HCLK_CENTER_ROOT, "hclk_center_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(168), 10, 2, MFLAGS, > + RK3576_CLKGATE_CON(72), 2, GFLAGS), > + COMPOSITE_NODIV(PCLK_CENTER_ROOT, "pclk_center_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(168), 12, 2, MFLAGS, > + RK3576_CLKGATE_CON(72), 3, GFLAGS), > + GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", CLK_IGNORE_UNUSED, > + RK3576_CLKGATE_CON(72), 5, GFLAGS), > + GATE(ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", "aclk_center_low_root", CLK_IGNORE_UNUSED, > + RK3576_CLKGATE_CON(72), 6, GFLAGS), > + GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", CLK_IGNORE_UNUSED, > + RK3576_CLKGATE_CON(72), 10, GFLAGS), > + GATE(PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", CLK_IGNORE_UNUSED, > + RK3576_CLKGATE_CON(72), 11, GFLAGS), > + > + /* ddr */ > + COMPOSITE(PCLK_DDR_ROOT, "pclk_ddr_root", gpll_cpll_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(76), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(21), 0, GFLAGS), > + GATE(PCLK_DDR_MON_CH0, "pclk_ddr_mon_ch0", "pclk_ddr_root", CLK_IGNORE_UNUSED, > + RK3576_CLKGATE_CON(21), 1, GFLAGS), > + COMPOSITE(HCLK_DDR_ROOT, "hclk_ddr_root", gpll_cpll_p, CLK_IGNORE_UNUSED, > + RK3576_CLKSEL_CON(77), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(22), 11, GFLAGS), > + GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_ddr_root", CLK_IS_CRITICAL, > + RK3576_CLKGATE_CON(22), 15, GFLAGS), > + COMPOSITE_NODIV(CLK_DDR_TIMER_ROOT, "clk_ddr_timer_root", mux_100m_24m_p, 0, > + RK3576_CLKSEL_CON(77), 6, 1, MFLAGS, > + RK3576_CLKGATE_CON(23), 3, GFLAGS), > + GATE(CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", 0, > + RK3576_CLKGATE_CON(23), 4, GFLAGS), > + GATE(CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", 0, > + RK3576_CLKGATE_CON(23), 5, GFLAGS), > + GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0, > + RK3576_CLKGATE_CON(23), 6, GFLAGS), > + GATE(PCLK_WDT, "pclk_wdt", "pclk_ddr_root", 0, > + RK3576_CLKGATE_CON(23), 7, GFLAGS), > + GATE(PCLK_TIMER, "pclk_timer", "pclk_ddr_root", 0, > + RK3576_CLKGATE_CON(23), 8, GFLAGS), > + COMPOSITE(CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", mux_24m_32k_p, 0, > + RK3576_CLKSEL_CON(77), 12, 1, MFLAGS, 7, 5, DFLAGS, > + RK3576_CLKGATE_CON(23), 10, GFLAGS), > + > + /* gpu */ > + COMPOSITE(CLK_GPU_SRC_PRE, "clk_gpu_src_pre", gpll_cpll_aupll_spll_lpll_p, 0, > + RK3576_CLKSEL_CON(165), 5, 3, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(69), 1, GFLAGS), > + GATE(CLK_GPU, "clk_gpu", "clk_gpu_src_pre", 0, > + RK3576_CLKGATE_CON(69), 3, GFLAGS), > + COMPOSITE_NODIV(PCLK_GPU_ROOT, "pclk_gpu_root", mux_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(166), 10, 2, MFLAGS, > + RK3576_CLKGATE_CON(69), 8, GFLAGS), > + > + /* npu */ > + COMPOSITE_NODIV(HCLK_RKNN_ROOT, "hclk_rknn_root", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(86), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(31), 4, GFLAGS), > + COMPOSITE(CLK_RKNN_DSU0, "clk_rknn_dsu0", gpll_cpll_aupll_spll_p, 0, > + RK3576_CLKSEL_CON(86), 7, 2, MFLAGS, 2, 5, DFLAGS, > + RK3576_CLKGATE_CON(31), 5, GFLAGS), > + GATE(ACLK_RKNN0, "aclk_rknn0", "clk_rknn_dsu0", 0, > + RK3576_CLKGATE_CON(28), 9, GFLAGS), > + GATE(ACLK_RKNN1, "aclk_rknn1", "clk_rknn_dsu0", 0, > + RK3576_CLKGATE_CON(29), 0, GFLAGS), > + COMPOSITE_NODIV(PCLK_NPUTOP_ROOT, "pclk_nputop_root", mux_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(87), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(31), 8, GFLAGS), > + GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_nputop_root", 0, > + RK3576_CLKGATE_CON(31), 10, GFLAGS), > + COMPOSITE_NODIV(CLK_NPUTIMER_ROOT, "clk_nputimer_root", mux_100m_24m_p, 0, > + RK3576_CLKSEL_CON(87), 2, 1, MFLAGS, > + RK3576_CLKGATE_CON(31), 11, GFLAGS), > + GATE(CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 0, > + RK3576_CLKGATE_CON(31), 12, GFLAGS), > + GATE(CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 0, > + RK3576_CLKGATE_CON(31), 13, GFLAGS), > + GATE(PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_nputop_root", 0, > + RK3576_CLKGATE_CON(31), 14, GFLAGS), > + GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0, > + RK3576_CLKGATE_CON(31), 15, GFLAGS), > + GATE(ACLK_RKNN_CBUF, "aclk_rknn_cbuf", "clk_rknn_dsu0", 0, > + RK3576_CLKGATE_CON(32), 0, GFLAGS), > + COMPOSITE_NODIV(HCLK_NPU_CM0_ROOT, "hclk_npu_cm0_root", mux_400m_200m_100m_24m_p, 0, > + RK3576_CLKSEL_CON(87), 3, 2, MFLAGS, > + RK3576_CLKGATE_CON(32), 5, GFLAGS), > + GATE(FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core", "hclk_npu_cm0_root", 0, > + RK3576_CLKGATE_CON(32), 7, GFLAGS), > + COMPOSITE(CLK_NPU_CM0_RTC, "clk_npu_cm0_rtc", mux_24m_32k_p, 0, > + RK3576_CLKSEL_CON(87), 10, 1, MFLAGS, 5, 5, DFLAGS, > + RK3576_CLKGATE_CON(32), 9, GFLAGS), > + GATE(HCLK_RKNN_CBUF, "hclk_rknn_cbuf", "hclk_rknn_root", 0, > + RK3576_CLKGATE_CON(32), 12, GFLAGS), > + > + /* nvm */ > + COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(88), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(33), 0, GFLAGS), > + COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(88), 7, 1, MFLAGS, 2, 5, DFLAGS, > + RK3576_CLKGATE_CON(33), 1, GFLAGS), > + COMPOSITE(SCLK_FSPI_X2, "sclk_fspi_x2", gpll_cpll_24m_p, 0, > + RK3576_CLKSEL_CON(89), 6, 2, MFLAGS, 0, 6, DFLAGS, > + RK3576_CLKGATE_CON(33), 6, GFLAGS), > + GATE(HCLK_FSPI, "hclk_fspi", "hclk_nvm_root", 0, > + RK3576_CLKGATE_CON(33), 7, GFLAGS), > + COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", gpll_cpll_24m_p, 0, > + RK3576_CLKSEL_CON(89), 14, 2, MFLAGS, 8, 6, DFLAGS, > + RK3576_CLKGATE_CON(33), 8, GFLAGS), > + GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm_root", 0, > + RK3576_CLKGATE_CON(33), 9, GFLAGS), > + GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, > + RK3576_CLKGATE_CON(33), 10, GFLAGS), > + COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(90), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(33), 11, GFLAGS), > + GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0, > + RK3576_CLKGATE_CON(33), 12, GFLAGS), > + > + /* usb */ > + COMPOSITE(ACLK_UFS_ROOT, "aclk_ufs_root", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(115), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(47), 0, GFLAGS), > + COMPOSITE(ACLK_USB_ROOT, "aclk_usb_root", gpll_cpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(115), 11, 1, MFLAGS, 6, 5, DFLAGS, > + RK3576_CLKGATE_CON(47), 1, GFLAGS), > + COMPOSITE_NODIV(PCLK_USB_ROOT, "pclk_usb_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(115), 12, 2, MFLAGS, > + RK3576_CLKGATE_CON(47), 2, GFLAGS), > + GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb_root", 0, > + RK3576_CLKGATE_CON(47), 5, GFLAGS), > + GATE(CLK_REF_USB3OTG0, "clk_ref_usb3otg0", "xin24m", 0, > + RK3576_CLKGATE_CON(47), 6, GFLAGS), > + GATE(CLK_SUSPEND_USB3OTG0, "clk_suspend_usb3otg0", "xin24m", 0, > + RK3576_CLKGATE_CON(47), 7, GFLAGS), > + GATE(ACLK_MMU2, "aclk_mmu2", "aclk_usb_root", 0, > + RK3576_CLKGATE_CON(47), 12, GFLAGS), > + GATE(ACLK_SLV_MMU2, "aclk_slv_mmu2", "aclk_usb_root", 0, > + RK3576_CLKGATE_CON(47), 13, GFLAGS), > + GATE(ACLK_UFS_SYS, "aclk_ufs_sys", "aclk_ufs_root", 0, > + RK3576_CLKGATE_CON(47), 15, GFLAGS), > + > + /* vdec */ > + COMPOSITE_NODIV(HCLK_RKVDEC_ROOT, "hclk_rkvdec_root", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(110), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(45), 0, GFLAGS), > + COMPOSITE(ACLK_RKVDEC_ROOT, "aclk_rkvdec_root", gpll_cpll_aupll_spll_p, 0, > + RK3576_CLKSEL_CON(110), 7, 2, MFLAGS, 2, 5, DFLAGS, > + RK3576_CLKGATE_CON(45), 1, GFLAGS), > + COMPOSITE(ACLK_RKVDEC_ROOT_BAK, "aclk_rkvdec_root_bak", cpll_vpll_lpll_bpll_p, 0, > + RK3576_CLKSEL_CON(110), 14, 2, MFLAGS, 9, 5, DFLAGS, > + RK3576_CLKGATE_CON(45), 2, GFLAGS), > + GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_root", 0, > + RK3576_CLKGATE_CON(45), 3, GFLAGS), > + COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_lpll_bpll_p, 0, > + RK3576_CLKSEL_CON(111), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(45), 8, GFLAGS), > + GATE(CLK_RKVDEC_CORE, "clk_rkvdec_core", "aclk_rkvdec_root", 0, > + RK3576_CLKGATE_CON(45), 9, GFLAGS), > + > + /* venc */ > + COMPOSITE_NODIV(HCLK_VEPU0_ROOT, "hclk_vepu0_root", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(124), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(51), 0, GFLAGS), > + COMPOSITE(ACLK_VEPU0_ROOT, "aclk_vepu0_root", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(124), 7, 1, MFLAGS, 2, 5, DFLAGS, > + RK3576_CLKGATE_CON(51), 1, GFLAGS), > + COMPOSITE(CLK_VEPU0_CORE, "clk_vepu0_core", gpll_cpll_spll_lpll_bpll_p, 0, > + RK3576_CLKSEL_CON(124), 13, 3, MFLAGS, 8, 5, DFLAGS, > + RK3576_CLKGATE_CON(51), 6, GFLAGS), > + GATE(HCLK_VEPU0, "hclk_vepu0", "hclk_vepu0_root", 0, > + RK3576_CLKGATE_CON(51), 4, GFLAGS), > + GATE(ACLK_VEPU0, "aclk_vepu0", "aclk_vepu0_root", 0, > + RK3576_CLKGATE_CON(51), 5, GFLAGS), > + > + /* vi */ > + COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_spll_isppvtpll_bpll_lpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(128), 5, 3, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(53), 0, GFLAGS), > + COMPOSITE_NOMUX(ACLK_VI_ROOT_INTER, "aclk_vi_root_inter", "aclk_vi_root", 0, > + RK3576_CLKSEL_CON(130), 10, 3, DFLAGS, > + RK3576_CLKGATE_CON(54), 13, GFLAGS), > + COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", hclk_vi_root_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(128), 8, 2, MFLAGS, > + RK3576_CLKGATE_CON(53), 1, GFLAGS), > + COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(128), 10, 2, MFLAGS, > + RK3576_CLKGATE_CON(53), 2, GFLAGS), > + COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(129), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(53), 6, GFLAGS), > + GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0, > + RK3576_CLKGATE_CON(53), 7, GFLAGS), > + GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0, > + RK3576_CLKGATE_CON(53), 8, GFLAGS), > + COMPOSITE(CLK_ISP_CORE, "clk_isp_core", gpll_spll_isppvtpll_bpll_lpll_p, 0, > + RK3576_CLKSEL_CON(129), 11, 3, MFLAGS, 6, 5, DFLAGS, > + RK3576_CLKGATE_CON(53), 9, GFLAGS), > + GATE(CLK_ISP_CORE_MARVIN, "clk_isp_core_marvin", "clk_isp_core", 0, > + RK3576_CLKGATE_CON(53), 10, GFLAGS), > + GATE(CLK_ISP_CORE_VICAP, "clk_isp_core_vicap", "clk_isp_core", 0, > + RK3576_CLKGATE_CON(53), 11, GFLAGS), > + GATE(ACLK_ISP, "aclk_isp", "aclk_vi_root", 0, > + RK3576_CLKGATE_CON(53), 12, GFLAGS), > + GATE(HCLK_ISP, "hclk_isp", "hclk_vi_root", 0, > + RK3576_CLKGATE_CON(53), 13, GFLAGS), > + GATE(ACLK_VPSS, "aclk_vpss", "aclk_vi_root", 0, > + RK3576_CLKGATE_CON(53), 15, GFLAGS), > + GATE(HCLK_VPSS, "hclk_vpss", "hclk_vi_root", 0, > + RK3576_CLKGATE_CON(54), 0, GFLAGS), > + GATE(CLK_CORE_VPSS, "clk_core_vpss", "clk_isp_core", 0, > + RK3576_CLKGATE_CON(54), 1, GFLAGS), > + GATE(PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 0, > + RK3576_CLKGATE_CON(54), 4, GFLAGS), > + GATE(PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 0, > + RK3576_CLKGATE_CON(54), 5, GFLAGS), > + GATE(PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 0, > + RK3576_CLKGATE_CON(54), 6, GFLAGS), > + GATE(PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 0, > + RK3576_CLKGATE_CON(54), 7, GFLAGS), > + GATE(PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root", 0, > + RK3576_CLKGATE_CON(54), 8, GFLAGS), > + COMPOSITE_NODIV(ICLK_CSIHOST01, "iclk_csihost01", mux_400m_200m_100m_24m_p, 0, > + RK3576_CLKSEL_CON(130), 7, 2, MFLAGS, > + RK3576_CLKGATE_CON(54), 10, GFLAGS), > + GATE(ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01", 0, > + RK3576_CLKGATE_CON(54), 11, GFLAGS), > + COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_aupll_spll_lpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(144), 5, 3, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(61), 0, GFLAGS), > + COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(144), 10, 2, MFLAGS, > + RK3576_CLKGATE_CON(61), 2, GFLAGS), > + COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(144), 12, 2, MFLAGS, > + RK3576_CLKGATE_CON(61), 3, GFLAGS), > + GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0, > + RK3576_CLKGATE_CON(61), 8, GFLAGS), > + GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0, > + RK3576_CLKGATE_CON(61), 9, GFLAGS), > + COMPOSITE(DCLK_VP0_SRC, "dclk_vp0_src", gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT, > + RK3576_CLKSEL_CON(145), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(61), 10, GFLAGS), > + COMPOSITE(DCLK_VP1_SRC, "dclk_vp1_src", gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT, > + RK3576_CLKSEL_CON(146), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(61), 11, GFLAGS), > + COMPOSITE(DCLK_VP2_SRC, "dclk_vp2_src", gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT, > + RK3576_CLKSEL_CON(147), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(61), 12, GFLAGS), > + COMPOSITE_NODIV(DCLK_VP0, "dclk_vp0", dclk_vp0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, > + RK3576_CLKSEL_CON(147), 11, 1, MFLAGS, > + RK3576_CLKGATE_CON(61), 13, GFLAGS), > + COMPOSITE_NODIV(DCLK_VP1, "dclk_vp1", dclk_vp1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, > + RK3576_CLKSEL_CON(147), 12, 1, MFLAGS, > + RK3576_CLKGATE_CON(62), 0, GFLAGS), > + COMPOSITE_NODIV(DCLK_VP2, "dclk_vp2", dclk_vp2_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, > + RK3576_CLKSEL_CON(147), 13, 1, MFLAGS, > + RK3576_CLKGATE_CON(62), 1, GFLAGS), > + > + /* vo0 */ > + COMPOSITE(ACLK_VO0_ROOT, "aclk_vo0_root", gpll_cpll_lpll_bpll_p, 0, > + RK3576_CLKSEL_CON(149), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(63), 0, GFLAGS), > + COMPOSITE_NODIV(HCLK_VO0_ROOT, "hclk_vo0_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(149), 7, 2, MFLAGS, > + RK3576_CLKGATE_CON(63), 1, GFLAGS), > + COMPOSITE_NODIV(PCLK_VO0_ROOT, "pclk_vo0_root", mux_150m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(149), 11, 2, MFLAGS, > + RK3576_CLKGATE_CON(63), 3, GFLAGS), > + GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_vo0_root", 0, > + RK3576_CLKGATE_CON(63), 12, GFLAGS), > + GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0_root", 0, > + RK3576_CLKGATE_CON(63), 13, GFLAGS), > + GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0, > + RK3576_CLKGATE_CON(63), 14, GFLAGS), > + GATE(CLK_TRNG0_SKP, "clk_trng0_skp", "aclk_hdcp0", 0, > + RK3576_CLKGATE_CON(64), 4, GFLAGS), > + GATE(PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vo0_root", 0, > + RK3576_CLKGATE_CON(64), 5, GFLAGS), > + COMPOSITE(CLK_DSIHOST0, "clk_dsihost0", gpll_cpll_spll_vpll_bpll_lpll_p, 0, > + RK3576_CLKSEL_CON(151), 7, 3, MFLAGS, 0, 7, DFLAGS, > + RK3576_CLKGATE_CON(64), 6, GFLAGS), > + GATE(PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo0_root", 0, > + RK3576_CLKGATE_CON(64), 7, GFLAGS), > + COMPOSITE(CLK_HDMITX0_EARC, "clk_hdmitx0_earc", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(151), 15, 1, MFLAGS, 10, 5, DFLAGS, > + RK3576_CLKGATE_CON(64), 8, GFLAGS), > + GATE(CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_vo0_root", 0, > + RK3576_CLKGATE_CON(64), 9, GFLAGS), > + GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo0_root", 0, > + RK3576_CLKGATE_CON(64), 13, GFLAGS), > + GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0, > + RK3576_CLKGATE_CON(64), 14, GFLAGS), > + COMPOSITE_NODIV(CLK_EDP0_200M, "clk_edp0_200m", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(152), 1, 2, MFLAGS, > + RK3576_CLKGATE_CON(64), 15, GFLAGS), > + COMPOSITE(MCLK_SAI5_8CH_SRC, "mclk_sai5_8ch_src", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(154), 10, 3, MFLAGS, 2, 8, DFLAGS, > + RK3576_CLKGATE_CON(65), 3, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI5_8CH, "mclk_sai5_8ch", mclk_sai5_8ch_p, CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(154), 13, 1, MFLAGS, > + RK3576_CLKGATE_CON(65), 4, GFLAGS), > + GATE(HCLK_SAI5_8CH, "hclk_sai5_8ch", "hclk_vo0_root", 0, > + RK3576_CLKGATE_CON(65), 5, GFLAGS), > + COMPOSITE(MCLK_SAI6_8CH_SRC, "mclk_sai6_8ch_src", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(155), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(65), 7, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI6_8CH, "mclk_sai6_8ch", mclk_sai6_8ch_p, CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(155), 11, 1, MFLAGS, > + RK3576_CLKGATE_CON(65), 8, GFLAGS), > + GATE(HCLK_SAI6_8CH, "hclk_sai6_8ch", "hclk_vo0_root", 0, > + RK3576_CLKGATE_CON(65), 9, GFLAGS), > + GATE(HCLK_SPDIF_TX2, "hclk_spdif_tx2", "hclk_vo0_root", 0, > + RK3576_CLKGATE_CON(65), 10, GFLAGS), > + COMPOSITE(MCLK_SPDIF_TX2, "mclk_spdif_tx2", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(156), 5, 3, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(65), 13, GFLAGS), > + GATE(HCLK_SPDIF_RX2, "hclk_spdif_rx2", "hclk_vo0_root", 0, > + RK3576_CLKGATE_CON(65), 14, GFLAGS), > + COMPOSITE(MCLK_SPDIF_RX2, "mclk_spdif_rx2", gpll_cpll_aupll_p, 0, > + RK3576_CLKSEL_CON(156), 13, 2, MFLAGS, 8, 5, DFLAGS, > + RK3576_CLKGATE_CON(65), 15, GFLAGS), > + > + /* vo1 */ > + COMPOSITE(ACLK_VO1_ROOT, "aclk_vo1_root", gpll_cpll_lpll_bpll_p, 0, > + RK3576_CLKSEL_CON(158), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(67), 1, GFLAGS), > + COMPOSITE_NODIV(HCLK_VO1_ROOT, "hclk_vo1_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(158), 7, 2, MFLAGS, > + RK3576_CLKGATE_CON(67), 2, GFLAGS), > + COMPOSITE_NODIV(PCLK_VO1_ROOT, "pclk_vo1_root", mux_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(158), 9, 2, MFLAGS, > + RK3576_CLKGATE_CON(67), 3, GFLAGS), > + COMPOSITE(MCLK_SAI8_8CH_SRC, "mclk_sai8_8ch_src", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(157), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(66), 1, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI8_8CH, "mclk_sai8_8ch", mclk_sai8_8ch_p, CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(157), 11, 1, MFLAGS, > + RK3576_CLKGATE_CON(66), 2, GFLAGS), > + GATE(HCLK_SAI8_8CH, "hclk_sai8_8ch", "hclk_vo1_root", 0, > + RK3576_CLKGATE_CON(66), 0, GFLAGS), > + COMPOSITE(MCLK_SAI7_8CH_SRC, "mclk_sai7_8ch_src", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(159), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(67), 8, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI7_8CH, "mclk_sai7_8ch", mclk_sai7_8ch_p, CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(159), 11, 1, MFLAGS, > + RK3576_CLKGATE_CON(67), 9, GFLAGS), > + GATE(HCLK_SAI7_8CH, "hclk_sai7_8ch", "hclk_vo1_root", 0, > + RK3576_CLKGATE_CON(67), 10, GFLAGS), > + GATE(HCLK_SPDIF_TX3, "hclk_spdif_tx3", "hclk_vo1_root", 0, > + RK3576_CLKGATE_CON(67), 11, GFLAGS), > + GATE(HCLK_SPDIF_TX4, "hclk_spdif_tx4", "hclk_vo1_root", 0, > + RK3576_CLKGATE_CON(67), 12, GFLAGS), > + GATE(HCLK_SPDIF_TX5, "hclk_spdif_tx5", "hclk_vo1_root", 0, > + RK3576_CLKGATE_CON(67), 13, GFLAGS), > + COMPOSITE(MCLK_SPDIF_TX3, "mclk_spdif_tx3", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(160), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(67), 14, GFLAGS), > + COMPOSITE_NOMUX(CLK_AUX16MHZ_0, "clk_aux16mhz_0", "gpll", 0, > + RK3576_CLKSEL_CON(161), 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(67), 15, GFLAGS), > + GATE(ACLK_DP0, "aclk_dp0", "aclk_vo1_root", 0, > + RK3576_CLKGATE_CON(68), 0, GFLAGS), > + GATE(PCLK_DP0, "pclk_dp0", "pclk_vo1_root", 0, > + RK3576_CLKGATE_CON(68), 1, GFLAGS), > + GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_vo1_root", 0, > + RK3576_CLKGATE_CON(68), 4, GFLAGS), > + GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1_root", 0, > + RK3576_CLKGATE_CON(68), 5, GFLAGS), > + GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0, > + RK3576_CLKGATE_CON(68), 6, GFLAGS), > + GATE(CLK_TRNG1_SKP, "clk_trng1_skp", "aclk_hdcp1", 0, > + RK3576_CLKGATE_CON(68), 7, GFLAGS), > + GATE(HCLK_SAI9_8CH, "hclk_sai9_8ch", "hclk_vo1_root", 0, > + RK3576_CLKGATE_CON(68), 9, GFLAGS), > + COMPOSITE(MCLK_SAI9_8CH_SRC, "mclk_sai9_8ch_src", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(162), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(68), 10, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI9_8CH, "mclk_sai9_8ch", mclk_sai9_8ch_p, CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(162), 11, 1, MFLAGS, > + RK3576_CLKGATE_CON(68), 11, GFLAGS), > + COMPOSITE(MCLK_SPDIF_TX4, "mclk_spdif_tx4", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(163), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(68), 12, GFLAGS), > + COMPOSITE(MCLK_SPDIF_TX5, "mclk_spdif_tx5", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(164), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(68), 13, GFLAGS), > + > + /* vpu */ > + COMPOSITE(ACLK_VPU_ROOT, "aclk_vpu_root", gpll_spll_cpll_bpll_lpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(118), 5, 3, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(49), 0, GFLAGS), > + COMPOSITE_NODIV(ACLK_VPU_MID_ROOT, "aclk_vpu_mid_root", mux_600m_400m_300m_24m_p, 0, > + RK3576_CLKSEL_CON(118), 8, 2, MFLAGS, > + RK3576_CLKGATE_CON(49), 1, GFLAGS), > + COMPOSITE_NODIV(HCLK_VPU_ROOT, "hclk_vpu_root", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(118), 10, 2, MFLAGS, > + RK3576_CLKGATE_CON(49), 2, GFLAGS), > + COMPOSITE(ACLK_JPEG_ROOT, "aclk_jpeg_root", gpll_cpll_aupll_spll_p, 0, > + RK3576_CLKSEL_CON(119), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(49), 3, GFLAGS), > + COMPOSITE_NODIV(ACLK_VPU_LOW_ROOT, "aclk_vpu_low_root", mux_400m_200m_100m_24m_p, 0, > + RK3576_CLKSEL_CON(119), 7, 2, MFLAGS, > + RK3576_CLKGATE_CON(49), 4, GFLAGS), > + GATE(HCLK_RGA2E_0, "hclk_rga2e_0", "hclk_vpu_root", 0, > + RK3576_CLKGATE_CON(49), 13, GFLAGS), > + GATE(ACLK_RGA2E_0, "aclk_rga2e_0", "aclk_vpu_root", 0, > + RK3576_CLKGATE_CON(49), 14, GFLAGS), > + COMPOSITE(CLK_CORE_RGA2E_0, "clk_core_rga2e_0", gpll_spll_cpll_bpll_lpll_p, 0, > + RK3576_CLKSEL_CON(120), 5, 3, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(49), 15, GFLAGS), > + GATE(ACLK_JPEG, "aclk_jpeg", "aclk_jpeg_root", 0, > + RK3576_CLKGATE_CON(50), 0, GFLAGS), > + GATE(HCLK_JPEG, "hclk_jpeg", "hclk_vpu_root", 0, > + RK3576_CLKGATE_CON(50), 1, GFLAGS), > + GATE(HCLK_VDPP, "hclk_vdpp", "hclk_vpu_root", 0, > + RK3576_CLKGATE_CON(50), 2, GFLAGS), > + GATE(ACLK_VDPP, "aclk_vdpp", "aclk_vpu_mid_root", 0, > + RK3576_CLKGATE_CON(50), 3, GFLAGS), > + COMPOSITE(CLK_CORE_VDPP, "clk_core_vdpp", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(120), 13, 1, MFLAGS, 8, 5, DFLAGS, > + RK3576_CLKGATE_CON(50), 4, GFLAGS), > + GATE(HCLK_RGA2E_1, "hclk_rga2e_1", "hclk_vpu_root", 0, > + RK3576_CLKGATE_CON(50), 5, GFLAGS), > + GATE(ACLK_RGA2E_1, "aclk_rga2e_1", "aclk_vpu_root", 0, > + RK3576_CLKGATE_CON(50), 6, GFLAGS), > + COMPOSITE(CLK_CORE_RGA2E_1, "clk_core_rga2e_1", gpll_spll_cpll_bpll_lpll_p, 0, > + RK3576_CLKSEL_CON(121), 5, 3, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(50), 7, GFLAGS), > + MUX(0, "dclk_ebc_frac_src_p", gpll_cpll_vpll_aupll_24m_p, 0, > + RK3576_CLKSEL_CON(123), 0, 3, MFLAGS), > + COMPOSITE_FRAC(DCLK_EBC_FRAC_SRC, "dclk_ebc_frac_src", "dclk_ebc_frac_src_p", 0, > + RK3576_CLKSEL_CON(122), 0, > + RK3576_CLKGATE_CON(50), 9, GFLAGS), > + GATE(ACLK_EBC, "aclk_ebc", "aclk_vpu_low_root", 0, > + RK3576_CLKGATE_CON(50), 11, GFLAGS), > + GATE(HCLK_EBC, "hclk_ebc", "hclk_vpu_root", 0, > + RK3576_CLKGATE_CON(50), 10, GFLAGS), > + COMPOSITE(DCLK_EBC, "dclk_ebc", dclk_ebc_p, CLK_SET_RATE_NO_REPARENT, > + RK3576_CLKSEL_CON(123), 12, 3, MFLAGS, 3, 9, DFLAGS, > + RK3576_CLKGATE_CON(50), 12, GFLAGS), > + > + /* vepu */ > + COMPOSITE_NODIV(HCLK_VEPU1_ROOT, "hclk_vepu1_root", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(178), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(78), 0, GFLAGS), > + COMPOSITE(ACLK_VEPU1_ROOT, "aclk_vepu1_root", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(180), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(79), 0, GFLAGS), > + GATE(HCLK_VEPU1, "hclk_vepu1", "hclk_vepu1_root", 0, > + RK3576_CLKGATE_CON(79), 3, GFLAGS), > + GATE(ACLK_VEPU1, "aclk_vepu1", "aclk_vepu1_root", 0, > + RK3576_CLKGATE_CON(79), 4, GFLAGS), > + COMPOSITE(CLK_VEPU1_CORE, "clk_vepu1_core", gpll_cpll_spll_lpll_bpll_p, 0, > + RK3576_CLKSEL_CON(180), 11, 3, MFLAGS, 6, 5, DFLAGS, > + RK3576_CLKGATE_CON(79), 5, GFLAGS), > + > + /* php */ > + COMPOSITE_NODIV(PCLK_PHP_ROOT, "pclk_php_root", mux_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(92), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(34), 0, GFLAGS), > + COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(92), 9, 1, MFLAGS, 4, 5, DFLAGS, > + RK3576_CLKGATE_CON(34), 7, GFLAGS), > + GATE(PCLK_PCIE0, "pclk_pcie0", "pclk_php_root", 0, > + RK3576_CLKGATE_CON(34), 13, GFLAGS), > + GATE(CLK_PCIE0_AUX, "clk_pcie0_aux", "xin24m", 0, > + RK3576_CLKGATE_CON(34), 14, GFLAGS), > + GATE(ACLK_PCIE0_MST, "aclk_pcie0_mst", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(34), 15, GFLAGS), > + GATE(ACLK_PCIE0_SLV, "aclk_pcie0_slv", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(35), 0, GFLAGS), > + GATE(ACLK_PCIE0_DBI, "aclk_pcie0_dbi", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(35), 1, GFLAGS), > + GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(35), 3, GFLAGS), > + GATE(CLK_REF_USB3OTG1, "clk_ref_usb3otg1", "xin24m", 0, > + RK3576_CLKGATE_CON(35), 4, GFLAGS), > + GATE(CLK_SUSPEND_USB3OTG1, "clk_suspend_usb3otg1", "xin24m", 0, > + RK3576_CLKGATE_CON(35), 5, GFLAGS), > + GATE(ACLK_MMU0, "aclk_mmu0", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(35), 11, GFLAGS), > + GATE(ACLK_SLV_MMU0, "aclk_slv_mmu0", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(35), 13, GFLAGS), > + GATE(ACLK_MMU1, "aclk_mmu1", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(35), 14, GFLAGS), > + GATE(ACLK_SLV_MMU1, "aclk_slv_mmu1", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(36), 0, GFLAGS), > + GATE(PCLK_PCIE1, "pclk_pcie1", "pclk_php_root", 0, > + RK3576_CLKGATE_CON(36), 7, GFLAGS), > + GATE(CLK_PCIE1_AUX, "clk_pcie1_aux", "xin24m", 0, > + RK3576_CLKGATE_CON(36), 8, GFLAGS), > + GATE(ACLK_PCIE1_MST, "aclk_pcie1_mst", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(36), 9, GFLAGS), > + GATE(ACLK_PCIE1_SLV, "aclk_pcie1_slv", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(36), 10, GFLAGS), > + GATE(ACLK_PCIE1_DBI, "aclk_pcie1_dbi", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(36), 11, GFLAGS), > + COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(93), 7, 1, MFLAGS, 0, 7, DFLAGS, > + RK3576_CLKGATE_CON(37), 0, GFLAGS), > + COMPOSITE(CLK_RXOOB1, "clk_rxoob1", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(93), 15, 1, MFLAGS, 8, 7, DFLAGS, > + RK3576_CLKGATE_CON(37), 1, GFLAGS), > + GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", CLK_IS_CRITICAL, > + RK3576_CLKGATE_CON(37), 2, GFLAGS), > + GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", CLK_IS_CRITICAL, > + RK3576_CLKGATE_CON(37), 3, GFLAGS), > + GATE(ACLK_SATA0, "aclk_sata0", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(37), 4, GFLAGS), > + GATE(ACLK_SATA1, "aclk_sata1", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(37), 5, GFLAGS), > + > + /* audio */ > + COMPOSITE_NODIV(HCLK_AUDIO_ROOT, "hclk_audio_root", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(42), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(7), 1, GFLAGS), > + GATE(HCLK_ASRC_2CH_0, "hclk_asrc_2ch_0", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(7), 3, GFLAGS), > + GATE(HCLK_ASRC_2CH_1, "hclk_asrc_2ch_1", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(7), 4, GFLAGS), > + GATE(HCLK_ASRC_4CH_0, "hclk_asrc_4ch_0", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(7), 5, GFLAGS), > + GATE(HCLK_ASRC_4CH_1, "hclk_asrc_4ch_1", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(7), 6, GFLAGS), > + COMPOSITE(CLK_ASRC_2CH_0, "clk_asrc_2ch_0", gpll_cpll_aupll_p, 0, > + RK3576_CLKSEL_CON(42), 7, 2, MFLAGS, 2, 5, DFLAGS, > + RK3576_CLKGATE_CON(7), 7, GFLAGS), > + COMPOSITE(CLK_ASRC_2CH_1, "clk_asrc_2ch_1", gpll_cpll_aupll_p, 0, > + RK3576_CLKSEL_CON(42), 14, 2, MFLAGS, 9, 5, DFLAGS, > + RK3576_CLKGATE_CON(7), 8, GFLAGS), > + COMPOSITE(CLK_ASRC_4CH_0, "clk_asrc_4ch_0", gpll_cpll_aupll_p, 0, > + RK3576_CLKSEL_CON(43), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(7), 9, GFLAGS), > + COMPOSITE(CLK_ASRC_4CH_1, "clk_asrc_4ch_1", gpll_cpll_aupll_p, 0, > + RK3576_CLKSEL_CON(43), 12, 2, MFLAGS, 7, 5, DFLAGS, > + RK3576_CLKGATE_CON(7), 10, GFLAGS), > + COMPOSITE(MCLK_SAI0_8CH_SRC, "mclk_sai0_8ch_src", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(44), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(7), 11, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI0_8CH, "mclk_sai0_8ch", mclk_sai0_8ch_p, CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(44), 11, 2, MFLAGS, > + RK3576_CLKGATE_CON(7), 12, GFLAGS), > + GATE(HCLK_SAI0_8CH, "hclk_sai0_8ch", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(7), 13, GFLAGS), > + GATE(HCLK_SPDIF_RX0, "hclk_spdif_rx0", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(7), 14, GFLAGS), > + COMPOSITE(MCLK_SPDIF_RX0, "mclk_spdif_rx0", gpll_cpll_aupll_p, 0, > + RK3576_CLKSEL_CON(45), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(7), 15, GFLAGS), > + GATE(HCLK_SPDIF_RX1, "hclk_spdif_rx1", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(8), 0, GFLAGS), > + COMPOSITE(MCLK_SPDIF_RX1, "mclk_spdif_rx1", gpll_cpll_aupll_p, 0, > + RK3576_CLKSEL_CON(45), 12, 2, MFLAGS, 7, 5, DFLAGS, > + RK3576_CLKGATE_CON(8), 1, GFLAGS), > + COMPOSITE(MCLK_SAI1_8CH_SRC, "mclk_sai1_8ch_src", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(46), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(8), 4, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI1_8CH, "mclk_sai1_8ch", mclk_sai1_8ch_p, CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(46), 11, 1, MFLAGS, > + RK3576_CLKGATE_CON(8), 5, GFLAGS), > + GATE(HCLK_SAI1_8CH, "hclk_sai1_8ch", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(8), 6, GFLAGS), > + COMPOSITE(MCLK_SAI2_2CH_SRC, "mclk_sai2_2ch_src", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(47), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(8), 7, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI2_2CH, "mclk_sai2_2ch", mclk_sai2_2ch_p, CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(47), 11, 2, MFLAGS, > + RK3576_CLKGATE_CON(8), 8, GFLAGS), > + GATE(HCLK_SAI2_2CH, "hclk_sai2_2ch", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(8), 10, GFLAGS), > + COMPOSITE(MCLK_SAI3_2CH_SRC, "mclk_sai3_2ch_src", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(48), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(8), 11, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI3_2CH, "mclk_sai3_2ch", mclk_sai3_2ch_p, CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(48), 11, 2, MFLAGS, > + RK3576_CLKGATE_CON(8), 12, GFLAGS), > + GATE(HCLK_SAI3_2CH, "hclk_sai3_2ch", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(8), 14, GFLAGS), > + COMPOSITE(MCLK_SAI4_2CH_SRC, "mclk_sai4_2ch_src", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(49), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(8), 15, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI4_2CH, "mclk_sai4_2ch", mclk_sai4_2ch_p, CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(49), 11, 2, MFLAGS, > + RK3576_CLKGATE_CON(9), 0, GFLAGS), > + GATE(HCLK_SAI4_2CH, "hclk_sai4_2ch", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(9), 2, GFLAGS), > + GATE(HCLK_ACDCDIG_DSM, "hclk_acdcdig_dsm", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(9), 3, GFLAGS), > + GATE(MCLK_ACDCDIG_DSM, "mclk_acdcdig_dsm", "mclk_sai4_2ch", 0, > + RK3576_CLKGATE_CON(9), 4, GFLAGS), > + COMPOSITE(CLK_PDM1, "clk_pdm1", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(50), 9, 3, MFLAGS, 0, 9, DFLAGS, > + RK3576_CLKGATE_CON(9), 5, GFLAGS), > + GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(9), 7, GFLAGS), > + GATE(CLK_PDM1_OUT, "clk_pdm1_out", "clk_pdm1", 0, > + RK3576_CLKGATE_CON(3), 5, GFLAGS), > + COMPOSITE(MCLK_PDM1, "mclk_pdm1", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(51), 5, 3, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(9), 8, GFLAGS), > + GATE(HCLK_SPDIF_TX0, "hclk_spdif_tx0", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(9), 9, GFLAGS), > + COMPOSITE(MCLK_SPDIF_TX0, "mclk_spdif_tx0", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(52), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(9), 10, GFLAGS), > + GATE(HCLK_SPDIF_TX1, "hclk_spdif_tx1", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(9), 11, GFLAGS), > + COMPOSITE(MCLK_SPDIF_TX1, "mclk_spdif_tx1", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(53), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(9), 12, GFLAGS), > + GATE(CLK_SAI1_MCLKOUT, "clk_sai1_mclkout", "mclk_sai1_8ch", 0, > + RK3576_CLKGATE_CON(9), 13, GFLAGS), > + GATE(CLK_SAI2_MCLKOUT, "clk_sai2_mclkout", "mclk_sai2_2ch", 0, > + RK3576_CLKGATE_CON(9), 14, GFLAGS), > + GATE(CLK_SAI3_MCLKOUT, "clk_sai3_mclkout", "mclk_sai3_2ch", 0, > + RK3576_CLKGATE_CON(9), 15, GFLAGS), > + GATE(CLK_SAI4_MCLKOUT, "clk_sai4_mclkout", "mclk_sai4_2ch", 0, > + RK3576_CLKGATE_CON(10), 0, GFLAGS), > + GATE(CLK_SAI0_MCLKOUT, "clk_sai0_mclkout", "mclk_sai0_8ch", 0, > + RK3576_CLKGATE_CON(10), 1, GFLAGS), > + > + /* sdgmac */ > + COMPOSITE_NODIV(HCLK_SDGMAC_ROOT, "hclk_sdgmac_root", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(103), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(42), 0, GFLAGS), > + COMPOSITE(ACLK_SDGMAC_ROOT, "aclk_sdgmac_root", gpll_cpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(103), 7, 1, MFLAGS, 2, 5, DFLAGS, > + RK3576_CLKGATE_CON(42), 1, GFLAGS), > + COMPOSITE_NODIV(PCLK_SDGMAC_ROOT, "pclk_sdgmac_root", mux_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(103), 8, 2, MFLAGS, > + RK3576_CLKGATE_CON(42), 2, GFLAGS), > + GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(42), 7, GFLAGS), > + GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(42), 8, GFLAGS), > + GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(42), 9, GFLAGS), > + GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(42), 10, GFLAGS), > + COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", gpll_cpll_24m_p, 0, > + RK3576_CLKSEL_CON(104), 6, 2, MFLAGS, 0, 6, DFLAGS, > + RK3576_CLKGATE_CON(42), 11, GFLAGS), > + GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(42), 12, GFLAGS), > + COMPOSITE(CLK_GMAC1_PTP_REF_SRC, "clk_gmac1_ptp_ref_src", clk_gmac1_ptp_ref_src_p, 0, > + RK3576_CLKSEL_CON(104), 13, 2, MFLAGS, 8, 5, DFLAGS, > + RK3576_CLKGATE_CON(42), 15, GFLAGS), > + COMPOSITE(CLK_GMAC0_PTP_REF_SRC, "clk_gmac0_ptp_ref_src", clk_gmac0_ptp_ref_src_p, 0, > + RK3576_CLKSEL_CON(105), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(43), 0, GFLAGS), > + GATE(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", "clk_gmac1_ptp_ref_src", 0, > + RK3576_CLKGATE_CON(42), 13, GFLAGS), > + GATE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", "clk_gmac0_ptp_ref_src", 0, > + RK3576_CLKGATE_CON(42), 14, GFLAGS), > + COMPOSITE(CCLK_SRC_SDMMC0, "cclk_src_sdmmc0", gpll_cpll_24m_p, 0, > + RK3576_CLKSEL_CON(105), 13, 2, MFLAGS, 7, 6, DFLAGS, > + RK3576_CLKGATE_CON(43), 1, GFLAGS), > + GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(43), 2, GFLAGS), > + COMPOSITE(SCLK_FSPI1_X2, "sclk_fspi1_x2", gpll_cpll_24m_p, 0, > + RK3576_CLKSEL_CON(106), 6, 2, MFLAGS, 0, 6, DFLAGS, > + RK3576_CLKGATE_CON(43), 3, GFLAGS), > + GATE(HCLK_FSPI1, "hclk_fspi1", "hclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(43), 4, GFLAGS), > + COMPOSITE(ACLK_DSMC_ROOT, "aclk_dsmc_root", gpll_cpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(106), 13, 1, MFLAGS, 8, 5, DFLAGS, > + RK3576_CLKGATE_CON(43), 5, GFLAGS), > + GATE(ACLK_DSMC, "aclk_dsmc", "aclk_dsmc_root", 0, > + RK3576_CLKGATE_CON(43), 7, GFLAGS), > + GATE(PCLK_DSMC, "pclk_dsmc", "pclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(43), 8, GFLAGS), > + COMPOSITE(CLK_DSMC_SYS, "clk_dsmc_sys", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(107), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(43), 9, GFLAGS), > + GATE(HCLK_HSGPIO, "hclk_hsgpio", "hclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(43), 10, GFLAGS), > + COMPOSITE(CLK_HSGPIO_TX, "clk_hsgpio_tx", gpll_cpll_24m_p, 0, > + RK3576_CLKSEL_CON(107), 11, 2, MFLAGS, 6, 5, DFLAGS, > + RK3576_CLKGATE_CON(43), 11, GFLAGS), > + COMPOSITE(CLK_HSGPIO_RX, "clk_hsgpio_rx", gpll_cpll_24m_p, 0, > + RK3576_CLKSEL_CON(108), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(43), 12, GFLAGS), > + GATE(ACLK_HSGPIO, "aclk_hsgpio", "aclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(43), 13, GFLAGS), > + > + /* phpphy */ > + GATE(PCLK_PHPPHY_ROOT, "pclk_phpphy_root", "pclk_bus_root", CLK_IS_CRITICAL, > + RK3576_PHP_CLKGATE_CON(0), 2, GFLAGS), > + GATE(PCLK_PCIE2_COMBOPHY0, "pclk_pcie2_combophy0", "pclk_phpphy_root", 0, > + RK3576_PHP_CLKGATE_CON(0), 5, GFLAGS), > + GATE(PCLK_PCIE2_COMBOPHY1, "pclk_pcie2_combophy1", "pclk_phpphy_root", 0, > + RK3576_PHP_CLKGATE_CON(0), 7, GFLAGS), > + COMPOSITE_NOMUX(CLK_PCIE_100M_SRC, "clk_pcie_100m_src", "ppll", 0, > + RK3576_PHP_CLKSEL_CON(0), 2, 5, DFLAGS, > + RK3576_PHP_CLKGATE_CON(1), 1, GFLAGS), > + COMPOSITE_NOMUX(CLK_PCIE_100M_NDUTY_SRC, "clk_pcie_100m_nduty_src", "ppll", 0, > + RK3576_PHP_CLKSEL_CON(0), 7, 5, DFLAGS, > + RK3576_PHP_CLKGATE_CON(1), 2, GFLAGS), > + COMPOSITE_NODIV(CLK_REF_PCIE0_PHY, "clk_ref_pcie0_phy", clk_ref_pcie0_phy_p, 0, > + RK3576_PHP_CLKSEL_CON(0), 12, 2, MFLAGS, > + RK3576_PHP_CLKGATE_CON(1), 5, GFLAGS), > + COMPOSITE_NODIV(CLK_REF_PCIE1_PHY, "clk_ref_pcie1_phy", clk_ref_pcie0_phy_p, 0, > + RK3576_PHP_CLKSEL_CON(0), 14, 2, MFLAGS, > + RK3576_PHP_CLKGATE_CON(1), 8, GFLAGS), > + COMPOSITE_NOMUX(CLK_REF_MPHY_26M, "clk_ref_mphy_26m", "ppll", CLK_IS_CRITICAL, > + RK3576_PHP_CLKSEL_CON(1), 0, 8, DFLAGS, > + RK3576_PHP_CLKGATE_CON(1), 9, GFLAGS), > + > + /* pmu */ > + GATE(CLK_200M_PMU_SRC, "clk_200m_pmu_src", "clk_gpll_div6", 0, > + RK3576_PMU_CLKGATE_CON(3), 2, GFLAGS), > + COMPOSITE_NOMUX(CLK_100M_PMU_SRC, "clk_100m_pmu_src", "cpll", 0, > + RK3576_PMU_CLKSEL_CON(4), 4, 5, DFLAGS, > + RK3576_PMU_CLKGATE_CON(3), 3, GFLAGS), > + FACTOR_GATE(CLK_50M_PMU_SRC, "clk_50m_pmu_src", "clk_100m_pmu_src", 0, 1, 2, > + RK3576_PMU_CLKGATE_CON(3), 4, GFLAGS), > + COMPOSITE_NODIV(HCLK_PMU1_ROOT, "hclk_pmu1_root", mux_pmu200m_pmu100m_pmu50m_24m_p, CLK_IS_CRITICAL, > + RK3576_PMU_CLKSEL_CON(4), 0, 2, MFLAGS, > + RK3576_PMU_CLKGATE_CON(3), 0, GFLAGS), > + COMPOSITE_NODIV(HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", mux_pmu200m_pmu100m_pmu50m_24m_p, 0, > + RK3576_PMU_CLKSEL_CON(4), 2, 2, MFLAGS, > + RK3576_PMU_CLKGATE_CON(3), 1, GFLAGS), > + COMPOSITE_NODIV(PCLK_PMU0_ROOT, "pclk_pmu0_root", mux_pmu100m_pmu50m_24m_p, 0, > + RK3576_PMU_CLKSEL_CON(20), 0, 2, MFLAGS, > + RK3576_PMU_CLKGATE_CON(7), 0, GFLAGS), > + GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL, > + RK3576_PMU_CLKGATE_CON(7), 3, GFLAGS), > + GATE(PCLK_PMU1_ROOT, "pclk_pmu1_root", "pclk_pmu0_root", CLK_IS_CRITICAL, > + RK3576_PMU_CLKGATE_CON(7), 9, GFLAGS), > + GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu1_root", CLK_IS_CRITICAL, > + RK3576_PMU_CLKGATE_CON(3), 15, GFLAGS), > + GATE(CLK_PMU1, "clk_pmu1", "xin24m", CLK_IS_CRITICAL, > + RK3576_PMU_CLKGATE_CON(4), 2, GFLAGS), > + GATE(PCLK_PMUPHY_ROOT, "pclk_pmuphy_root", "pclk_pmu1_root", CLK_IS_CRITICAL, > + RK3576_PMU_CLKGATE_CON(5), 0, GFLAGS), > + GATE(PCLK_HDPTX_APB, "pclk_hdptx_apb", "pclk_pmuphy_root", 0, > + RK3576_PMU_CLKGATE_CON(0), 1, GFLAGS), > + GATE(PCLK_MIPI_DCPHY, "pclk_mipi_dcphy", "pclk_pmuphy_root", 0, > + RK3576_PMU_CLKGATE_CON(0), 2, GFLAGS), > + GATE(PCLK_CSIDPHY, "pclk_csidphy", "pclk_pmuphy_root", 0, > + RK3576_PMU_CLKGATE_CON(0), 8, GFLAGS), > + GATE(PCLK_USBDPPHY, "pclk_usbdpphy", "pclk_pmuphy_root", 0, > + RK3576_PMU_CLKGATE_CON(0), 12, GFLAGS), > + COMPOSITE_NOMUX(CLK_PMUPHY_REF_SRC, "clk_pmuphy_ref_src", "cpll", 0, > + RK3576_PMU_CLKSEL_CON(0), 0, 5, DFLAGS, > + RK3576_PMU_CLKGATE_CON(0), 13, GFLAGS), > + GATE(CLK_USBDP_COMBO_PHY_IMMORTAL, "clk_usbdp_combo_phy_immortal", "xin24m", 0, > + RK3576_PMU_CLKGATE_CON(0), 15, GFLAGS), > + GATE(CLK_HDMITXHPD, "clk_hdmitxhpd", "xin24m", 0, > + RK3576_PMU_CLKGATE_CON(1), 13, GFLAGS), > + GATE(PCLK_MPHY, "pclk_mphy", "pclk_pmuphy_root", 0, > + RK3576_PMU_CLKGATE_CON(2), 0, GFLAGS), > + MUX(CLK_REF_OSC_MPHY, "clk_ref_osc_mphy", clk_ref_osc_mphy_p, 0, > + RK3576_PMU_CLKSEL_CON(3), 0, 2, MFLAGS), > + GATE(CLK_REF_UFS_CLKOUT, "clk_ref_ufs_clkout", "clk_ref_osc_mphy", 0, > + RK3576_PMU_CLKGATE_CON(2), 5, GFLAGS), > + GATE(FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core", "hclk_pmu_cm0_root", 0, > + RK3576_PMU_CLKGATE_CON(3), 12, GFLAGS), > + COMPOSITE(CLK_PMU_CM0_RTC, "clk_pmu_cm0_rtc", mux_24m_32k_p, 0, > + RK3576_PMU_CLKSEL_CON(4), 14, 1, MFLAGS, 9, 5, DFLAGS, > + RK3576_PMU_CLKGATE_CON(3), 14, GFLAGS), > + GATE(PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu1_root", 0, > + RK3576_PMU_CLKGATE_CON(4), 5, GFLAGS), > + COMPOSITE_NODIV(TCLK_PMU1WDT, "tclk_pmu1wdt", mux_24m_32k_p, 0, > + RK3576_PMU_CLKSEL_CON(4), 15, 1, MFLAGS, > + RK3576_PMU_CLKGATE_CON(4), 6, GFLAGS), > + GATE(PCLK_PMUTIMER, "pclk_pmutimer", "pclk_pmu1_root", 0, > + RK3576_PMU_CLKGATE_CON(4), 7, GFLAGS), > + COMPOSITE_NODIV(CLK_PMUTIMER_ROOT, "clk_pmutimer_root", mux_pmu100m_24m_32k_p, 0, > + RK3576_PMU_CLKSEL_CON(5), 0, 2, MFLAGS, > + RK3576_PMU_CLKGATE_CON(4), 8, GFLAGS), > + GATE(CLK_PMUTIMER0, "clk_pmutimer0", "clk_pmutimer_root", 0, > + RK3576_PMU_CLKGATE_CON(4), 9, GFLAGS), > + GATE(CLK_PMUTIMER1, "clk_pmutimer1", "clk_pmutimer_root", 0, > + RK3576_PMU_CLKGATE_CON(4), 10, GFLAGS), > + GATE(PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu1_root", 0, > + RK3576_PMU_CLKGATE_CON(4), 11, GFLAGS), > + COMPOSITE_NODIV(CLK_PMU1PWM, "clk_pmu1pwm", mux_pmu100m_pmu50m_24m_p, 0, > + RK3576_PMU_CLKSEL_CON(5), 2, 2, MFLAGS, > + RK3576_PMU_CLKGATE_CON(4), 12, GFLAGS), > + GATE(CLK_PMU1PWM_OSC, "clk_pmu1pwm_osc", "xin24m", 0, > + RK3576_PMU_CLKGATE_CON(4), 13, GFLAGS), > + GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pmu1_root", 0, > + RK3576_PMU_CLKGATE_CON(5), 1, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_pmu200m_pmu100m_pmu50m_24m_p, 0, > + RK3576_PMU_CLKSEL_CON(6), 7, 2, MFLAGS, > + RK3576_PMU_CLKGATE_CON(5), 2, GFLAGS), > + COMPOSITE_NODIV(SCLK_UART1, "sclk_uart1", uart1_p, 0, > + RK3576_PMU_CLKSEL_CON(8), 0, 1, MFLAGS, > + RK3576_PMU_CLKGATE_CON(5), 5, GFLAGS), > + GATE(PCLK_UART1, "pclk_uart1", "pclk_pmu1_root", 0, > + RK3576_PMU_CLKGATE_CON(5), 6, GFLAGS), > + GATE(CLK_PDM0, "clk_pdm0", "clk_pdm0_src_top", 0, > + RK3576_PMU_CLKGATE_CON(5), 13, GFLAGS), > + GATE(HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 0, > + RK3576_PMU_CLKGATE_CON(5), 15, GFLAGS), > + GATE(MCLK_PDM0, "mclk_pdm0", "mclk_pdm0_src_top", 0, > + RK3576_PMU_CLKGATE_CON(6), 0, GFLAGS), > + GATE(HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 0, > + RK3576_PMU_CLKGATE_CON(6), 1, GFLAGS), > + GATE(CLK_PDM0_OUT, "clk_pdm0_out", "clk_pdm0", 0, > + RK3576_PMU_CLKGATE_CON(6), 8, GFLAGS), > + COMPOSITE(CLK_HPTIMER_SRC, "clk_hptimer_src", cpll_24m_p, CLK_IS_CRITICAL, > + RK3576_PMU_CLKSEL_CON(11), 6, 1, MFLAGS, 1, 5, DFLAGS, > + RK3576_PMU_CLKGATE_CON(6), 10, GFLAGS), > + GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0, > + RK3576_PMU_CLKGATE_CON(7), 6, GFLAGS), > + COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0, > + RK3576_PMU_CLKSEL_CON(20), 2, 1, MFLAGS, > + RK3576_PMU_CLKGATE_CON(7), 7, GFLAGS), > + GATE(CLK_OSC0_PMU1, "clk_osc0_pmu1", "xin24m", CLK_IS_CRITICAL, > + RK3576_PMU_CLKGATE_CON(7), 8, GFLAGS), > + GATE(CLK_PMU1PWM_RC, "clk_pmu1pwm_rc", "clk_pvtm_clkout", 0, > + RK3576_PMU_CLKGATE_CON(5), 7, GFLAGS), > + > + /* phy ref */ > + MUXGRF(CLK_PHY_REF_SRC, "clk_phy_ref_src", clk_phy_ref_src_p, 0, > + RK3576_PMU0_GRF_OSC_CON6, 4, 1, MFLAGS), > + MUXGRF(CLK_USBPHY_REF_SRC, "clk_usbphy_ref_src", clk_usbphy_ref_src_p, 0, > + RK3576_PMU0_GRF_OSC_CON6, 2, 1, MFLAGS), > + MUXGRF(CLK_CPLL_REF_SRC, "clk_cpll_ref_src", clk_cpll_ref_src_p, 0, > + RK3576_PMU0_GRF_OSC_CON6, 1, 1, MFLAGS), > + MUXGRF(CLK_AUPLL_REF_SRC, "clk_aupll_ref_src", clk_aupll_ref_src_p, 0, > + RK3576_PMU0_GRF_OSC_CON6, 0, 1, MFLAGS), > + > + /* secure ns */ > + COMPOSITE_NODIV(ACLK_SECURE_NS, "aclk_secure_ns", mux_350m_175m_116m_24m_p, CLK_IS_CRITICAL, > + RK3576_SECURE_NS_CLKSEL_CON(0), 0, 2, MFLAGS, > + RK3576_SECURE_NS_CLKGATE_CON(0), 0, GFLAGS), > + COMPOSITE_NODIV(HCLK_SECURE_NS, "hclk_secure_ns", mux_175m_116m_58m_24m_p, CLK_IS_CRITICAL, > + RK3576_SECURE_NS_CLKSEL_CON(0), 2, 2, MFLAGS, > + RK3576_SECURE_NS_CLKGATE_CON(0), 1, GFLAGS), > + COMPOSITE_NODIV(PCLK_SECURE_NS, "pclk_secure_ns", mux_116m_58m_24m_p, CLK_IS_CRITICAL, > + RK3576_SECURE_NS_CLKSEL_CON(0), 4, 2, MFLAGS, > + RK3576_SECURE_NS_CLKGATE_CON(0), 2, GFLAGS), > + GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_ns", 0, > + RK3576_SECURE_NS_CLKGATE_CON(0), 3, GFLAGS), > + GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_secure_ns", 0, > + RK3576_SECURE_NS_CLKGATE_CON(0), 8, GFLAGS), > + GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0, > + RK3576_SECURE_NS_CLKGATE_CON(0), 9, GFLAGS), > + GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_s", 0, > + RK3576_NON_SECURE_GATING_CON00, 14, GFLAGS), > + GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_s", 0, > + RK3576_NON_SECURE_GATING_CON00, 13, GFLAGS), > + GATE(CLK_PKA_CRYPTO_NS, "clk_pka_crypto_ns", "clk_pka_crypto_s", 0, > + RK3576_NON_SECURE_GATING_CON00, 1, GFLAGS), > + > + /* io */ > + GATE(CLK_VICAP_I0CLK, "clk_vicap_i0clk", "clk_csihost0_clkdata_i", 0, > + RK3576_CLKGATE_CON(59), 1, GFLAGS), > + GATE(CLK_VICAP_I1CLK, "clk_vicap_i1clk", "clk_csihost1_clkdata_i", 0, > + RK3576_CLKGATE_CON(59), 2, GFLAGS), > + GATE(CLK_VICAP_I2CLK, "clk_vicap_i2clk", "clk_csihost2_clkdata_i", 0, > + RK3576_CLKGATE_CON(59), 3, GFLAGS), > + GATE(CLK_VICAP_I3CLK, "clk_vicap_i3clk", "clk_csihost3_clkdata_i", 0, > + RK3576_CLKGATE_CON(59), 4, GFLAGS), > + GATE(CLK_VICAP_I4CLK, "clk_vicap_i4clk", "clk_csihost4_clkdata_i", 0, > + RK3576_CLKGATE_CON(59), 5, GFLAGS), > +}; > + > +static void __init rk3576_clk_init(struct device_node *np) > +{ > + struct rockchip_clk_provider *ctx; > + unsigned long clk_nr_clks; > + void __iomem *reg_base; > + > + clk_nr_clks = rockchip_clk_find_max_clk_id(rk3576_clk_branches, > + ARRAY_SIZE(rk3576_clk_branches)) + 1; > + > + reg_base = of_iomap(np, 0); > + if (!reg_base) { > + pr_err("%s: could not map cru region\n", __func__); > + return; > + } > + > + ctx = rockchip_clk_init(np, reg_base, clk_nr_clks); > + if (IS_ERR(ctx)) { > + pr_err("%s: rockchip clk init failed\n", __func__); > + iounmap(reg_base); > + return; > + } > + > + rockchip_clk_register_plls(ctx, rk3576_pll_clks, > + ARRAY_SIZE(rk3576_pll_clks), > + RK3576_GRF_SOC_STATUS0); > + > + rockchip_clk_register_armclk(ctx, ARMCLK_L, "armclk_l", > + mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), > + &rk3576_cpulclk_data, rk3576_cpulclk_rates, > + ARRAY_SIZE(rk3576_cpulclk_rates)); > + rockchip_clk_register_armclk(ctx, ARMCLK_B, "armclk_b", > + mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p), > + &rk3576_cpubclk_data, rk3576_cpubclk_rates, > + ARRAY_SIZE(rk3576_cpubclk_rates)); > + > + rockchip_clk_register_branches(ctx, rk3576_clk_branches, > + ARRAY_SIZE(rk3576_clk_branches)); > + > + rk3576_rst_init(np, reg_base); > + > + rockchip_register_restart_notifier(ctx, RK3576_GLB_SRST_FST, NULL); > + > + rockchip_clk_of_add_provider(np, ctx); > +} > + > +CLK_OF_DECLARE(rk3576_cru, "rockchip,rk3576-cru", rk3576_clk_init); > + > +#ifdef MODULE > +struct clk_rk3576_inits { > + void (*inits)(struct device_node *np); > +}; > + > +static const struct clk_rk3576_inits clk_rk3576_cru_init = { > + .inits = rk3576_clk_init, > +}; > + > +static const struct of_device_id clk_rk3576_match_table[] = { > + { > + .compatible = "rockchip,rk3576-cru", > + .data = &clk_rk3576_cru_init, > + }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, clk_rk3576_match_table); > + > +static int clk_rk3576_probe(struct platform_device *pdev) > +{ > + struct device_node *np = pdev->dev.of_node; > + const struct of_device_id *match; > + const struct clk_rk3576_inits *init_data; > + > + match = of_match_device(clk_rk3576_match_table, &pdev->dev); > + if (!match || !match->data) > + return -EINVAL; > + > + init_data = match->data; > + if (init_data->inits) > + init_data->inits(np); > + > + return 0; > +} > + > +static struct platform_driver clk_rk3576_driver = { > + .probe = clk_rk3576_probe, > + .driver = { > + .name = "clk-rk3576", > + .of_match_table = clk_rk3576_match_table, > + .suppress_bind_attrs = true, > + }, > +}; > +module_platform_driver(clk_rk3576_driver); > + > +MODULE_DESCRIPTION("Rockchip RK3576 Clock Driver"); > +MODULE_LICENSE("GPL"); > +#endif /* MODULE */ > diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h > index fd3b476dedda9..43eaeac8a8f62 100644 > --- a/drivers/clk/rockchip/clk.h > +++ b/drivers/clk/rockchip/clk.h > @@ -235,6 +235,58 @@ struct clk; > #define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180) > #define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200) > > +#define RK3576_PHP_CRU_BASE 0x8000 > +#define RK3576_SECURE_NS_CRU_BASE 0x10000 > +#define RK3576_PMU_CRU_BASE 0x20000 > +#define RK3576_BIGCORE_CRU_BASE 0x38000 > +#define RK3576_LITCORE_CRU_BASE 0x40000 > +#define RK3576_CCI_CRU_BASE 0x48000 > + > +#define RK3576_PLL_CON(x) RK2928_PLL_CON(x) > +#define RK3576_MODE_CON0 0x280 > +#define RK3576_BPLL_MODE_CON0 (RK3576_BIGCORE_CRU_BASE + 0x280) > +#define RK3576_LPLL_MODE_CON0 (RK3576_LITCORE_CRU_BASE + 0x280) > +#define RK3576_PPLL_MODE_CON0 (RK3576_PHP_CRU_BASE + 0x280) > +#define RK3576_CLKSEL_CON(x) ((x) * 0x4 + 0x300) > +#define RK3576_CLKGATE_CON(x) ((x) * 0x4 + 0x800) > +#define RK3576_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) > +#define RK3576_GLB_CNT_TH 0xc00 > +#define RK3576_GLB_SRST_FST 0xc08 > +#define RK3576_GLB_SRST_SND 0xc0c > +#define RK3576_GLB_RST_CON 0xc10 > +#define RK3576_GLB_RST_ST 0xc04 > +#define RK3576_SDIO_CON0 0xC24 > +#define RK3576_SDIO_CON1 0xC28 > +#define RK3576_SDMMC_CON0 0xC30 > +#define RK3576_SDMMC_CON1 0xC34 > + > +#define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x300) > +#define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x800) > +#define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0xa00) > + > +#define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE) > +#define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x300) > +#define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x800) > +#define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0xa00) > + > +#define RK3576_SECURE_NS_CLKSEL_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x300) > +#define RK3576_SECURE_NS_CLKGATE_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x800) > +#define RK3576_SECURE_NS_SOFTRST_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0xa00) > + > +#define RK3576_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x300) > +#define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x800) > +#define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0xa00) > + > +#define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE) > +#define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x300) > +#define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x800) > +#define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0xa00) > +#define RK3576_LPLL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE) > +#define RK3576_LITCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x300) > +#define RK3576_LITCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x800) > +#define RK3576_LITCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0xa00) > +#define RK3576_NON_SECURE_GATING_CON00 0xc48 > + > #define RK3588_PHP_CRU_BASE 0x8000 > #define RK3588_PMU_CRU_BASE 0x30000 > #define RK3588_BIGCORE0_CRU_BASE 0x50000 > @@ -1025,6 +1077,7 @@ static inline void rockchip_register_softrst(struct device_node *np, > return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags); > } > > +void rk3576_rst_init(struct device_node *np, void __iomem *reg_base); > void rk3588_rst_init(struct device_node *np, void __iomem *reg_base); > > #endif > diff --git a/drivers/clk/rockchip/rst-rk3576.c b/drivers/clk/rockchip/rst-rk3576.c > new file mode 100644 > index 0000000000000..3380d73c86c52 > --- /dev/null > +++ b/drivers/clk/rockchip/rst-rk3576.c > @@ -0,0 +1,652 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +/* > + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. > + * Copyright (c) 2024 Collabora Ltd. > + * Author: Detlev Casanova > + * Based on Sebastien Reichel's implementation for RK3588 > + */ > + > +#include > +#include > +#include > +#include "clk.h" > + > +/* 0x27200000 + 0x0A00 */ > +#define RK3576_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) > +/* 0x27208000 + 0x0A00 */ > +#define RK3576_PHPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit) > +/* 0x27210000 + 0x0A00 */ > +#define RK3576_SECURENSCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit) > +/* 0x27220000 + 0x0A00 */ > +#define RK3576_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit) > + > +/* mapping table for reset ID to register offset */ > +static const int rk3576_register_offset[] = { > + /* SOFTRST_CON01 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3), > + RK3576_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 5), > + RK3576_CRU_RESET_OFFSET(SRST_A_TOP_MID_BIU, 1, 6), > + RK3576_CRU_RESET_OFFSET(SRST_A_SECURE_HIGH_BIU, 1, 7), > + RK3576_CRU_RESET_OFFSET(SRST_H_TOP_BIU, 1, 14), > + > + /* SOFTRST_CON02 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_VO0VOP_CHANNEL_BIU, 2, 0), > + RK3576_CRU_RESET_OFFSET(SRST_A_VO0VOP_CHANNEL_BIU, 2, 1), > + > + /* SOFTRST_CON06 */ > + RK3576_CRU_RESET_OFFSET(SRST_BISRINTF, 6, 2), > + > + /* SOFTRST_CON07 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2), > + RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_0, 7, 3), > + RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_1, 7, 4), > + RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_0, 7, 5), > + RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_1, 7, 6), > + RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_0, 7, 7), > + RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_1, 7, 8), > + RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_0, 7, 9), > + RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_1, 7, 10), > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI0_8CH, 7, 12), > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI0_8CH, 7, 13), > + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX0, 7, 14), > + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX0, 7, 15), > + > + /* SOFTRST_CON08 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX1, 8, 0), > + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX1, 8, 1), > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI1_8CH, 8, 5), > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI1_8CH, 8, 6), > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI2_2CH, 8, 8), > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI2_2CH, 8, 10), > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI3_2CH, 8, 12), > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI3_2CH, 8, 14), > + > + /* SOFTRST_CON09 */ > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI4_2CH, 9, 0), > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2), > + RK3576_CRU_RESET_OFFSET(SRST_H_ACDCDIG_DSM, 9, 3), > + RK3576_CRU_RESET_OFFSET(SRST_M_ACDCDIG_DSM, 9, 4), > + RK3576_CRU_RESET_OFFSET(SRST_PDM1, 9, 5), > + RK3576_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 7), > + RK3576_CRU_RESET_OFFSET(SRST_M_PDM1, 9, 8), > + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX0, 9, 9), > + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX0, 9, 10), > + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX1, 9, 11), > + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX1, 9, 12), > + > + /* SOFTRST_CON11 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 11, 3), > + RK3576_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 11, 4), > + RK3576_CRU_RESET_OFFSET(SRST_P_CRU, 11, 5), > + RK3576_CRU_RESET_OFFSET(SRST_H_CAN0, 11, 6), > + RK3576_CRU_RESET_OFFSET(SRST_CAN0, 11, 7), > + RK3576_CRU_RESET_OFFSET(SRST_H_CAN1, 11, 8), > + RK3576_CRU_RESET_OFFSET(SRST_CAN1, 11, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2BUS, 11, 12), > + RK3576_CRU_RESET_OFFSET(SRST_P_VCCIO_IOC, 11, 13), > + RK3576_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 11, 14), > + RK3576_CRU_RESET_OFFSET(SRST_KEY_SHIFT, 11, 15), > + > + /* SOFTRST_CON12 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0), > + RK3576_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_I2C3, 12, 2), > + RK3576_CRU_RESET_OFFSET(SRST_P_I2C4, 12, 3), > + RK3576_CRU_RESET_OFFSET(SRST_P_I2C5, 12, 4), > + RK3576_CRU_RESET_OFFSET(SRST_P_I2C6, 12, 5), > + RK3576_CRU_RESET_OFFSET(SRST_P_I2C7, 12, 6), > + RK3576_CRU_RESET_OFFSET(SRST_P_I2C8, 12, 7), > + RK3576_CRU_RESET_OFFSET(SRST_P_I2C9, 12, 8), > + RK3576_CRU_RESET_OFFSET(SRST_P_WDT_BUSMCU, 12, 9), > + RK3576_CRU_RESET_OFFSET(SRST_T_WDT_BUSMCU, 12, 10), > + RK3576_CRU_RESET_OFFSET(SRST_A_GIC, 12, 11), > + RK3576_CRU_RESET_OFFSET(SRST_I2C1, 12, 12), > + RK3576_CRU_RESET_OFFSET(SRST_I2C2, 12, 13), > + RK3576_CRU_RESET_OFFSET(SRST_I2C3, 12, 14), > + RK3576_CRU_RESET_OFFSET(SRST_I2C4, 12, 15), > + > + /* SOFTRST_CON13 */ > + RK3576_CRU_RESET_OFFSET(SRST_I2C5, 13, 0), > + RK3576_CRU_RESET_OFFSET(SRST_I2C6, 13, 1), > + RK3576_CRU_RESET_OFFSET(SRST_I2C7, 13, 2), > + RK3576_CRU_RESET_OFFSET(SRST_I2C8, 13, 3), > + RK3576_CRU_RESET_OFFSET(SRST_I2C9, 13, 4), > + RK3576_CRU_RESET_OFFSET(SRST_P_SARADC, 13, 6), > + RK3576_CRU_RESET_OFFSET(SRST_SARADC, 13, 7), > + RK3576_CRU_RESET_OFFSET(SRST_P_TSADC, 13, 8), > + RK3576_CRU_RESET_OFFSET(SRST_TSADC, 13, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART0, 13, 10), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART2, 13, 11), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART3, 13, 12), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART4, 13, 13), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART5, 13, 14), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART6, 13, 15), > + > + /* SOFTRST_CON14 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_UART7, 14, 0), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART8, 14, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART9, 14, 2), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART10, 14, 3), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART11, 14, 4), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART0, 14, 5), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART2, 14, 6), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART3, 14, 9), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART4, 14, 12), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART5, 14, 15), > + > + /* SOFTRST_CON15 */ > + RK3576_CRU_RESET_OFFSET(SRST_S_UART6, 15, 2), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART7, 15, 5), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART8, 15, 8), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART9, 15, 9), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART10, 15, 10), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART11, 15, 11), > + RK3576_CRU_RESET_OFFSET(SRST_P_SPI0, 15, 13), > + RK3576_CRU_RESET_OFFSET(SRST_P_SPI1, 15, 14), > + RK3576_CRU_RESET_OFFSET(SRST_P_SPI2, 15, 15), > + > + /* SOFTRST_CON16 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_SPI3, 16, 0), > + RK3576_CRU_RESET_OFFSET(SRST_P_SPI4, 16, 1), > + RK3576_CRU_RESET_OFFSET(SRST_SPI0, 16, 2), > + RK3576_CRU_RESET_OFFSET(SRST_SPI1, 16, 3), > + RK3576_CRU_RESET_OFFSET(SRST_SPI2, 16, 4), > + RK3576_CRU_RESET_OFFSET(SRST_SPI3, 16, 5), > + RK3576_CRU_RESET_OFFSET(SRST_SPI4, 16, 6), > + RK3576_CRU_RESET_OFFSET(SRST_P_WDT0, 16, 7), > + RK3576_CRU_RESET_OFFSET(SRST_T_WDT0, 16, 8), > + RK3576_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 16, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_PWM1, 16, 10), > + RK3576_CRU_RESET_OFFSET(SRST_PWM1, 16, 11), > + > + /* SOFTRST_CON17 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 17, 3), > + RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 17, 4), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER0, 17, 6), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER1, 17, 7), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER2, 17, 8), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER3, 17, 9), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER4, 17, 10), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER5, 17, 11), > + RK3576_CRU_RESET_OFFSET(SRST_P_BUSIOC, 17, 12), > + RK3576_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 17, 13), > + RK3576_CRU_RESET_OFFSET(SRST_P_GPIO1, 17, 15), > + > + /* SOFTRST_CON18 */ > + RK3576_CRU_RESET_OFFSET(SRST_GPIO1, 18, 0), > + RK3576_CRU_RESET_OFFSET(SRST_P_GPIO2, 18, 1), > + RK3576_CRU_RESET_OFFSET(SRST_GPIO2, 18, 2), > + RK3576_CRU_RESET_OFFSET(SRST_P_GPIO3, 18, 3), > + RK3576_CRU_RESET_OFFSET(SRST_GPIO3, 18, 4), > + RK3576_CRU_RESET_OFFSET(SRST_P_GPIO4, 18, 5), > + RK3576_CRU_RESET_OFFSET(SRST_GPIO4, 18, 6), > + RK3576_CRU_RESET_OFFSET(SRST_A_DECOM, 18, 7), > + RK3576_CRU_RESET_OFFSET(SRST_P_DECOM, 18, 8), > + RK3576_CRU_RESET_OFFSET(SRST_D_DECOM, 18, 9), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER6, 18, 11), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER7, 18, 12), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER8, 18, 13), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER9, 18, 14), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER10, 18, 15), > + > + /* SOFTRST_CON19 */ > + RK3576_CRU_RESET_OFFSET(SRST_TIMER11, 19, 0), > + RK3576_CRU_RESET_OFFSET(SRST_A_DMAC0, 19, 1), > + RK3576_CRU_RESET_OFFSET(SRST_A_DMAC1, 19, 2), > + RK3576_CRU_RESET_OFFSET(SRST_A_DMAC2, 19, 3), > + RK3576_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 19, 4), > + RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_BUS, 19, 5), > + RK3576_CRU_RESET_OFFSET(SRST_H_I3C0, 19, 7), > + RK3576_CRU_RESET_OFFSET(SRST_H_I3C1, 19, 9), > + RK3576_CRU_RESET_OFFSET(SRST_H_BUS_CM0_BIU, 19, 11), > + RK3576_CRU_RESET_OFFSET(SRST_F_BUS_CM0_CORE, 19, 12), > + RK3576_CRU_RESET_OFFSET(SRST_T_BUS_CM0_JTAG, 19, 13), > + > + /* SOFTRST_CON20 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2PMU, 20, 0), > + RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2DDR, 20, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_BUS, 20, 3), > + RK3576_CRU_RESET_OFFSET(SRST_P_PWM2, 20, 4), > + RK3576_CRU_RESET_OFFSET(SRST_PWM2, 20, 5), > + RK3576_CRU_RESET_OFFSET(SRST_FREQ_PWM1, 20, 8), > + RK3576_CRU_RESET_OFFSET(SRST_COUNTER_PWM1, 20, 9), > + RK3576_CRU_RESET_OFFSET(SRST_I3C0, 20, 12), > + RK3576_CRU_RESET_OFFSET(SRST_I3C1, 20, 13), > + > + /* SOFTRST_CON21 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 21, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 21, 2), > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 21, 3), > + RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 21, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 21, 5), > + RK3576_CRU_RESET_OFFSET(SRST_DFI_CH0, 21, 6), > + RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 21, 10), > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH0, 21, 13), > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 21, 14), > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH1, 21, 15), > + > + /* SOFTRST_CON22 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 22, 0), > + RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 22, 1), > + RK3576_CRU_RESET_OFFSET(SRST_DFI_CH1, 22, 2), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 22, 3), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 4), > + RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 22, 6), > + RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH0, 22, 9), > + RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH1, 22, 10), > + RK3576_CRU_RESET_OFFSET(SRST_P_AHB2APB, 22, 12), > + RK3576_CRU_RESET_OFFSET(SRST_H_AHB2APB, 22, 13), > + RK3576_CRU_RESET_OFFSET(SRST_H_DDR_BIU, 22, 14), > + RK3576_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 22, 15), > + > + /* SOFTRST_CON23 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 23, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 23, 2), > + RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 23, 4), > + RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 23, 5), > + RK3576_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 23, 6), > + RK3576_CRU_RESET_OFFSET(SRST_P_WDT, 23, 7), > + RK3576_CRU_RESET_OFFSET(SRST_P_TIMER, 23, 8), > + RK3576_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 23, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 23, 11), > + > + /* SOFTRST_CON25 */ > + RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 25, 1), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH0, 25, 2), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH0, 25, 3), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH0, 25, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH0, 25, 5), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH0, 25, 6), > + > + /* SOFTRST_CON26 */ > + RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 26, 1), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH1, 26, 2), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH1, 26, 3), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH1, 26, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH1, 26, 5), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH1, 26, 6), > + > + /* SOFTRST_CON27 */ > + RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_DDR, 27, 0), > + RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_DDR, 27, 1), > + > + /* SOFTRST_CON28 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0, 28, 9), > + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 28, 11), > + RK3576_CRU_RESET_OFFSET(SRST_L_RKNN0_BIU, 28, 12), > + > + /* SOFTRST_CON29 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1, 29, 0), > + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 29, 2), > + RK3576_CRU_RESET_OFFSET(SRST_L_RKNN1_BIU, 29, 3), > + > + /* SOFTRST_CON31 */ > + RK3576_CRU_RESET_OFFSET(SRST_NPU_DAP, 31, 0), > + RK3576_CRU_RESET_OFFSET(SRST_L_NPUSUBSYS_BIU, 31, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 31, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 31, 10), > + RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER0, 31, 12), > + RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER1, 31, 13), > + RK3576_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 31, 14), > + RK3576_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 31, 15), > + > + /* SOFTRST_CON32 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN_CBUF, 32, 0), > + RK3576_CRU_RESET_OFFSET(SRST_A_RVCORE0, 32, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 32, 2), > + RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_NPU, 32, 3), > + RK3576_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 32, 4), > + RK3576_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 32, 6), > + RK3576_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 32, 7), > + RK3576_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 32, 8), > + RK3576_CRU_RESET_OFFSET(SRST_A_RKNNTOP_BIU, 32, 11), > + RK3576_CRU_RESET_OFFSET(SRST_H_RKNN_CBUF, 32, 12), > + RK3576_CRU_RESET_OFFSET(SRST_H_RKNNTOP_BIU, 32, 13), > + > + /* SOFTRST_CON33 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 33, 2), > + RK3576_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 33, 3), > + RK3576_CRU_RESET_OFFSET(SRST_S_FSPI, 33, 6), > + RK3576_CRU_RESET_OFFSET(SRST_H_FSPI, 33, 7), > + RK3576_CRU_RESET_OFFSET(SRST_C_EMMC, 33, 8), > + RK3576_CRU_RESET_OFFSET(SRST_H_EMMC, 33, 9), > + RK3576_CRU_RESET_OFFSET(SRST_A_EMMC, 33, 10), > + RK3576_CRU_RESET_OFFSET(SRST_B_EMMC, 33, 11), > + RK3576_CRU_RESET_OFFSET(SRST_T_EMMC, 33, 12), > + > + /* SOFTRST_CON34 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_GRF, 34, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 34, 5), > + RK3576_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 34, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_PCIE0, 34, 13), > + RK3576_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 34, 15), > + > + /* SOFTRST_CON35 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 35, 3), > + RK3576_CRU_RESET_OFFSET(SRST_A_MMU0, 35, 11), > + RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU0, 35, 13), > + RK3576_CRU_RESET_OFFSET(SRST_A_MMU1, 35, 14), > + > + /* SOFTRST_CON36 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU1, 36, 0), > + RK3576_CRU_RESET_OFFSET(SRST_P_PCIE1, 36, 7), > + RK3576_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 36, 9), > + > + /* SOFTRST_CON37 */ > + RK3576_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 0), > + RK3576_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 1), > + RK3576_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 2), > + RK3576_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 3), > + RK3576_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 5), > + RK3576_CRU_RESET_OFFSET(SRST_ASIC1, 37, 6), > + RK3576_CRU_RESET_OFFSET(SRST_ASIC0, 37, 7), > + > + /* SOFTRST_CON40 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_CSIDPHY1, 40, 2), > + RK3576_CRU_RESET_OFFSET(SRST_SCAN_CSIDPHY1, 40, 3), > + > + /* SOFTRST_CON42 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_GRF, 42, 3), > + RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_BIU, 42, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_SDGMAC_BIU, 42, 5), > + RK3576_CRU_RESET_OFFSET(SRST_H_SDGMAC_BIU, 42, 6), > + RK3576_CRU_RESET_OFFSET(SRST_A_GMAC0, 42, 7), > + RK3576_CRU_RESET_OFFSET(SRST_A_GMAC1, 42, 8), > + RK3576_CRU_RESET_OFFSET(SRST_P_GMAC0, 42, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_GMAC1, 42, 10), > + RK3576_CRU_RESET_OFFSET(SRST_H_SDIO, 42, 12), > + > + /* SOFTRST_CON43 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_SDMMC0, 43, 2), > + RK3576_CRU_RESET_OFFSET(SRST_S_FSPI1, 43, 3), > + RK3576_CRU_RESET_OFFSET(SRST_H_FSPI1, 43, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_DSMC_BIU, 43, 6), > + RK3576_CRU_RESET_OFFSET(SRST_A_DSMC, 43, 7), > + RK3576_CRU_RESET_OFFSET(SRST_P_DSMC, 43, 8), > + RK3576_CRU_RESET_OFFSET(SRST_H_HSGPIO, 43, 10), > + RK3576_CRU_RESET_OFFSET(SRST_HSGPIO, 43, 11), > + RK3576_CRU_RESET_OFFSET(SRST_A_HSGPIO, 43, 13), > + > + /* SOFTRST_CON45 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC, 45, 3), > + RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 45, 5), > + RK3576_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 45, 6), > + RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_HEVC_CA, 45, 8), > + RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_CORE, 45, 9), > + > + /* SOFTRST_CON47 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_USB_BIU, 47, 3), > + RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_BIU, 47, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 47, 5), > + RK3576_CRU_RESET_OFFSET(SRST_A_UFS_BIU, 47, 10), > + RK3576_CRU_RESET_OFFSET(SRST_A_MMU2, 47, 12), > + RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU2, 47, 13), > + RK3576_CRU_RESET_OFFSET(SRST_A_UFS_SYS, 47, 15), > + > + /* SOFTRST_CON48 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_UFS, 48, 0), > + RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_GRF, 48, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_UFS_GRF, 48, 2), > + > + /* SOFTRST_CON49 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 49, 6), > + RK3576_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 49, 7), > + RK3576_CRU_RESET_OFFSET(SRST_A_RGA_BIU, 49, 10), > + RK3576_CRU_RESET_OFFSET(SRST_A_VDPP_BIU, 49, 11), > + RK3576_CRU_RESET_OFFSET(SRST_A_EBC_BIU, 49, 12), > + RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_0, 49, 13), > + RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_0, 49, 14), > + RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_0, 49, 15), > + > + /* SOFTRST_CON50 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_JPEG, 50, 0), > + RK3576_CRU_RESET_OFFSET(SRST_H_JPEG, 50, 1), > + RK3576_CRU_RESET_OFFSET(SRST_H_VDPP, 50, 2), > + RK3576_CRU_RESET_OFFSET(SRST_A_VDPP, 50, 3), > + RK3576_CRU_RESET_OFFSET(SRST_CORE_VDPP, 50, 4), > + RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_1, 50, 5), > + RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_1, 50, 6), > + RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_1, 50, 7), > + RK3576_CRU_RESET_OFFSET(SRST_H_EBC, 50, 10), > + RK3576_CRU_RESET_OFFSET(SRST_A_EBC, 50, 11), > + RK3576_CRU_RESET_OFFSET(SRST_D_EBC, 50, 12), > + > + /* SOFTRST_CON51 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0_BIU, 51, 2), > + RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0_BIU, 51, 3), > + RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0, 51, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0, 51, 5), > + RK3576_CRU_RESET_OFFSET(SRST_VEPU0_CORE, 51, 6), > + > + /* SOFTRST_CON53 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_VI_BIU, 53, 3), > + RK3576_CRU_RESET_OFFSET(SRST_H_VI_BIU, 53, 4), > + RK3576_CRU_RESET_OFFSET(SRST_P_VI_BIU, 53, 5), > + RK3576_CRU_RESET_OFFSET(SRST_D_VICAP, 53, 6), > + RK3576_CRU_RESET_OFFSET(SRST_A_VICAP, 53, 7), > + RK3576_CRU_RESET_OFFSET(SRST_H_VICAP, 53, 8), > + RK3576_CRU_RESET_OFFSET(SRST_ISP0, 53, 10), > + RK3576_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 53, 11), > + > + /* SOFTRST_CON54 */ > + RK3576_CRU_RESET_OFFSET(SRST_CORE_VPSS, 54, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 54, 4), > + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 54, 5), > + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 54, 6), > + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 54, 7), > + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 54, 8), > + > + /* SOFTRST_CON59 */ > + RK3576_CRU_RESET_OFFSET(SRST_CIFIN, 59, 0), > + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I0CLK, 59, 1), > + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I1CLK, 59, 2), > + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I2CLK, 59, 3), > + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I3CLK, 59, 4), > + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I4CLK, 59, 5), > + > + /* SOFTRST_CON61 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 61, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_VOP2_BIU, 61, 5), > + RK3576_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 61, 6), > + RK3576_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 61, 7), > + RK3576_CRU_RESET_OFFSET(SRST_H_VOP, 61, 8), > + RK3576_CRU_RESET_OFFSET(SRST_A_VOP, 61, 9), > + RK3576_CRU_RESET_OFFSET(SRST_D_VP0, 61, 13), > + > + /* SOFTRST_CON62 */ > + RK3576_CRU_RESET_OFFSET(SRST_D_VP1, 62, 0), > + RK3576_CRU_RESET_OFFSET(SRST_D_VP2, 62, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_VOP2_BIU, 62, 2), > + RK3576_CRU_RESET_OFFSET(SRST_P_VOPGRF, 62, 3), > + > + /* SOFTRST_CON63 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 63, 5), > + RK3576_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 63, 7), > + RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 63, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_VO0_GRF, 63, 10), > + RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0, 63, 12), > + RK3576_CRU_RESET_OFFSET(SRST_H_HDCP0, 63, 13), > + RK3576_CRU_RESET_OFFSET(SRST_HDCP0, 63, 14), > + > + /* SOFTRST_CON64 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 64, 5), > + RK3576_CRU_RESET_OFFSET(SRST_DSIHOST0, 64, 6), > + RK3576_CRU_RESET_OFFSET(SRST_P_HDMITX0, 64, 7), > + RK3576_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 64, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_EDP0, 64, 13), > + RK3576_CRU_RESET_OFFSET(SRST_EDP0_24M, 64, 14), > + > + /* SOFTRST_CON65 */ > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI5_8CH, 65, 4), > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI5_8CH, 65, 5), > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI6_8CH, 65, 8), > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI6_8CH, 65, 9), > + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX2, 65, 10), > + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX2, 65, 13), > + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX2, 65, 14), > + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX2, 65, 15), > + > + /* SOFTRST_CON66 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI8_8CH, 66, 0), > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI8_8CH, 66, 2), > + > + /* SOFTRST_CON67 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_VO1_BIU, 67, 5), > + RK3576_CRU_RESET_OFFSET(SRST_P_VO1_BIU, 67, 6), > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI7_8CH, 67, 9), > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI7_8CH, 67, 10), > + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX3, 67, 11), > + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX4, 67, 12), > + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX5, 67, 13), > + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX3, 67, 14), > + > + /* SOFTRST_CON68 */ > + RK3576_CRU_RESET_OFFSET(SRST_DP0, 68, 0), > + RK3576_CRU_RESET_OFFSET(SRST_P_VO1_GRF, 68, 2), > + RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 68, 3), > + RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1, 68, 4), > + RK3576_CRU_RESET_OFFSET(SRST_H_HDCP1, 68, 5), > + RK3576_CRU_RESET_OFFSET(SRST_HDCP1, 68, 6), > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI9_8CH, 68, 9), > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI9_8CH, 68, 11), > + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX4, 68, 12), > + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX5, 68, 13), > + > + /* SOFTRST_CON69 */ > + RK3576_CRU_RESET_OFFSET(SRST_GPU, 69, 3), > + RK3576_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 69, 6), > + RK3576_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 69, 7), > + RK3576_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 69, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 69, 13), > + RK3576_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 69, 14), > + RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_GPU, 69, 15), > + > + /* SOFTRST_CON72 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_CENTER_BIU, 72, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 72, 5), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 72, 6), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 72, 7), > + RK3576_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 72, 8), > + RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 72, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 72, 10), > + RK3576_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 72, 11), > + RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 72, 12), > + > + /* SOFTRST_CON75 */ > + RK3576_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 75, 1), > + > + /* SOFTRST_CON78 */ > + RK3576_CRU_RESET_OFFSET(SRST_DP0_PIXELCLK, 78, 1), > + RK3576_CRU_RESET_OFFSET(SRST_PHY_DP0_TX, 78, 2), > + RK3576_CRU_RESET_OFFSET(SRST_DP1_PIXELCLK, 78, 3), > + RK3576_CRU_RESET_OFFSET(SRST_DP2_PIXELCLK, 78, 4), > + > + /* SOFTRST_CON79 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1_BIU, 79, 1), > + RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1_BIU, 79, 2), > + RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1, 79, 3), > + RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1, 79, 4), > + RK3576_CRU_RESET_OFFSET(SRST_VEPU1_CORE, 79, 5), > + > + /* PPLL_SOFTRST_CON00 */ > + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PHPPHY_CRU, 0, 1), > + RK3576_PHPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 3), > + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0, 0, 5), > + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0_GRF, 0, 6), > + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1, 0, 7), > + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1_GRF, 0, 8), > + > + /* PPLL_SOFTRST_CON01 */ > + RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE0_PIPE_PHY, 1, 5), > + RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE1_PIPE_PHY, 1, 8), > + > + /* SECURENS_SOFTRST_CON00 */ > + RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_CRYPTO_NS, 0, 3), > + RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_TRNG_NS, 0, 4), > + RK3576_SECURENSCRU_RESET_OFFSET(SRST_P_OTPC_NS, 0, 8), > + RK3576_SECURENSCRU_RESET_OFFSET(SRST_OTPC_NS, 0, 9), > + > + /* PMU1_SOFTRST_CON00 */ > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_GRF, 0, 0), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_APB, 0, 1), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY, 0, 2), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_DCPHY_GRF, 0, 3), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT0_APB2ASB, 0, 4), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT1_APB2ASB, 0, 5), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_USB2DEBUG, 0, 6), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY_GRF, 0, 7), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY, 0, 8), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_0, 0, 9), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_1, 0, 10), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDP_GRF, 0, 11), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDPPHY, 0, 12), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_INIT, 0, 15), > + > + /* PMU1_SOFTRST_CON01 */ > + RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_CMN, 1, 0), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_LANE, 1, 1), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_PCS, 1, 2), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY, 1, 3), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY, 1, 4), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_SCAN_CSIPHY, 1, 5), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO6_IOC, 1, 6), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_0, 1, 7), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_1, 1, 8), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_INIT, 1, 9), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_CMN, 1, 10), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_LANE, 1, 11), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_HDMITXHPD, 1, 13), > + > + /* PMU1_SOFTRST_CON02 */ > + RK3576_PMU1CRU_RESET_OFFSET(SRST_MPHY_INIT, 2, 0), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MPHY_GRF, 2, 1), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO7_IOC, 2, 3), > + > + /* PMU1_SOFTRST_CON03 */ > + RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 3, 9), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_NIU, 3, 10), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 3, 11), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_CORE, 3, 12), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_JTAG, 3, 13), > + > + /* PMU1_SOFTRST_CON04 */ > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 4, 1), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 4, 3), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 4, 4), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 4, 5), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 4, 6), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMUTIMER, 4, 7), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER0, 4, 9), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER1, 4, 10), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 4, 11), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 4, 12), > + > + /* PMU1_SOFTRST_CON05 */ > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 5, 1), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_I2C0, 5, 2), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_S_UART1, 5, 5), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_UART1, 5, 6), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_PDM0, 5, 13), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 5, 15), > + > + /* PMU1_SOFTRST_CON06 */ > + RK3576_PMU1CRU_RESET_OFFSET(SRST_M_PDM0, 6, 0), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 6, 1), > + > + /* PMU1_SOFTRST_CON07 */ > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 7, 4), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 7, 5), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 7, 6), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_DB_GPIO0, 7, 7), > +}; > + > +void rk3576_rst_init(struct device_node *np, void __iomem *reg_base) > +{ > + rockchip_register_softrst_lut(np, > + rk3576_register_offset, > + ARRAY_SIZE(rk3576_register_offset), > + reg_base + RK3576_SOFTRST_CON(0), > + ROCKCHIP_SOFTRST_HIWORD_MASK); > +} > + From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 510ACC52D7B for ; Tue, 13 Aug 2024 07:49:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:To:Subject:Cc: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WwBiCfsq1VYaZ8PYsVJS88o7iN5pLbB3bf3a+Xq88cU=; b=k8WmWOC7rjEAU7 4IkqFPZglgscJFo/rpJxqUr+tjtgVz5+VGn1LJtavZrP5iCIPlDqgqBmYm6M0Y/0YWOfoKiP1QNtz oIM6BnVErVwCd92E4eNb51aTp5MwIDXroTQ0wbkKg5dTwVhoZqFaaKQ4Yi72/XpVgoIBN3xrkJzkC eUGPT9tXntS6Du7IlmXAphHUai2EdyHQL4j6wP5gERYMEKRZIP6zILAFDIzRab8pw1pCDRU2oe1Ur hK9fZrP5TdyRDI/WLBaztmJEe+3bU7+YZPNIvRgxpaex+52w8b16u+8GEJsxeXeXh6ATuNqWx5iwY Mu1MJAUxlhIQFKXfjg1g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sdmHa-00000002mqK-1NLO; Tue, 13 Aug 2024 07:49:30 +0000 Received: from mail-m155115.qiye.163.com ([101.71.155.115]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sdmFM-00000002mU4-2VJW; Tue, 13 Aug 2024 07:47:17 +0000 DKIM-Signature: a=rsa-sha256; b=BZheOnnpdPhgXm0LM85wZhawyWDnNS2PmQ7fs4Rd8IWDRuNvmDdFKUCiQC/1l2Ps6ZR6Bf/pzlHYb0nVC7HByvYMVVpDlqzuuH7YX6MW1LgklEnCfOq/Q9O18yFNRYUlCuLuyASBVzcXH6pnp6hyMxkOWTi/AcFscSdZfPY679A=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=+eGUbbqfyIAVWNh2RbP2Of+Y0aBF87hxxFFq/iXNQFA=; h=date:mime-version:subject:message-id:from; Received: from [172.16.12.45] (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTPA id A436D460573; Tue, 13 Aug 2024 15:46:51 +0800 (CST) Message-ID: Date: Tue, 13 Aug 2024 15:46:50 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Cc: shawn.lin@rock-chips.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Philipp Zabel , Elaine Zhang , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@collabora.com, Finley Xiao , YouMin Chen , Liang Chen , Sugar Zhang Subject: Re: [PATCH v4 3/3] clk: rockchip: Add clock controller for the RK3576 To: Detlev Casanova , linux-kernel@vger.kernel.org References: <20240809125553.3889-1-detlev.casanova@collabora.com> <20240809125553.3889-4-detlev.casanova@collabora.com> Content-Language: en-GB From: Shawn Lin In-Reply-To: <20240809125553.3889-4-detlev.casanova@collabora.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQxpOTlZNGBpJH01DHkofQkJWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a914ab4416f03aekunma436d460573 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Mzo6Kgw*FjI#E0o5TDhRKAg0 Sz0KCUtVSlVKTElITkhOSUpIQ0NCVTMWGhIXVQgTGgwVVRcSFTsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUpISkxLQjcG X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: base64 Content-Type: text/plain; charset="utf-8"; Format="flowed" Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org 5ZyoIDIwMjQvOC85IDIwOjU0LCBEZXRsZXYgQ2FzYW5vdmEg5YaZ6YGTOgo+IEZyb206IEVsYWlu ZSBaaGFuZyA8emhhbmdxaW5nQHJvY2stY2hpcHMuY29tPgo+IAo+IEFkZCB0aGUgY2xvY2sgYW5k IHJlc2V0IHRyZWUgZGVmaW5pdGlvbnMgZm9yIHRoZSBuZXcgUkszNTc2Cj4gU29DLgo+IAo+IFNp Z25lZC1vZmYtYnk6IEVsYWluZSBaaGFuZyA8emhhbmdxaW5nQHJvY2stY2hpcHMuY29tPgo+IFNp Z25lZC1vZmYtYnk6IEZpbmxleSBYaWFvIDxmaW5sZXkueGlhb0Byb2NrLWNoaXBzLmNvbT4KPiBT aWduZWQtb2ZmLWJ5OiBZb3VNaW4gQ2hlbiA8Y3ltQHJvY2stY2hpcHMuY29tPgo+IFNpZ25lZC1v ZmYtYnk6IExpYW5nIENoZW4gPGNsQHJvY2stY2hpcHMuY29tPgo+IFNpZ25lZC1vZmYtYnk6IFN1 Z2FyIFpoYW5nIDxzdWdhci56aGFuZ0Byb2NrLWNoaXBzLmNvbT4KPiBbcmViYXNlLCBzcXVhc2gg YW5kIHJlbnVtYmVyIHJlc2V0c10KPiBTaWduZWQtb2ZmLWJ5OiBEZXRsZXYgQ2FzYW5vdmEgPGRl dGxldi5jYXNhbm92YUBjb2xsYWJvcmEuY29tPgoKVGVzdGVkLWJ5OiBTaGF3biBMaW4gPHNoYXdu LmxpbkByb2NrLWNoaXBzLmNvbT4KCgo+IC0tLQo+ICAgZHJpdmVycy9jbGsvcm9ja2NoaXAvS2Nv bmZpZyAgICAgIHwgICAgNyArCj4gICBkcml2ZXJzL2Nsay9yb2NrY2hpcC9NYWtlZmlsZSAgICAg fCAgICAxICsKPiAgIGRyaXZlcnMvY2xrL3JvY2tjaGlwL2Nsay1yazM1NzYuYyB8IDE4MTkgKysr KysrKysrKysrKysrKysrKysrKysrKysrKysKPiAgIGRyaXZlcnMvY2xrL3JvY2tjaGlwL2Nsay5o ICAgICAgICB8ICAgNTMgKwo+ICAgZHJpdmVycy9jbGsvcm9ja2NoaXAvcnN0LXJrMzU3Ni5jIHwg IDY1MiArKysrKysrKysrKwo+ICAgNSBmaWxlcyBjaGFuZ2VkLCAyNTMyIGluc2VydGlvbnMoKykK PiAgIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2Nsay9yb2NrY2hpcC9jbGstcmszNTc2LmMK PiAgIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2Nsay9yb2NrY2hpcC9yc3QtcmszNTc2LmMK PiAKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9jbGsvcm9ja2NoaXAvS2NvbmZpZyBiL2RyaXZlcnMv Y2xrL3JvY2tjaGlwL0tjb25maWcKPiBpbmRleCA5YWFkODY5MjVjZDI4Li5mOGViMTZmMTcwZDQ4 IDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvY2xrL3JvY2tjaGlwL0tjb25maWcKPiArKysgYi9kcml2 ZXJzL2Nsay9yb2NrY2hpcC9LY29uZmlnCj4gQEAgLTEwMCw2ICsxMDAsMTMgQEAgY29uZmlnIENM S19SSzM1NjgKPiAgIAloZWxwCj4gICAJICBCdWlsZCB0aGUgZHJpdmVyIGZvciBSSzM1NjggQ2xv Y2sgRHJpdmVyLgo+ICAgCj4gK2NvbmZpZyBDTEtfUkszNTc2Cj4gKwl0cmlzdGF0ZSAiUm9ja2No aXAgUkszNTc2IGNsb2NrIGNvbnRyb2xsZXIgc3VwcG9ydCIKPiArCWRlcGVuZHMgb24gQVJNNjQg fHwgQ09NUElMRV9URVNUCj4gKwlkZWZhdWx0IHkKPiArCWhlbHAKPiArCSAgQnVpbGQgdGhlIGRy aXZlciBmb3IgUkszNTc2IENsb2NrIERyaXZlci4KPiArCj4gICBjb25maWcgQ0xLX1JLMzU4OAo+ ICAgCWJvb2wgIlJvY2tjaGlwIFJLMzU4OCBjbG9jayBjb250cm9sbGVyIHN1cHBvcnQiCj4gICAJ ZGVwZW5kcyBvbiBBUk02NCB8fCBDT01QSUxFX1RFU1QKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9j bGsvcm9ja2NoaXAvTWFrZWZpbGUgYi9kcml2ZXJzL2Nsay9yb2NrY2hpcC9NYWtlZmlsZQo+IGlu ZGV4IDM2ODk0ZjZhNzAyMmQuLmFmMmFkZTU0YTdlZmEgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9j bGsvcm9ja2NoaXAvTWFrZWZpbGUKPiArKysgYi9kcml2ZXJzL2Nsay9yb2NrY2hpcC9NYWtlZmls ZQo+IEBAIC0yOCw0ICsyOCw1IEBAIG9iai0kKENPTkZJR19DTEtfUkszMzI4KSAgICAgICAgKz0g Y2xrLXJrMzMyOC5vCj4gICBvYmotJChDT05GSUdfQ0xLX1JLMzM2OCkgICAgICAgICs9IGNsay1y azMzNjgubwo+ICAgb2JqLSQoQ09ORklHX0NMS19SSzMzOTkpICAgICAgICArPSBjbGstcmszMzk5 Lm8KPiAgIG9iai0kKENPTkZJR19DTEtfUkszNTY4KQkrPSBjbGstcmszNTY4Lm8KPiArb2JqLSQo Q09ORklHX0NMS19SSzM1NzYpCSs9IGNsay1yazM1NzYubyByc3QtcmszNTc2Lm8KPiAgIG9iai0k KENPTkZJR19DTEtfUkszNTg4KQkrPSBjbGstcmszNTg4Lm8gcnN0LXJrMzU4OC5vCj4gZGlmZiAt LWdpdCBhL2RyaXZlcnMvY2xrL3JvY2tjaGlwL2Nsay1yazM1NzYuYyBiL2RyaXZlcnMvY2xrL3Jv Y2tjaGlwL2Nsay1yazM1NzYuYwo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4gaW5kZXggMDAwMDAw MDAwMDAwMC4uYTU3OGRkODhmYTkzMQo+IC0tLSAvZGV2L251bGwKPiArKysgYi9kcml2ZXJzL2Ns ay9yb2NrY2hpcC9jbGstcmszNTc2LmMKPiBAQCAtMCwwICsxLDE4MTkgQEAKPiArLy8gU1BEWC1M aWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjAKPiArLyoKPiArICogQ29weXJpZ2h0IChjKSAyMDIz IFJvY2tjaGlwIEVsZWN0cm9uaWNzIENvLiBMdGQuCj4gKyAqIEF1dGhvcjogRWxhaW5lIFpoYW5n IDx6aGFuZ3FpbmdAcm9jay1jaGlwcy5jb20+Cj4gKyAqLwo+ICsKPiArI2luY2x1ZGUgPGxpbnV4 L2Nsay1wcm92aWRlci5oPgo+ICsjaW5jbHVkZSA8bGludXgvbW9kdWxlLmg+Cj4gKyNpbmNsdWRl IDxsaW51eC9vZi5oPgo+ICsjaW5jbHVkZSA8bGludXgvb2ZfZGV2aWNlLmg+Cj4gKyNpbmNsdWRl IDxsaW51eC9vZl9hZGRyZXNzLmg+Cj4gKyNpbmNsdWRlIDxsaW51eC9zeXNjb3JlX29wcy5oPgo+ ICsjaW5jbHVkZSA8ZHQtYmluZGluZ3MvY2xvY2svcm9ja2NoaXAscmszNTc2LWNydS5oPgo+ICsj aW5jbHVkZSAiY2xrLmgiCj4gKwo+ICsjZGVmaW5lIFJLMzU3Nl9HUkZfU09DX1NUQVRVUzAJCTB4 NjAwCj4gKyNkZWZpbmUgUkszNTc2X1BNVTBfR1JGX09TQ19DT042CTB4MTgKPiArCj4gK2VudW0g cmszNTc2X3BsbHMgewo+ICsJYnBsbCwgbHBsbCwgdnBsbCwgYXVwbGwsIGNwbGwsIGdwbGwsIHBw bGwsCj4gK307Cj4gKwo+ICtzdGF0aWMgc3RydWN0IHJvY2tjaGlwX3BsbF9yYXRlX3RhYmxlIHJr MzU3Nl9wbGxfcmF0ZXNbXSA9IHsKPiArCS8qIF9taHosIF9wLCBfbSwgX3MsIF9rICovCj4gKwlS SzM1ODhfUExMX1JBVEUoMjUyMDAwMDAwMCwgMiwgMjEwLCAwLCAwKSwKPiArCVJLMzU4OF9QTExf UkFURSgyNDk2MDAwMDAwLCAyLCAyMDgsIDAsIDApLAo+ICsJUkszNTg4X1BMTF9SQVRFKDI0NzIw MDAwMDAsIDIsIDIwNiwgMCwgMCksCj4gKwlSSzM1ODhfUExMX1JBVEUoMjQ0ODAwMDAwMCwgMiwg MjA0LCAwLCAwKSwKPiArCVJLMzU4OF9QTExfUkFURSgyNDI0MDAwMDAwLCAyLCAyMDIsIDAsIDAp LAo+ICsJUkszNTg4X1BMTF9SQVRFKDI0MDAwMDAwMDAsIDIsIDIwMCwgMCwgMCksCj4gKwlSSzM1 ODhfUExMX1JBVEUoMjM3NjAwMDAwMCwgMiwgMTk4LCAwLCAwKSwKPiArCVJLMzU4OF9QTExfUkFU RSgyMzUyMDAwMDAwLCAyLCAxOTYsIDAsIDApLAo+ICsJUkszNTg4X1BMTF9SQVRFKDIzMjgwMDAw MDAsIDIsIDE5NCwgMCwgMCksCj4gKwlSSzM1ODhfUExMX1JBVEUoMjMwNDAwMDAwMCwgMiwgMTky LCAwLCAwKSwKPiArCVJLMzU4OF9QTExfUkFURSgyMjgwMDAwMDAwLCAyLCAxOTAsIDAsIDApLAo+ ICsJUkszNTg4X1BMTF9SQVRFKDIyNTYwMDAwMDAsIDIsIDM3NiwgMSwgMCksCj4gKwlSSzM1ODhf UExMX1JBVEUoMjIzMjAwMDAwMCwgMiwgMzcyLCAxLCAwKSwKPiArCVJLMzU4OF9QTExfUkFURSgy MjA4MDAwMDAwLCAyLCAzNjgsIDEsIDApLAo+ICsJUkszNTg4X1BMTF9SQVRFKDIxODQwMDAwMDAs IDIsIDM2NCwgMSwgMCksCj4gKwlSSzM1ODhfUExMX1JBVEUoMjE2MDAwMDAwMCwgMiwgMzYwLCAx LCAwKSwKPiArCVJLMzU4OF9QTExfUkFURSgyMTM2MDAwMDAwLCAyLCAzNTYsIDEsIDApLAo+ICsJ UkszNTg4X1BMTF9SQVRFKDIxMTIwMDAwMDAsIDIsIDM1MiwgMSwgMCksCj4gKwlSSzM1ODhfUExM X1JBVEUoMjA4ODAwMDAwMCwgMiwgMzQ4LCAxLCAwKSwKPiArCVJLMzU4OF9QTExfUkFURSgyMDY0 MDAwMDAwLCAyLCAzNDQsIDEsIDApLAo+ICsJUkszNTg4X1BMTF9SQVRFKDIwNDAwMDAwMDAsIDIs IDM0MCwgMSwgMCksCj4gKwlSSzM1ODhfUExMX1JBVEUoMjAxNjAwMDAwMCwgMiwgMzM2LCAxLCAw KSwKPiArCVJLMzU4OF9QTExfUkFURSgxOTkyMDAwMDAwLCAyLCAzMzIsIDEsIDApLAo+ICsJUksz NTg4X1BMTF9SQVRFKDE5NjgwMDAwMDAsIDIsIDMyOCwgMSwgMCksCj4gKwlSSzM1ODhfUExMX1JB VEUoMTk0NDAwMDAwMCwgMiwgMzI0LCAxLCAwKSwKPiArCVJLMzU4OF9QTExfUkFURSgxOTIwMDAw MDAwLCAyLCAzMjAsIDEsIDApLAo+ICsJUkszNTg4X1BMTF9SQVRFKDE4OTYwMDAwMDAsIDIsIDMx NiwgMSwgMCksCj4gKwlSSzM1ODhfUExMX1JBVEUoMTg3MjAwMDAwMCwgMiwgMzEyLCAxLCAwKSwK PiArCVJLMzU4OF9QTExfUkFURSgxODQ4MDAwMDAwLCAyLCAzMDgsIDEsIDApLAo+ICsJUkszNTg4 X1BMTF9SQVRFKDE4MjQwMDAwMDAsIDIsIDMwNCwgMSwgMCksCj4gKwlSSzM1ODhfUExMX1JBVEUo MTgwMDAwMDAwMCwgMiwgMzAwLCAxLCAwKSwKPiArCVJLMzU4OF9QTExfUkFURSgxNzc2MDAwMDAw LCAyLCAyOTYsIDEsIDApLAo+ICsJUkszNTg4X1BMTF9SQVRFKDE3NTIwMDAwMDAsIDIsIDI5Miwg MSwgMCksCj4gKwlSSzM1ODhfUExMX1JBVEUoMTcyODAwMDAwMCwgMiwgMjg4LCAxLCAwKSwKPiAr CVJLMzU4OF9QTExfUkFURSgxNzA0MDAwMDAwLCAyLCAyODQsIDEsIDApLAo+ICsJUkszNTg4X1BM TF9SQVRFKDE2ODAwMDAwMDAsIDIsIDI4MCwgMSwgMCksCj4gKwlSSzM1ODhfUExMX1JBVEUoMTY1 NjAwMDAwMCwgMiwgMjc2LCAxLCAwKSwKPiArCVJLMzU4OF9QTExfUkFURSgxNjMyMDAwMDAwLCAy LCAyNzIsIDEsIDApLAo+ICsJUkszNTg4X1BMTF9SQVRFKDE2MDgwMDAwMDAsIDIsIDI2OCwgMSwg MCksCj4gKwlSSzM1ODhfUExMX1JBVEUoMTU4NDAwMDAwMCwgMiwgMjY0LCAxLCAwKSwKPiArCVJL MzU4OF9QTExfUkFURSgxNTYwMDAwMDAwLCAyLCAyNjAsIDEsIDApLAo+ICsJUkszNTg4X1BMTF9S QVRFKDE1MzYwMDAwMDAsIDIsIDI1NiwgMSwgMCksCj4gKwlSSzM1ODhfUExMX1JBVEUoMTUxMjAw MDAwMCwgMiwgMjUyLCAxLCAwKSwKPiArCVJLMzU4OF9QTExfUkFURSgxNDg4MDAwMDAwLCAyLCAy NDgsIDEsIDApLAo+ICsJUkszNTg4X1BMTF9SQVRFKDE0NjQwMDAwMDAsIDIsIDI0NCwgMSwgMCks Cj4gKwlSSzM1ODhfUExMX1JBVEUoMTQ0MDAwMDAwMCwgMiwgMjQwLCAxLCAwKSwKPiArCVJLMzU4 OF9QTExfUkFURSgxNDE2MDAwMDAwLCAyLCAyMzYsIDEsIDApLAo+ICsJUkszNTg4X1BMTF9SQVRF KDEzOTIwMDAwMDAsIDIsIDIzMiwgMSwgMCksCj4gKwlSSzM1ODhfUExMX1JBVEUoMTMyMDAwMDAw MCwgMiwgMjIwLCAxLCAwKSwKPiArCVJLMzU4OF9QTExfUkFURSgxMjAwMDAwMDAwLCAyLCAyMDAs IDEsIDApLAo+ICsJUkszNTg4X1BMTF9SQVRFKDExODgwMDAwMDAsIDIsIDE5OCwgMSwgMCksCj4g KwlSSzM1ODhfUExMX1JBVEUoMTEwMDAwMDAwMCwgMywgNTUwLCAyLCAwKSwKPiArCVJLMzU4OF9Q TExfUkFURSgxMDA4MDAwMDAwLCAyLCAzMzYsIDIsIDApLAo+ICsJUkszNTg4X1BMTF9SQVRFKDEw MDAwMDAwMDAsIDMsIDUwMCwgMiwgMCksCj4gKwlSSzM1ODhfUExMX1JBVEUoOTgzMDQwMDAwLCA0 LCA2NTUsIDIsIDIzNTkyKSwKPiArCVJLMzU4OF9QTExfUkFURSg5NTU1MjAwMDAsIDMsIDQ3Nywg MiwgNDk4MDYpLAo+ICsJUkszNTg4X1BMTF9SQVRFKDkwMzE2ODAwMCwgNiwgOTAzLCAyLCAxMTAw OSksCj4gKwlSSzM1ODhfUExMX1JBVEUoOTAwMDAwMDAwLCAyLCAzMDAsIDIsIDApLAo+ICsJUksz NTg4X1BMTF9SQVRFKDgxNjAwMDAwMCwgMiwgMjcyLCAyLCAwKSwKPiArCVJLMzU4OF9QTExfUkFU RSg3ODY0MzIwMDAsIDIsIDI2MiwgMiwgOTQzNyksCj4gKwlSSzM1ODhfUExMX1JBVEUoNzg2MDAw MDAwLCAxLCAxMzEsIDIsIDApLAo+ICsJUkszNTg4X1BMTF9SQVRFKDc4NTU2MDAwMCwgMywgMzky LCAyLCA1MTExNyksCj4gKwlSSzM1ODhfUExMX1JBVEUoNzIyNTM0NDAwLCA4LCA5NjMsIDIsIDI0 ODUwKSwKPiArCVJLMzU4OF9QTExfUkFURSg2MDAwMDAwMDAsIDIsIDIwMCwgMiwgMCksCj4gKwlS SzM1ODhfUExMX1JBVEUoNTk0MDAwMDAwLCAyLCAxOTgsIDIsIDApLAo+ICsJUkszNTg4X1BMTF9S QVRFKDQwODAwMDAwMCwgMiwgMjcyLCAzLCAwKSwKPiArCVJLMzU4OF9QTExfUkFURSgzMTIwMDAw MDAsIDIsIDIwOCwgMywgMCksCj4gKwlSSzM1ODhfUExMX1JBVEUoMjE2MDAwMDAwLCAyLCAyODgs IDQsIDApLAo+ICsJUkszNTg4X1BMTF9SQVRFKDk2MDAwMDAwLCAyLCAyNTYsIDUsIDApLAo+ICsJ eyAvKiBzZW50aW5lbCAqLyB9LAo+ICt9Owo+ICsKPiArc3RhdGljIHN0cnVjdCByb2NrY2hpcF9w bGxfcmF0ZV90YWJsZSByazM1NzZfcHBsbF9yYXRlc1tdID0gewo+ICsJLyogX21oeiwgX3AsIF9t LCBfcywgX2sgKi8KPiArCVJLMzU4OF9QTExfUkFURSgxMzAwMDAwMDAwLCAzLCAzMjUsIDIsIDAp LAo+ICsJeyAvKiBzZW50aW5lbCAqLyB9LAo+ICt9Owo+ICsKPiArI2RlZmluZSBSSzM1NzZfQUNM S19NX0JJR0NPUkVfRElWX01BU0sJCTB4MWYKPiArI2RlZmluZSBSSzM1NzZfQUNMS19NX0JJR0NP UkVfRElWX1NISUZUCQkwCj4gKyNkZWZpbmUgUkszNTc2X0FDTEtfTV9MSVRDT1JFX0RJVl9NQVNL CQkweDFmCj4gKyNkZWZpbmUgUkszNTc2X0FDTEtfTV9MSVRDT1JFX0RJVl9TSElGVAkJOAo+ICsj ZGVmaW5lIFJLMzU3Nl9QQ0xLX0RCR19MSVRDT1JFX0RJVl9NQVNLCTB4MWYKPiArI2RlZmluZSBS SzM1NzZfUENMS19EQkdfTElUQ09SRV9ESVZfU0hJRlQJMAo+ICsjZGVmaW5lIFJLMzU3Nl9BQ0xL X0NDSV9ESVZfTUFTSwkJMHgxZgo+ICsjZGVmaW5lIFJLMzU3Nl9BQ0xLX0NDSV9ESVZfU0hJRlQJ CTcKPiArI2RlZmluZSBSSzM1NzZfQUNMS19DQ0lfTVVYX01BU0sJCTB4Mwo+ICsjZGVmaW5lIFJL MzU3Nl9BQ0xLX0NDSV9NVVhfU0hJRlQJCTEyCj4gKwo+ICsjZGVmaW5lIFJLMzU3Nl9CSUdDT1JF X0NMS1NFTDIoX2FtY29yZSkJCQkJCQlcCj4gK3sJCQkJCQkJCQkJXAo+ICsJLnJlZyA9IFJLMzU3 Nl9CSUdDT1JFX0NMS1NFTF9DT04oMiksCQkJCQlcCj4gKwkudmFsID0gSElXT1JEX1VQREFURShf YW1jb3JlIC0gMSwgUkszNTc2X0FDTEtfTV9CSUdDT1JFX0RJVl9NQVNLLAlcCj4gKwkJCVJLMzU3 Nl9BQ0xLX01fQklHQ09SRV9ESVZfU0hJRlQpLAkJCVwKPiArfQo+ICsKPiArI2RlZmluZSBSSzM1 NzZfTElUQ09SRV9DTEtTRUwxKF9hbWNvcmUpCQkJCQkJXAo+ICt7CQkJCQkJCQkJCVwKPiArCS5y ZWcgPSBSSzM1NzZfTElUQ09SRV9DTEtTRUxfQ09OKDEpLAkJCQkJXAo+ICsJLnZhbCA9IEhJV09S RF9VUERBVEUoX2FtY29yZSAtIDEsIFJLMzU3Nl9BQ0xLX01fTElUQ09SRV9ESVZfTUFTSywJXAo+ ICsJCQlSSzM1NzZfQUNMS19NX0xJVENPUkVfRElWX1NISUZUKSwJCQlcCj4gK30KPiArCj4gKyNk ZWZpbmUgUkszNTc2X0xJVENPUkVfQ0xLU0VMMihfcGNsa2RiZykJCQkJCVwKPiArewkJCQkJCQkJ CQlcCj4gKwkucmVnID0gUkszNTc2X0xJVENPUkVfQ0xLU0VMX0NPTigyKSwJCQkJCVwKPiArCS52 YWwgPSBISVdPUkRfVVBEQVRFKF9wY2xrZGJnIC0gMSwgUkszNTc2X1BDTEtfREJHX0xJVENPUkVf RElWX01BU0ssCVwKPiArCQkJUkszNTc2X1BDTEtfREJHX0xJVENPUkVfRElWX1NISUZUKSwJCQlc Cj4gK30KPiArCj4gKyNkZWZpbmUgUkszNTc2X0NDSV9DTEtTRUw0KF9jY2lzZWwsIF9kaXYpCQkJ CQlcCj4gK3sJCQkJCQkJCQkJXAo+ICsJLnJlZyA9IFJLMzU3Nl9DQ0lfQ0xLU0VMX0NPTig0KSwJ CQkJCVwKPiArCS52YWwgPSBISVdPUkRfVVBEQVRFKF9jY2lzZWwsIFJLMzU3Nl9BQ0xLX0NDSV9N VVhfTUFTSywJCQlcCj4gKwkJCVJLMzU3Nl9BQ0xLX0NDSV9NVVhfU0hJRlQpIHwJCQkJXAo+ICsJ ICAgICAgIEhJV09SRF9VUERBVEUoX2RpdiAtIDEsIFJLMzU3Nl9BQ0xLX0NDSV9ESVZfTUFTSywJ CVwKPiArCQkJUkszNTc2X0FDTEtfQ0NJX0RJVl9TSElGVCksCQkJCVwKPiArfQo+ICsKPiArI2Rl ZmluZSBSSzM1NzZfQ1BVQkNMS19SQVRFKF9wcmF0ZSwgX2FtY29yZSkJCQkJCVwKPiArewkJCQkJ CQkJCQlcCj4gKwkucHJhdGUgPSBfcHJhdGUjI1UsCQkJCQkJCVwKPiArCS5kaXZzID0gewkJCQkJ CQkJXAo+ICsJCVJLMzU3Nl9CSUdDT1JFX0NMS1NFTDIoX2FtY29yZSksCQkJCVwKPiArCX0sCQkJ CQkJCQkJXAo+ICt9Cj4gKwo+ICsjZGVmaW5lIFJLMzU3Nl9DUFVMQ0xLX1JBVEUoX3ByYXRlLCBf YW1jb3JlLCBfcGNsa2RiZywgX2NjaXNlbCkJCQlcCj4gK3sJCQkJCQkJCQkJXAo+ICsJLnByYXRl ID0gX3ByYXRlIyNVLAkJCQkJCQlcCj4gKwkuZGl2cyA9IHsJCQkJCQkJCVwKPiArCQlSSzM1NzZf TElUQ09SRV9DTEtTRUwxKF9hbWNvcmUpLAkJCQlcCj4gKwkJUkszNTc2X0xJVENPUkVfQ0xLU0VM MihfcGNsa2RiZyksCQkJCVwKPiArCX0sCQkJCQkJCQkJXAo+ICsJLnByZV9tdXhzID0gewkJCQkJ CQkJXAo+ICsJCVJLMzU3Nl9DQ0lfQ0xLU0VMNCgyLCAyKSwJCQkJCVwKPiArCX0sCQkJCQkJCQkJ XAo+ICsJLnBvc3RfbXV4cyA9IHsJCQkJCQkJCVwKPiArCQlSSzM1NzZfQ0NJX0NMS1NFTDQoX2Nj aXNlbCwgMiksCQkJCQlcCj4gKwl9LAkJCQkJCQkJCVwKPiArfQo+ICsKPiArc3RhdGljIHN0cnVj dCByb2NrY2hpcF9jcHVjbGtfcmF0ZV90YWJsZSByazM1NzZfY3B1YmNsa19yYXRlc1tdIF9faW5p dGRhdGEgPSB7Cj4gKwlSSzM1NzZfQ1BVQkNMS19SQVRFKDI0OTYwMDAwMDAsIDIpLAo+ICsJUksz NTc2X0NQVUJDTEtfUkFURSgyNDAwMDAwMDAwLCAyKSwKPiArCVJLMzU3Nl9DUFVCQ0xLX1JBVEUo MjMwNDAwMDAwMCwgMiksCj4gKwlSSzM1NzZfQ1BVQkNMS19SQVRFKDIyMDgwMDAwMDAsIDIpLAo+ ICsJUkszNTc2X0NQVUJDTEtfUkFURSgyMTg0MDAwMDAwLCAyKSwKPiArCVJLMzU3Nl9DUFVCQ0xL X1JBVEUoMjA4ODAwMDAwMCwgMiksCj4gKwlSSzM1NzZfQ1BVQkNMS19SQVRFKDIwNDAwMDAwMDAs IDIpLAo+ICsJUkszNTc2X0NQVUJDTEtfUkFURSgyMDE2MDAwMDAwLCAyKSwKPiArCVJLMzU3Nl9D UFVCQ0xLX1JBVEUoMTk5MjAwMDAwMCwgMiksCj4gKwlSSzM1NzZfQ1BVQkNMS19SQVRFKDE4OTYw MDAwMDAsIDIpLAo+ICsJUkszNTc2X0NQVUJDTEtfUkFURSgxODAwMDAwMDAwLCAyKSwKPiArCVJL MzU3Nl9DUFVCQ0xLX1JBVEUoMTcwNDAwMDAwMCwgMiksCj4gKwlSSzM1NzZfQ1BVQkNMS19SQVRF KDE2MDgwMDAwMDAsIDIpLAo+ICsJUkszNTc2X0NQVUJDTEtfUkFURSgxNTg0MDAwMDAwLCAyKSwK PiArCVJLMzU3Nl9DUFVCQ0xLX1JBVEUoMTU2MDAwMDAwMCwgMiksCj4gKwlSSzM1NzZfQ1BVQkNM S19SQVRFKDE1MzYwMDAwMDAsIDIpLAo+ICsJUkszNTc2X0NQVUJDTEtfUkFURSgxNTEyMDAwMDAw LCAyKSwKPiArCVJLMzU3Nl9DUFVCQ0xLX1JBVEUoMTQ4ODAwMDAwMCwgMiksCj4gKwlSSzM1NzZf Q1BVQkNMS19SQVRFKDE0NjQwMDAwMDAsIDIpLAo+ICsJUkszNTc2X0NQVUJDTEtfUkFURSgxNDQw MDAwMDAwLCAyKSwKPiArCVJLMzU3Nl9DUFVCQ0xLX1JBVEUoMTQxNjAwMDAwMCwgMiksCj4gKwlS SzM1NzZfQ1BVQkNMS19SQVRFKDEzOTIwMDAwMDAsIDIpLAo+ICsJUkszNTc2X0NQVUJDTEtfUkFU RSgxMzY4MDAwMDAwLCAyKSwKPiArCVJLMzU3Nl9DUFVCQ0xLX1JBVEUoMTM0NDAwMDAwMCwgMiks Cj4gKwlSSzM1NzZfQ1BVQkNMS19SQVRFKDEzMjAwMDAwMDAsIDIpLAo+ICsJUkszNTc2X0NQVUJD TEtfUkFURSgxMjk2MDAwMDAwLCAyKSwKPiArCVJLMzU3Nl9DUFVCQ0xLX1JBVEUoMTI3MjAwMDAw MCwgMiksCj4gKwlSSzM1NzZfQ1BVQkNMS19SQVRFKDEyNDgwMDAwMDAsIDIpLAo+ICsJUkszNTc2 X0NQVUJDTEtfUkFURSgxMjI0MDAwMDAwLCAyKSwKPiArCVJLMzU3Nl9DUFVCQ0xLX1JBVEUoMTIw MDAwMDAwMCwgMiksCj4gKwlSSzM1NzZfQ1BVQkNMS19SQVRFKDExMDQwMDAwMDAsIDIpLAo+ICsJ UkszNTc2X0NQVUJDTEtfUkFURSgxMDA4MDAwMDAwLCAyKSwKPiArCVJLMzU3Nl9DUFVCQ0xLX1JB VEUoOTEyMDAwMDAwLCAyKSwKPiArCVJLMzU3Nl9DUFVCQ0xLX1JBVEUoODE2MDAwMDAwLCAyKSwK PiArCVJLMzU3Nl9DUFVCQ0xLX1JBVEUoNjk2MDAwMDAwLCAyKSwKPiArCVJLMzU3Nl9DUFVCQ0xL X1JBVEUoNjAwMDAwMDAwLCAyKSwKPiArCVJLMzU3Nl9DUFVCQ0xLX1JBVEUoNDA4MDAwMDAwLCAy KSwKPiArCVJLMzU3Nl9DUFVCQ0xLX1JBVEUoMzEyMDAwMDAwLCAyKSwKPiArCVJLMzU3Nl9DUFVC Q0xLX1JBVEUoMjE2MDAwMDAwLCAyKSwKPiArCVJLMzU3Nl9DUFVCQ0xLX1JBVEUoOTYwMDAwMDAs IDIpLAo+ICt9Owo+ICsKPiArc3RhdGljIGNvbnN0IHN0cnVjdCByb2NrY2hpcF9jcHVjbGtfcmVn X2RhdGEgcmszNTc2X2NwdWJjbGtfZGF0YSA9IHsKPiArCS5jb3JlX3JlZ1swXSA9IFJLMzU3Nl9C SUdDT1JFX0NMS1NFTF9DT04oMSksCj4gKwkuZGl2X2NvcmVfc2hpZnRbMF0gPSA3LAo+ICsJLmRp dl9jb3JlX21hc2tbMF0gPSAweDFmLAo+ICsJLm51bV9jb3JlcyA9IDEsCj4gKwkubXV4X2NvcmVf YWx0ID0gMSwKPiArCS5tdXhfY29yZV9tYWluID0gMCwKPiArCS5tdXhfY29yZV9zaGlmdCA9IDEy LAo+ICsJLm11eF9jb3JlX21hc2sgPSAweDMsCj4gK307Cj4gKwo+ICtzdGF0aWMgc3RydWN0IHJv Y2tjaGlwX2NwdWNsa19yYXRlX3RhYmxlIHJrMzU3Nl9jcHVsY2xrX3JhdGVzW10gX19pbml0ZGF0 YSA9IHsKPiArCVJLMzU3Nl9DUFVMQ0xLX1JBVEUoMjQwMDAwMDAwMCwgMiwgNiwgMyksCj4gKwlS SzM1NzZfQ1BVTENMS19SQVRFKDIzMDQwMDAwMDAsIDIsIDYsIDMpLAo+ICsJUkszNTc2X0NQVUxD TEtfUkFURSgyMjA4MDAwMDAwLCAyLCA2LCAzKSwKPiArCVJLMzU3Nl9DUFVMQ0xLX1JBVEUoMjE4 NDAwMDAwMCwgMiwgNiwgMyksCj4gKwlSSzM1NzZfQ1BVTENMS19SQVRFKDIwODgwMDAwMDAsIDIs IDYsIDMpLAo+ICsJUkszNTc2X0NQVUxDTEtfUkFURSgyMDQwMDAwMDAwLCAyLCA2LCAzKSwKPiAr CVJLMzU3Nl9DUFVMQ0xLX1JBVEUoMjAxNjAwMDAwMCwgMiwgNiwgMyksCj4gKwlSSzM1NzZfQ1BV TENMS19SQVRFKDE5OTIwMDAwMDAsIDIsIDYsIDMpLAo+ICsJUkszNTc2X0NQVUxDTEtfUkFURSgx ODk2MDAwMDAwLCAyLCA2LCAzKSwKPiArCVJLMzU3Nl9DUFVMQ0xLX1JBVEUoMTgwMDAwMDAwMCwg MiwgNiwgMyksCj4gKwlSSzM1NzZfQ1BVTENMS19SQVRFKDE3MDQwMDAwMDAsIDIsIDYsIDMpLAo+ ICsJUkszNTc2X0NQVUxDTEtfUkFURSgxNjA4MDAwMDAwLCAyLCA2LCAzKSwKPiArCVJLMzU3Nl9D UFVMQ0xLX1JBVEUoMTU4NDAwMDAwMCwgMiwgNiwgMyksCj4gKwlSSzM1NzZfQ1BVTENMS19SQVRF KDE1NjAwMDAwMDAsIDIsIDYsIDMpLAo+ICsJUkszNTc2X0NQVUxDTEtfUkFURSgxNTM2MDAwMDAw LCAyLCA2LCAzKSwKPiArCVJLMzU3Nl9DUFVMQ0xLX1JBVEUoMTUxMjAwMDAwMCwgMiwgNiwgMyks Cj4gKwlSSzM1NzZfQ1BVTENMS19SQVRFKDE0ODgwMDAwMDAsIDIsIDYsIDMpLAo+ICsJUkszNTc2 X0NQVUxDTEtfUkFURSgxNDY0MDAwMDAwLCAyLCA2LCAzKSwKPiArCVJLMzU3Nl9DUFVMQ0xLX1JB VEUoMTQ0MDAwMDAwMCwgMiwgNiwgMyksCj4gKwlSSzM1NzZfQ1BVTENMS19SQVRFKDE0MTYwMDAw MDAsIDIsIDYsIDMpLAo+ICsJUkszNTc2X0NQVUxDTEtfUkFURSgxMzkyMDAwMDAwLCAyLCA2LCAz KSwKPiArCVJLMzU3Nl9DUFVMQ0xLX1JBVEUoMTM2ODAwMDAwMCwgMiwgNiwgMyksCj4gKwlSSzM1 NzZfQ1BVTENMS19SQVRFKDEzNDQwMDAwMDAsIDIsIDYsIDMpLAo+ICsJUkszNTc2X0NQVUxDTEtf UkFURSgxMzIwMDAwMDAwLCAyLCA2LCAzKSwKPiArCVJLMzU3Nl9DUFVMQ0xLX1JBVEUoMTI5NjAw MDAwMCwgMiwgNiwgMyksCj4gKwlSSzM1NzZfQ1BVTENMS19SQVRFKDEyNzIwMDAwMDAsIDIsIDYs IDMpLAo+ICsJUkszNTc2X0NQVUxDTEtfUkFURSgxMjQ4MDAwMDAwLCAyLCA2LCAzKSwKPiArCVJL MzU3Nl9DUFVMQ0xLX1JBVEUoMTIyNDAwMDAwMCwgMiwgNiwgMyksCj4gKwlSSzM1NzZfQ1BVTENM S19SQVRFKDEyMDAwMDAwMDAsIDIsIDYsIDIpLAo+ICsJUkszNTc2X0NQVUxDTEtfUkFURSgxMTA0 MDAwMDAwLCAyLCA2LCAyKSwKPiArCVJLMzU3Nl9DUFVMQ0xLX1JBVEUoMTAwODAwMDAwMCwgMiwg NiwgMiksCj4gKwlSSzM1NzZfQ1BVTENMS19SQVRFKDkxMjAwMDAwMCwgMiwgNiwgMiksCj4gKwlS SzM1NzZfQ1BVTENMS19SQVRFKDgxNjAwMDAwMCwgMiwgNiwgMiksCj4gKwlSSzM1NzZfQ1BVTENM S19SQVRFKDY5NjAwMDAwMCwgMiwgNiwgMiksCj4gKwlSSzM1NzZfQ1BVTENMS19SQVRFKDYwMDAw MDAwMCwgMiwgNiwgMiksCj4gKwlSSzM1NzZfQ1BVTENMS19SQVRFKDQwODAwMDAwMCwgMiwgNiwg MiksCj4gKwlSSzM1NzZfQ1BVTENMS19SQVRFKDMxMjAwMDAwMCwgMiwgNiwgMiksCj4gKwlSSzM1 NzZfQ1BVTENMS19SQVRFKDIxNjAwMDAwMCwgMiwgNiwgMiksCj4gKwlSSzM1NzZfQ1BVTENMS19S QVRFKDk2MDAwMDAwLCAyLCA2LCAyKSwKPiArfTsKPiArCj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3Qg cm9ja2NoaXBfY3B1Y2xrX3JlZ19kYXRhIHJrMzU3Nl9jcHVsY2xrX2RhdGEgPSB7Cj4gKwkuY29y ZV9yZWdbMF0gPSBSSzM1NzZfTElUQ09SRV9DTEtTRUxfQ09OKDApLAo+ICsJLmRpdl9jb3JlX3No aWZ0WzBdID0gNywKPiArCS5kaXZfY29yZV9tYXNrWzBdID0gMHgxZiwKPiArCS5udW1fY29yZXMg PSAxLAo+ICsJLm11eF9jb3JlX2FsdCA9IDEsCj4gKwkubXV4X2NvcmVfbWFpbiA9IDAsCj4gKwku bXV4X2NvcmVfc2hpZnQgPSAxMiwKPiArCS5tdXhfY29yZV9tYXNrID0gMHgzLAo+ICt9Owo+ICsK PiArI2RlZmluZSBNRkxBR1MgQ0xLX01VWF9ISVdPUkRfTUFTSwo+ICsjZGVmaW5lIERGTEFHUyBD TEtfRElWSURFUl9ISVdPUkRfTUFTSwo+ICsjZGVmaW5lIEdGTEFHUyAoQ0xLX0dBVEVfSElXT1JE X01BU0sgfCBDTEtfR0FURV9TRVRfVE9fRElTQUJMRSkKPiArCj4gK1BOQU1FKG11eF9wbGxfcCkJ CQk9IHsgInhpbjI0bSIsICJ4aW4zMmsiIH07Cj4gK1BOQU1FKG11eF8yNG1fMzJrX3ApCQkJPSB7 ICJ4aW4yNG0iLCAieGluX29zYzBfZGl2IiB9Owo+ICtQTkFNRShtdXhfYXJtY2xrbF9wKQkJCT0g eyAieGluMjRtIiwgInBsbF9scGxsIiwgImxwbGwiIH07Cj4gK1BOQU1FKG11eF9hcm1jbGtiX3Ap CQkJPSB7ICJ4aW4yNG0iLCAicGxsX2JwbGwiLCAiYnBsbCIgfTsKPiArUE5BTUUoZ3BsbF8yNG1f cCkJCQk9IHsgImdwbGwiLCAieGluMjRtIiB9Owo+ICtQTkFNRShjcGxsXzI0bV9wKQkJCT0geyAi Y3BsbCIsICJ4aW4yNG0iIH07Cj4gK1BOQU1FKGdwbGxfY3BsbF9wKQkJCT0geyAiZ3BsbCIsICJj cGxsIiB9Owo+ICtQTkFNRShncGxsX3NwbGxfcCkJCQk9IHsgImdwbGwiLCAic3BsbCIgfTsKPiAr UE5BTUUoZ3BsbF9jcGxsX2F1cGxsX3ApCQk9IHsgImdwbGwiLCAiY3BsbCIsICJhdXBsbCIgfTsK PiArUE5BTUUoZ3BsbF9jcGxsXzI0bV9wKQkJCT0geyAiZ3BsbCIsICJjcGxsIiwgInhpbjI0bSIg fTsKPiArUE5BTUUoZ3BsbF9jcGxsXzI0bV9zcGxsX3ApCQk9IHsgImdwbGwiLCAiY3BsbCIsICJ4 aW4yNG0iLCAic3BsbCIgfTsKPiArUE5BTUUoZ3BsbF9jcGxsX2F1cGxsXzI0bV9wKQkJPSB7ICJn cGxsIiwgImNwbGwiLCAiYXVwbGwiLCAieGluMjRtIiB9Owo+ICtQTkFNRShncGxsX2NwbGxfYXVw bGxfc3BsbF9wKQkJPSB7ICJncGxsIiwgImNwbGwiLCAiYXVwbGwiLCAic3BsbCIgfTsKPiArUE5B TUUoZ3BsbF9jcGxsX2F1cGxsX3NwbGxfbHBsbF9wKQk9IHsgImdwbGwiLCAiY3BsbCIsICJhdXBs bCIsICJzcGxsIiwgImxwbGxfZHVtbXkiIH07Cj4gK1BOQU1FKGdwbGxfY3BsbF9zcGxsX2JwbGxf cCkJCT0geyAiZ3BsbCIsICJjcGxsIiwgInNwbGwiLCAiYnBsbF9kdW1teSIgfTsKPiArUE5BTUUo Z3BsbF9jcGxsX2xwbGxfYnBsbF9wKQkJPSB7ICJncGxsIiwgImNwbGwiLCAibHBsbF9kdW1teSIs ICJicGxsX2R1bW15IiB9Owo+ICtQTkFNRShncGxsX3NwbGxfY3BsbF9icGxsX2xwbGxfcCkJPSB7 ICJncGxsIiwgInNwbGwiLCAgImNwbGwiLCAiYnBsbF9kdW1teSIsICJscGxsX2R1bW15IiB9Owo+ ICtQTkFNRShncGxsX2NwbGxfdnBsbF9hdXBsbF8yNG1fcCkJPSB7ICJncGxsIiwgImNwbGwiLCAi dnBsbCIsICJhdXBsbCIsICJ4aW4yNG0iIH07Cj4gK1BOQU1FKGdwbGxfY3BsbF9zcGxsX2F1cGxs X2JwbGxfcCkJPSB7ICJncGxsIiwgImNwbGwiLCAic3BsbCIsICJhdXBsbCIsICJicGxsX2R1bW15 IiB9Owo+ICtQTkFNRShncGxsX2NwbGxfc3BsbF9icGxsX2xwbGxfcCkJPSB7ICJncGxsIiwgImNw bGwiLCAic3BsbCIsICJicGxsX2R1bW15IiwgImxwbGxfZHVtbXkiIH07Cj4gK1BOQU1FKGdwbGxf Y3BsbF9zcGxsX2xwbGxfYnBsbF9wKQk9IHsgImdwbGwiLCAiY3BsbCIsICJzcGxsIiwgImxwbGxf ZHVtbXkiLCAiYnBsbF9kdW1teSIgfTsKPiArUE5BTUUoZ3BsbF9jcGxsX3ZwbGxfYnBsbF9scGxs X3ApCT0geyAiZ3BsbCIsICJjcGxsIiwgInZwbGwiLCAiYnBsbF9kdW1teSIsICJscGxsX2R1bW15 IiB9Owo+ICtQTkFNRShncGxsX3NwbGxfYXVwbGxfYnBsbF9scGxsX3ApCT0geyAiZ3BsbCIsICJz cGxsIiwgImF1cGxsIiwgImJwbGxfZHVtbXkiLCAibHBsbF9kdW1teSIgfTsKPiArUE5BTUUoZ3Bs bF9zcGxsX2lzcHB2dHBsbF9icGxsX2xwbGxfcCkJPSB7ICJncGxsIiwgInNwbGwiLCAiaXNwX3B2 dHBsbCIsICJicGxsX2R1bW15IiwgImxwbGxfZHVtbXkiIH07Cj4gK1BOQU1FKGdwbGxfY3BsbF9z cGxsX2F1cGxsX2xwbGxfMjRtX3ApCT0geyAiZ3BsbCIsICJjcGxsIiwgInNwbGwiLCAiYXVwbGwi LCAibHBsbF9kdW1teSIsICJ4aW4yNG0iIH07Cj4gK1BOQU1FKGdwbGxfY3BsbF9zcGxsX3ZwbGxf YnBsbF9scGxsX3ApCT0geyAiZ3BsbCIsICJjcGxsIiwgInNwbGwiLCAidnBsbCIsICJicGxsX2R1 bW15IiwgImxwbGxfZHVtbXkiIH07Cj4gK1BOQU1FKGNwbGxfdnBsbF9scGxsX2JwbGxfcCkJCT0g eyAiY3BsbCIsICJ2cGxsIiwgImxwbGxfZHVtbXkiLCAiYnBsbF9kdW1teSIgfTsKPiArUE5BTUUo bXV4XzI0bV9jY2lwdnRwbGxfZ3BsbF9scGxsX3ApCT0geyAieGluMjRtIiwgImNjaV9wdnRwbGwi LCAiZ3BsbCIsICJscGxsIiB9Owo+ICtQTkFNRShtdXhfMjRtX3NwbGxfZ3BsbF9jcGxsX3ApCQk9 IHsieGluMjRtIiwgInNwbGwiLCAiZ3BsbCIsICJjcGxsIiB9Owo+ICtQTkFNRShhdWRpb19mcmFj X2ludF9wKQkJCT0geyAieGluMjRtIiwgImNsa19hdWRpb19mcmFjXzAiLCAiY2xrX2F1ZGlvX2Zy YWNfMSIsICJjbGtfYXVkaW9fZnJhY18yIiwKPiArCQkJCQkgICAgImNsa19hdWRpb19mcmFjXzMi LCAiY2xrX2F1ZGlvX2ludF8wIiwgImNsa19hdWRpb19pbnRfMSIsICJjbGtfYXVkaW9faW50XzIi IH07Cj4gK1BOQU1FKGF1ZGlvX2ZyYWNfcCkJCQk9IHsgImNsa19hdWRpb19mcmFjXzAiLCAiY2xr X2F1ZGlvX2ZyYWNfMSIsICJjbGtfYXVkaW9fZnJhY18yIiwgImNsa19hdWRpb19mcmFjXzMiIH07 Cj4gK1BOQU1FKG11eF8xMDBtXzI0bV9wKQkJCT0geyAiY2xrX2NwbGxfZGl2MTAiLCAieGluMjRt IiB9Owo+ICtQTkFNRShtdXhfMTAwbV81MG1fMjRtX3ApCQk9IHsgImNsa19jcGxsX2RpdjEwIiwg ImNsa19jcGxsX2RpdjIwIiwgInhpbjI0bSIgfTsKPiArUE5BTUUobXV4XzEwMG1fMjRtX2xjbGsw X3ApCQk9IHsgImNsa19jcGxsX2RpdjEwIiwgInhpbjI0bSIsICJsY2xrX2FzcmNfc3JjXzAiIH07 Cj4gK1BOQU1FKG11eF8xMDBtXzI0bV9sY2xrMV9wKQkJPSB7ICJjbGtfY3BsbF9kaXYxMCIsICJ4 aW4yNG0iLCAibGNsa19hc3JjX3NyY18xIiB9Owo+ICtQTkFNRShtdXhfMTUwbV8xMDBtXzUwbV8y NG1fcCkJCT0geyAiY2xrX2dwbGxfZGl2OCIsICJjbGtfY3BsbF9kaXYxMCIsICJjbGtfY3BsbF9k aXYyMCIsICJ4aW4yNG0iIH07Cj4gK1BOQU1FKG11eF8yMDBtXzEwMG1fNTBtXzI0bV9wKQkJPSB7 ICJjbGtfZ3BsbF9kaXY2IiwgImNsa19jcGxsX2RpdjEwIiwgImNsa19jcGxsX2RpdjIwIiwgInhp bjI0bSIgfTsKPiArUE5BTUUobXV4XzQwMG1fMjAwbV8xMDBtXzI0bV9wKQkJPSB7ICJjbGtfZ3Bs bF9kaXYzIiwgImNsa19ncGxsX2RpdjYiLCAiY2xrX2NwbGxfZGl2MTAiLCAieGluMjRtIiB9Owo+ ICtQTkFNRShtdXhfNTAwbV8yNTBtXzEwMG1fMjRtX3ApCQk9IHsgImNsa19jcGxsX2RpdjIiLCAi Y2xrX2NwbGxfZGl2NCIsICJjbGtfY3BsbF9kaXYxMCIsICJ4aW4yNG0iIH07Cj4gK1BOQU1FKG11 eF82MDBtXzQwMG1fMzAwbV8yNG1fcCkJCT0geyAiY2xrX2dwbGxfZGl2MiIsICJjbGtfZ3BsbF9k aXYzIiwgImNsa19ncGxsX2RpdjQiLCAieGluMjRtIiB9Owo+ICtQTkFNRShtdXhfMzUwbV8xNzVt XzExNm1fMjRtX3ApCQk9IHsgImNsa19zcGxsX2RpdjIiLCAiY2xrX3NwbGxfZGl2NCIsICJjbGtf c3BsbF9kaXY2IiwgInhpbjI0bSIgfTsKPiArUE5BTUUobXV4XzE3NW1fMTE2bV81OG1fMjRtX3Ap CQk9IHsgImNsa19zcGxsX2RpdjQiLCAiY2xrX3NwbGxfZGl2NiIsICJjbGtfc3BsbF9kaXYxMiIs ICJ4aW4yNG0iIH07Cj4gK1BOQU1FKG11eF8xMTZtXzU4bV8yNG1fcCkJCT0geyAiY2xrX3NwbGxf ZGl2NiIsICJjbGtfc3BsbF9kaXYxMiIsICJ4aW4yNG0iIH07Cj4gK1BOQU1FKG1jbGtfc2FpMF84 Y2hfcCkJCQk9IHsgIm1jbGtfc2FpMF84Y2hfc3JjIiwgInNhaTBfbWNsa2luIiwgInNhaTFfbWNs a2luIiB9Owo+ICtQTkFNRShtY2xrX3NhaTFfOGNoX3ApCQkJPSB7ICJtY2xrX3NhaTFfOGNoX3Ny YyIsICJzYWkxX21jbGtpbiIgfTsKPiArUE5BTUUobWNsa19zYWkyXzJjaF9wKQkJCT0geyAibWNs a19zYWkyXzJjaF9zcmMiLCAic2FpMl9tY2xraW4iLCAic2FpMV9tY2xraW4iIH07Cj4gK1BOQU1F KG1jbGtfc2FpM18yY2hfcCkJCQk9IHsgIm1jbGtfc2FpM18yY2hfc3JjIiwgInNhaTNfbWNsa2lu IiwgInNhaTFfbWNsa2luIiB9Owo+ICtQTkFNRShtY2xrX3NhaTRfMmNoX3ApCQkJPSB7ICJtY2xr X3NhaTRfMmNoX3NyYyIsICJzYWk0X21jbGtpbiIsICJzYWkxX21jbGtpbiIgfTsKPiArUE5BTUUo bWNsa19zYWk1XzhjaF9wKQkJCT0geyAibWNsa19zYWk1XzhjaF9zcmMiLCAic2FpMV9tY2xraW4i IH07Cj4gK1BOQU1FKG1jbGtfc2FpNl84Y2hfcCkJCQk9IHsgIm1jbGtfc2FpNl84Y2hfc3JjIiwg InNhaTFfbWNsa2luIiB9Owo+ICtQTkFNRShtY2xrX3NhaTdfOGNoX3ApCQkJPSB7ICJtY2xrX3Nh aTdfOGNoX3NyYyIsICJzYWkxX21jbGtpbiIgfTsKPiArUE5BTUUobWNsa19zYWk4XzhjaF9wKQkJ CT0geyAibWNsa19zYWk4XzhjaF9zcmMiLCAic2FpMV9tY2xraW4iIH07Cj4gK1BOQU1FKG1jbGtf c2FpOV84Y2hfcCkJCQk9IHsgIm1jbGtfc2FpOV84Y2hfc3JjIiwgInNhaTFfbWNsa2luIiB9Owo+ ICtQTkFNRSh1YXJ0MV9wKQkJCQk9IHsgImNsa191YXJ0MV9zcmNfdG9wIiwgInhpbjI0bSIgfTsK PiArUE5BTUUocGRtMF9wKQkJCQk9IHsgImNsa19wZG0wX3NyY190b3AiLCAieGluMjRtIiB9Owo+ ICtQTkFNRShtY2xrX3BkbTBfcCkJCQk9IHsgIm1jbGtfcGRtMF9zcmNfdG9wIiwgInhpbjI0bSIg fTsKPiArUE5BTUUoY2xrX2dtYWMxX3B0cF9yZWZfc3JjX3ApCQk9IHsgImdwbGwiLCAiY3BsbCIs ICJnbWFjMV9wdHBfcmVmY2xrX2luIiB9Owo+ICtQTkFNRShjbGtfZ21hYzBfcHRwX3JlZl9zcmNf cCkJCT0geyAiZ3BsbCIsICJjcGxsIiwgImdtYWMwX3B0cF9yZWZjbGtfaW4iIH07Cj4gK1BOQU1F KGRjbGtfZWJjX3ApCQkJPSB7ICJncGxsIiwgImNwbGwiLCAidnBsbCIsICJhdXBsbCIsICJscGxs X2R1bW15IiwKPiArCQkJCQkgICAgImRjbGtfZWJjX2ZyYWMiLCAieGluMjRtIiB9Owo+ICtQTkFN RShkY2xrX3ZwMF9wKQkJCT0geyAiZGNsa192cDBfc3JjIiwgImNsa19oZG1pcGh5X3BpeGVsMCIg fTsKPiArUE5BTUUoZGNsa192cDFfcCkJCQk9IHsgImRjbGtfdnAxX3NyYyIsICJjbGtfaGRtaXBo eV9waXhlbDAiIH07Cj4gK1BOQU1FKGRjbGtfdnAyX3ApCQkJPSB7ICJkY2xrX3ZwMl9zcmMiLCAi Y2xrX2hkbWlwaHlfcGl4ZWwwIiB9Owo+ICtQTkFNRShjbGtfdWFydF9wKQkJCT0geyAiZ3BsbCIs ICJjcGxsIiwgImF1cGxsIiwgInhpbjI0bSIsICJjbGtfdWFydF9mcmFjXzAiLAo+ICsJCQkJCSAg ICAiY2xrX3VhcnRfZnJhY18xIiwgImNsa191YXJ0X2ZyYWNfMiJ9Owo+ICtQTkFNRShjbGtfZnJl cV9wd20xX3ApCQkJPSB7ICJzYWkwX21jbGtpbiIsICJzYWkxX21jbGtpbiIsICJzYWkyX21jbGtp biIsCj4gKwkJCQkJICAgICJzYWkzX21jbGtpbiIsICJzYWk0X21jbGtpbiIsICJzYWlfc2Nsa2lu X2ZyZXEifTsKPiArUE5BTUUoY2xrX2NvdW50ZXJfcHdtMV9wKQkJPSB7ICJzYWkwX21jbGtpbiIs ICJzYWkxX21jbGtpbiIsICJzYWkyX21jbGtpbiIsCj4gKwkJCQkJICAgICJzYWkzX21jbGtpbiIs ICJzYWk0X21jbGtpbiIsICJzYWlfc2Nsa2luX2NvdW50ZXIifTsKPiArUE5BTUUoc2FpX3NjbGtp bl9mcmVxX3ApCQk9IHsgInNhaTBfc2Nsa19pbiIsICJzYWkxX3NjbGtfaW4iLCAic2FpMl9zY2xr X2luIiwKPiArCQkJCQkgICAgInNhaTNfc2Nsa19pbiIsICJzYWk0X3NjbGtfaW4ifTsKPiArUE5B TUUoY2xrX3JlZl9wY2llMF9waHlfcCkJCT0geyAiY2xrX3BjaWVfMTAwbV9zcmMiLCAiY2xrX3Bj aWVfMTAwbV9uZHV0eV9zcmMiLAo+ICsJCQkJCSAgICAieGluMjRtIn07Cj4gK1BOQU1FKGhjbGtf dmlfcm9vdF9wKQkJCT0geyAiY2xrX2dwbGxfZGl2NiIsICJjbGtfY3BsbF9kaXYxMCIsCj4gKwkJ CQkJICAgICJhY2xrX3ZpX3Jvb3RfaW50ZXIiLCAieGluMjRtIn07Cj4gK1BOQU1FKGNsa19yZWZf b3NjX21waHlfcCkJCT0geyAieGluMjRtIiwgImNsa19ncGlvX21waHlfaSIsICJjbGtfcmVmX21w aHlfMjZtIn07Cj4gK1BOQU1FKG11eF9wbXUyMDBtX3BtdTEwMG1fcG11NTBtXzI0bV9wKQk9IHsg ImNsa18yMDBtX3BtdV9zcmMiLCAiY2xrXzEwMG1fcG11X3NyYyIsCj4gKwkJCQkJICAgICJjbGtf NTBtX3BtdV9zcmMiLCAieGluMjRtIiB9Owo+ICtQTkFNRShtdXhfcG11MTAwbV9wbXU1MG1fMjRt X3ApCQk9IHsgImNsa18xMDBtX3BtdV9zcmMiLCAiY2xrXzUwbV9wbXVfc3JjIiwgInhpbjI0bSIg fTsKPiArUE5BTUUobXV4X3BtdTEwMG1fMjRtXzMya19wKQkJPSB7ICJjbGtfMTAwbV9wbXVfc3Jj IiwgInhpbjI0bSIsICJ4aW5fb3NjMF9kaXYiIH07Cj4gK1BOQU1FKGNsa19waHlfcmVmX3NyY19w KQkJPSB7ICJ4aW4yNG0iLCAiY2xrX3BtdXBoeV9yZWZfc3JjIiB9Owo+ICtQTkFNRShjbGtfdXNi cGh5X3JlZl9zcmNfcCkJCT0geyAidXNicGh5MF8yNG0iLCAidXNicGh5MV8yNG0iIH07Cj4gK1BO QU1FKGNsa19jcGxsX3JlZl9zcmNfcCkJCT0geyAieGluMjRtIiwgImNsa191c2JwaHlfcmVmX3Ny YyIgfTsKPiArUE5BTUUoY2xrX2F1cGxsX3JlZl9zcmNfcCkJCT0geyAieGluMjRtIiwgImNsa19h dXBsbF9yZWZfaW8iIH07Cj4gKwo+ICtzdGF0aWMgc3RydWN0IHJvY2tjaGlwX3BsbF9jbG9jayBy azM1NzZfcGxsX2Nsa3NbXSBfX2luaXRkYXRhID0gewo+ICsJW2JwbGxdID0gUExMKHBsbF9yazM1 ODhfY29yZSwgUExMX0JQTEwsICJicGxsIiwgbXV4X3BsbF9wLAo+ICsJCSAgICAgMCwgUkszNTc2 X1BMTF9DT04oMCksCj4gKwkJICAgICBSSzM1NzZfQlBMTF9NT0RFX0NPTjAsIDAsIDE1LCAwLCBy azM1NzZfcGxsX3JhdGVzKSwKPiArCVtscGxsXSA9IFBMTChwbGxfcmszNTg4X2NvcmUsIFBMTF9M UExMLCAibHBsbCIsIG11eF9wbGxfcCwKPiArCQkgICAgIDAsIFJLMzU3Nl9MUExMX0NPTigxNiks Cj4gKwkJICAgICBSSzM1NzZfTFBMTF9NT0RFX0NPTjAsIDAsIDE1LCAwLCByazM1NzZfcGxsX3Jh dGVzKSwKPiArCVt2cGxsXSA9IFBMTChwbGxfcmszNTg4LCBQTExfVlBMTCwgInZwbGwiLCBtdXhf cGxsX3AsCj4gKwkJICAgICAwLCBSSzM1NzZfUExMX0NPTig4OCksCj4gKwkJICAgICBSSzM1NzZf TU9ERV9DT04wLCA0LCAxNSwgMCwgcmszNTc2X3BsbF9yYXRlcyksCj4gKwlbYXVwbGxdID0gUExM KHBsbF9yazM1ODgsIFBMTF9BVVBMTCwgImF1cGxsIiwgbXV4X3BsbF9wLAo+ICsJCSAgICAgMCwg UkszNTc2X1BMTF9DT04oOTYpLAo+ICsJCSAgICAgUkszNTc2X01PREVfQ09OMCwgNiwgMTUsIDAs IHJrMzU3Nl9wbGxfcmF0ZXMpLAo+ICsJW2NwbGxdID0gUExMKHBsbF9yazM1ODgsIFBMTF9DUExM LCAiY3BsbCIsIG11eF9wbGxfcCwKPiArCQkgICAgIENMS19JR05PUkVfVU5VU0VELCBSSzM1NzZf UExMX0NPTigxMDQpLAo+ICsJCSAgICAgUkszNTc2X01PREVfQ09OMCwgOCwgMTUsIDAsIHJrMzU3 Nl9wbGxfcmF0ZXMpLAo+ICsJW2dwbGxdID0gUExMKHBsbF9yazM1ODgsIFBMTF9HUExMLCAiZ3Bs bCIsIG11eF9wbGxfcCwKPiArCQkgICAgIENMS19JR05PUkVfVU5VU0VELCBSSzM1NzZfUExMX0NP TigxMTIpLAo+ICsJCSAgICAgUkszNTc2X01PREVfQ09OMCwgMiwgMTUsIDAsIHJrMzU3Nl9wbGxf cmF0ZXMpLAo+ICsJW3BwbGxdID0gUExMKHBsbF9yazM1ODhfY29yZSwgUExMX1BQTEwsICJwcGxs IiwgbXV4X3BsbF9wLAo+ICsJCSAgICAgQ0xLX0lHTk9SRV9VTlVTRUQsIFJLMzU3Nl9QTVVfUExM X0NPTigxMjgpLAo+ICsJCSAgICAgUkszNTc2X01PREVfQ09OMCwgMTAsIDE1LCAwLCByazM1NzZf cHBsbF9yYXRlcyksCj4gK307Cj4gKwo+ICtzdGF0aWMgc3RydWN0IHJvY2tjaGlwX2Nsa19icmFu Y2ggcmszNTc2X2Nsa19icmFuY2hlc1tdIF9faW5pdGRhdGEgPSB7Cj4gKwkvKgo+ICsJICogQ1JV IENsb2NrLUFyY2hpdGVjdHVyZQo+ICsJICovCj4gKwkvKiBmaXhlZCAqLwo+ICsJRkFDVE9SKDAs ICJ4aW4xMm0iLCAieGluMjRtIiwgMCwgMSwgMiksCj4gKwo+ICsJQ09NUE9TSVRFX0ZSQUMoWElO X09TQzBfRElWLCAieGluX29zYzBfZGl2IiwgInhpbjI0bSIsIENMS19JU19DUklUSUNBTCwKPiAr CQkJUkszNTc2X1BNVV9DTEtTRUxfQ09OKDIxKSwgMCwKPiArCQkJUkszNTc2X1BNVV9DTEtHQVRF X0NPTig3KSwgMTEsIEdGTEFHUyksCj4gKwo+ICsJRkFDVE9SKDAsICJjbGtfc3BsbF9kaXYxMiIs ICJzcGxsIiwgMCwgMSwgMTIpLAo+ICsJRkFDVE9SKDAsICJjbGtfc3BsbF9kaXY2IiwgInNwbGwi LCAwLCAxLCA2KSwKPiArCUZBQ1RPUigwLCAiY2xrX3NwbGxfZGl2NCIsICJzcGxsIiwgMCwgMSwg NCksCj4gKwlGQUNUT1IoMCwgImxwbGxfZGl2MiIsICJscGxsIiwgMCwgMSwgMiksCj4gKwlGQUNU T1IoMCwgImJwbGxfZGl2NCIsICJicGxsIiwgMCwgMSwgNCksCj4gKwo+ICsJLyogdG9wICovCj4g KwlDT01QT1NJVEUoQ0xLX0NQTExfRElWMjAsICJjbGtfY3BsbF9kaXYyMCIsIGdwbGxfY3BsbF9w LCBDTEtfSVNfQ1JJVElDQUwsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDApLCA1LCAxLCBNRkxB R1MsIDAsIDUsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDApLCAwLCBHRkxBR1Mp LAo+ICsJQ09NUE9TSVRFKENMS19DUExMX0RJVjEwLCAiY2xrX2NwbGxfZGl2MTAiLCBncGxsX2Nw bGxfcCwgQ0xLX0lTX0NSSVRJQ0FMLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigwKSwgMTEsIDEs IE1GTEFHUywgNiwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMCksIDEsIEdG TEFHUyksCj4gKwlDT01QT1NJVEUoQ0xLX0dQTExfRElWOCwgImNsa19ncGxsX2RpdjgiLCBncGxs X2NwbGxfcCwgQ0xLX0lTX0NSSVRJQ0FMLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxKSwgNSwg MSwgTUZMQUdTLCAwLCA1LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigwKSwgMiwg R0ZMQUdTKSwKPiArCUNPTVBPU0lURShDTEtfR1BMTF9ESVY2LCAiY2xrX2dwbGxfZGl2NiIsIGdw bGxfY3BsbF9wLCBDTEtfSVNfQ1JJVElDQUwsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDEpLCAx MSwgMSwgTUZMQUdTLCA2LCA1LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigwKSwg MywgR0ZMQUdTKSwKPiArCUNPTVBPU0lURShDTEtfQ1BMTF9ESVY0LCAiY2xrX2NwbGxfZGl2NCIs IGdwbGxfY3BsbF9wLCBDTEtfSVNfQ1JJVElDQUwsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDIp LCA1LCAxLCBNRkxBR1MsIDAsIDUsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDAp LCA0LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKENMS19HUExMX0RJVjQsICJjbGtfZ3BsbF9kaXY0 IiwgZ3BsbF9jcGxsX3AsIENMS19JU19DUklUSUNBTCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04o MiksIDExLCAxLCBNRkxBR1MsIDYsIDUsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09O KDApLCA1LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKENMS19TUExMX0RJVjIsICJjbGtfc3BsbF9k aXYyIiwgZ3BsbF9jcGxsX3NwbGxfYnBsbF9wLCBDTEtfSVNfQ1JJVElDQUwsCj4gKwkJCVJLMzU3 Nl9DTEtTRUxfQ09OKDMpLCA1LCAyLCBNRkxBR1MsIDAsIDUsIERGTEFHUywKPiArCQkJUkszNTc2 X0NMS0dBVEVfQ09OKDApLCA2LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKENMS19HUExMX0RJVjMs ICJjbGtfZ3BsbF9kaXYzIiwgZ3BsbF9jcGxsX3AsIENMS19JU19DUklUSUNBTCwKPiArCQkJUksz NTc2X0NMS1NFTF9DT04oMyksIDEyLCAxLCBNRkxBR1MsIDcsIDUsIERGTEFHUywKPiArCQkJUksz NTc2X0NMS0dBVEVfQ09OKDApLCA3LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKENMS19DUExMX0RJ VjIsICJjbGtfY3BsbF9kaXYyIiwgZ3BsbF9jcGxsX3AsIENMS19JU19DUklUSUNBTCwKPiArCQkJ UkszNTc2X0NMS1NFTF9DT04oNCksIDExLCAxLCBNRkxBR1MsIDYsIDUsIERGTEFHUywKPiArCQkJ UkszNTc2X0NMS0dBVEVfQ09OKDApLCA5LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKENMS19HUExM X0RJVjIsICJjbGtfZ3BsbF9kaXYyIiwgZ3BsbF9jcGxsX3AsIENMS19JU19DUklUSUNBTCwKPiAr CQkJUkszNTc2X0NMS1NFTF9DT04oNSksIDUsIDEsIE1GTEFHUywgMCwgNSwgREZMQUdTLAo+ICsJ CQlSSzM1NzZfQ0xLR0FURV9DT04oMCksIDEwLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKENMS19T UExMX0RJVjEsICJjbGtfc3BsbF9kaXYxIiwgZ3BsbF9jcGxsX3NwbGxfYnBsbF9scGxsX3AsIENM S19JU19DUklUSUNBTCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oNiksIDUsIDMsIE1GTEFHUywg MCwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMCksIDEyLCBHRkxBR1MpLAo+ ICsJQ09NUE9TSVRFX05PRElWKFBDTEtfVE9QX1JPT1QsICJwY2xrX3RvcF9yb290IiwgbXV4XzEw MG1fNTBtXzI0bV9wLCBDTEtfSVNfQ1JJVElDQUwsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDgp LCA3LCAyLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxKSwgMSwgR0ZMQUdTKSwK PiArCUNPTVBPU0lURShBQ0xLX1RPUCwgImFjbGtfdG9wIiwgZ3BsbF9jcGxsX2F1cGxsX3AsIENM S19JU19DUklUSUNBTCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oOSksIDUsIDIsIE1GTEFHUywg MCwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMSksIDMsIEdGTEFHUyksCj4g KwlDT01QT1NJVEUoQUNMS19UT1BfTUlELCAiYWNsa190b3BfbWlkIiwgZ3BsbF9jcGxsX3AsIENM S19JU19DUklUSUNBTCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oMTApLCA1LCAxLCBNRkxBR1Ms IDAsIDUsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDEpLCA2LCBHRkxBR1MpLAo+ ICsJQ09NUE9TSVRFKEFDTEtfU0VDVVJFX0hJR0gsICJhY2xrX3NlY3VyZV9oaWdoIiwgZ3BsbF9z cGxsX2F1cGxsX2JwbGxfbHBsbF9wLCBDTEtfSVNfQ1JJVElDQUwsCj4gKwkJCVJLMzU3Nl9DTEtT RUxfQ09OKDEwKSwgMTEsIDMsIE1GTEFHUywgNiwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xL R0FURV9DT04oMSksIDcsIEdGTEFHUyksCj4gKwlDT01QT1NJVEVfTk9ESVYoSENMS19UT1AsICJo Y2xrX3RvcCIsIG11eF8yMDBtXzEwMG1fNTBtXzI0bV9wLCBDTEtfSVNfQ1JJVElDQUwsCj4gKwkJ CVJLMzU3Nl9DTEtTRUxfQ09OKDE5KSwgMiwgMiwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FU RV9DT04oMSksIDE0LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFX05PRElWKEhDTEtfVk8wVk9QX0NI QU5ORUwsICJoY2xrX3ZvMHZvcF9jaGFubmVsIiwgbXV4XzIwMG1fMTAwbV81MG1fMjRtX3AsIENM S19JU19DUklUSUNBTCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oMTkpLCA2LCAyLCBNRkxBR1Ms Cj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigyKSwgMCwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURShB Q0xLX1ZPMFZPUF9DSEFOTkVMLCAiYWNsa192bzB2b3BfY2hhbm5lbCIsIGdwbGxfY3BsbF9scGxs X2JwbGxfcCwgQ0xLX0lTX0NSSVRJQ0FMLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxOSksIDEy LCAyLCBNRkxBR1MsIDgsIDQsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDIpLCAx LCBHRkxBR1MpLAo+ICsJTVVYKENMS19BVURJT19GUkFDXzBfU1JDLCAiY2xrX2F1ZGlvX2ZyYWNf MF9zcmMiLCBncGxsX2NwbGxfYXVwbGxfMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09O KDEzKSwgMCwgMiwgTUZMQUdTKSwKPiArCUNPTVBPU0lURV9GUkFDKENMS19BVURJT19GUkFDXzAs ICJjbGtfYXVkaW9fZnJhY18wIiwgImNsa19hdWRpb19mcmFjXzBfc3JjIiwgMCwKPiArCQkJUksz NTc2X0NMS1NFTF9DT04oMTIpLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMSksIDEwLCBH RkxBR1MpLAo+ICsJTVVYKENMS19BVURJT19GUkFDXzFfU1JDLCAiY2xrX2F1ZGlvX2ZyYWNfMV9z cmMiLCBncGxsX2NwbGxfYXVwbGxfMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDE1 KSwgMCwgMiwgTUZMQUdTKSwKPiArCUNPTVBPU0lURV9GUkFDKENMS19BVURJT19GUkFDXzEsICJj bGtfYXVkaW9fZnJhY18xIiwgImNsa19hdWRpb19mcmFjXzFfc3JjIiwgMCwKPiArCQkJUkszNTc2 X0NMS1NFTF9DT04oMTQpLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMSksIDExLCBHRkxB R1MpLAo+ICsJTVVYKENMS19BVURJT19GUkFDXzJfU1JDLCAiY2xrX2F1ZGlvX2ZyYWNfMl9zcmMi LCBncGxsX2NwbGxfYXVwbGxfMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDE3KSwg MCwgMiwgTUZMQUdTKSwKPiArCUNPTVBPU0lURV9GUkFDKENMS19BVURJT19GUkFDXzIsICJjbGtf YXVkaW9fZnJhY18yIiwgImNsa19hdWRpb19mcmFjXzJfc3JjIiwgMCwKPiArCQkJUkszNTc2X0NM S1NFTF9DT04oMTYpLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMSksIDEyLCBHRkxBR1Mp LAo+ICsJTVVYKENMS19BVURJT19GUkFDXzNfU1JDLCAiY2xrX2F1ZGlvX2ZyYWNfM19zcmMiLCBn cGxsX2NwbGxfYXVwbGxfMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDE5KSwgMCwg MiwgTUZMQUdTKSwKPiArCUNPTVBPU0lURV9GUkFDKENMS19BVURJT19GUkFDXzMsICJjbGtfYXVk aW9fZnJhY18zIiwgImNsa19hdWRpb19mcmFjXzNfc3JjIiwgMCwKPiArCQkJUkszNTc2X0NMS1NF TF9DT04oMTgpLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMSksIDEzLCBHRkxBR1MpLAo+ ICsJTVVYKDAsICJjbGtfdWFydF9mcmFjXzBfc3JjIiwgZ3BsbF9jcGxsX2F1cGxsXzI0bV9wLCAw LAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigyMiksIDAsIDIsIE1GTEFHUyksCj4gKwlDT01QT1NJ VEVfRlJBQyhDTEtfVUFSVF9GUkFDXzAsICJjbGtfdWFydF9mcmFjXzAiLCAiY2xrX3VhcnRfZnJh Y18wX3NyYyIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDIxKSwgMCwKPiArCQkJUkszNTc2 X0NMS0dBVEVfQ09OKDIpLCA1LCBHRkxBR1MpLAo+ICsJTVVYKDAsICJjbGtfdWFydF9mcmFjXzFf c3JjIiwgZ3BsbF9jcGxsX2F1cGxsXzI0bV9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigy NCksIDAsIDIsIE1GTEFHUyksCj4gKwlDT01QT1NJVEVfRlJBQyhDTEtfVUFSVF9GUkFDXzEsICJj bGtfdWFydF9mcmFjXzEiLCAiY2xrX3VhcnRfZnJhY18xX3NyYyIsIDAsCj4gKwkJCVJLMzU3Nl9D TEtTRUxfQ09OKDIzKSwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDIpLCA2LCBHRkxBR1Mp LAo+ICsJTVVYKDAsICJjbGtfdWFydF9mcmFjXzJfc3JjIiwgZ3BsbF9jcGxsX2F1cGxsXzI0bV9w LCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigyNiksIDAsIDIsIE1GTEFHUyksCj4gKwlDT01Q T1NJVEVfRlJBQyhDTEtfVUFSVF9GUkFDXzIsICJjbGtfdWFydF9mcmFjXzIiLCAiY2xrX3VhcnRf ZnJhY18yX3NyYyIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDI1KSwgMCwKPiArCQkJUksz NTc2X0NMS0dBVEVfQ09OKDIpLCA3LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKENMS19VQVJUMV9T UkNfVE9QLCAiY2xrX3VhcnQxX3NyY190b3AiLCBjbGtfdWFydF9wLCAwLAo+ICsJCQlSSzM1NzZf Q0xLU0VMX0NPTigyNyksIDEzLCAzLCBNRkxBR1MsIDUsIDgsIERGTEFHUywKPiArCQkJUkszNTc2 X0NMS0dBVEVfQ09OKDIpLCAxMywgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT01VWChDTEtfQVVE SU9fSU5UXzAsICJjbGtfYXVkaW9faW50XzAiLCAiZ3BsbCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtT RUxfQ09OKDI4KSwgMCwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMiksIDE0 LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFX05PTVVYKENMS19BVURJT19JTlRfMSwgImNsa19hdWRp b19pbnRfMSIsICJjcGxsIiwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oMjgpLCA1LCA1LCBE RkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigyKSwgMTUsIEdGTEFHUyksCj4gKwlDT01Q T1NJVEVfTk9NVVgoQ0xLX0FVRElPX0lOVF8yLCAiY2xrX2F1ZGlvX2ludF8yIiwgImF1cGxsIiwg MCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oMjgpLCAxMCwgNSwgREZMQUdTLAo+ICsJCQlSSzM1 NzZfQ0xLR0FURV9DT04oMyksIDAsIEdGTEFHUyksCj4gKwlDT01QT1NJVEUoQ0xLX1BETTBfU1JD X1RPUCwgImNsa19wZG0wX3NyY190b3AiLCBhdWRpb19mcmFjX2ludF9wLCAwLAo+ICsJCQlSSzM1 NzZfQ0xLU0VMX0NPTigyOSksIDksIDMsIE1GTEFHUywgMCwgOSwgREZMQUdTLAo+ICsJCQlSSzM1 NzZfQ0xLR0FURV9DT04oMyksIDIsIEdGTEFHUyksCj4gKwlDT01QT1NJVEVfTk9NVVgoQ0xLX0dN QUMwXzEyNU1fU1JDLCAiY2xrX2dtYWMwXzEyNW1fc3JjIiwgImNwbGwiLCAwLAo+ICsJCQlSSzM1 NzZfQ0xLU0VMX0NPTigzMCksIDEwLCA1LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NP TigzKSwgNiwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT01VWChDTEtfR01BQzFfMTI1TV9TUkMs ICJjbGtfZ21hYzFfMTI1bV9zcmMiLCAiY3BsbCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09O KDMxKSwgMCwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMyksIDcsIEdGTEFH UyksCj4gKwlDT01QT1NJVEUoTENMS19BU1JDX1NSQ18wLCAibGNsa19hc3JjX3NyY18wIiwgYXVk aW9fZnJhY19wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigzMSksIDEwLCAyLCBNRkxBR1Ms IDUsIDUsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDMpLCAxMCwgR0ZMQUdTKSwK PiArCUNPTVBPU0lURShMQ0xLX0FTUkNfU1JDXzEsICJsY2xrX2FzcmNfc3JjXzEiLCBhdWRpb19m cmFjX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDMyKSwgNSwgMiwgTUZMQUdTLCAwLCA1 LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigzKSwgMTEsIEdGTEFHUyksCj4gKwlD T01QT1NJVEUoUkVGX0NMSzBfT1VUX1BMTCwgInJlZl9jbGswX291dF9wbGwiLCBncGxsX2NwbGxf c3BsbF9hdXBsbF9scGxsXzI0bV9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigzMyksIDgs IDMsIE1GTEFHUywgMCwgOCwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNCksIDEs IEdGTEFHUyksCj4gKwlDT01QT1NJVEUoUkVGX0NMSzFfT1VUX1BMTCwgInJlZl9jbGsxX291dF9w bGwiLCBncGxsX2NwbGxfc3BsbF9hdXBsbF9scGxsXzI0bV9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xL U0VMX0NPTigzNCksIDgsIDMsIE1GTEFHUywgMCwgOCwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xL R0FURV9DT04oNCksIDIsIEdGTEFHUyksCj4gKwlDT01QT1NJVEUoUkVGX0NMSzJfT1VUX1BMTCwg InJlZl9jbGsyX291dF9wbGwiLCBncGxsX2NwbGxfc3BsbF9hdXBsbF9scGxsXzI0bV9wLCAwLAo+ ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigzNSksIDgsIDMsIE1GTEFHUywgMCwgOCwgREZMQUdTLAo+ ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNCksIDMsIEdGTEFHUyksCj4gKwlDT01QT1NJVEUoUkVG Q0xLTzI1TV9HTUFDMF9PVVQsICJyZWZjbGtvMjVtX2dtYWMwX291dCIsIGdwbGxfY3BsbF9wLCAw LAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigzNiksIDcsIDEsIE1GTEFHUywgMCwgNywgREZMQUdT LAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNSksIDEwLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRF KFJFRkNMS08yNU1fR01BQzFfT1VULCAicmVmY2xrbzI1bV9nbWFjMV9vdXQiLCBncGxsX2NwbGxf cCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oMzYpLCAxNSwgMSwgTUZMQUdTLCA4LCA3LCBE RkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig1KSwgMTEsIEdGTEFHUyksCj4gKwlDT01Q T1NJVEUoQ0xLX0NJRk9VVF9PVVQsICJjbGtfY2lmb3V0X291dCIsIGdwbGxfY3BsbF8yNG1fc3Bs bF9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigzNyksIDgsIDIsIE1GTEFHUywgMCwgOCwg REZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNSksIDEyLCBHRkxBR1MpLAo+ICsJR0FU RShDTEtfR01BQzBfUk1JSV9DUlUsICJjbGtfZ21hYzBfcm1paV9jcnUiLCAiY2xrX2NwbGxfZGl2 MjAiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNSksIDEzLCBHRkxBR1MpLAo+ICsJR0FU RShDTEtfR01BQzFfUk1JSV9DUlUsICJjbGtfZ21hYzFfcm1paV9jcnUiLCAiY2xrX2NwbGxfZGl2 MjAiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNSksIDE0LCBHRkxBR1MpLAo+ICsJR0FU RShDTEtfT1RQQ19BVVRPX1JEX0csICJjbGtfb3RwY19hdXRvX3JkX2ciLCAieGluMjRtIiwgMCwK PiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDUpLCAxNSwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURShD TEtfTUlQSV9DQU1FUkFPVVRfTTAsICJjbGtfbWlwaV9jYW1lcmFvdXRfbTAiLCBtdXhfMjRtX3Nw bGxfZ3BsbF9jcGxsX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDM4KSwgOCwgMiwgTUZM QUdTLCAwLCA4LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig2KSwgMywgR0ZMQUdT KSwKPiArCUNPTVBPU0lURShDTEtfTUlQSV9DQU1FUkFPVVRfTTEsICJjbGtfbWlwaV9jYW1lcmFv dXRfbTEiLCBtdXhfMjRtX3NwbGxfZ3BsbF9jcGxsX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxf Q09OKDM5KSwgOCwgMiwgTUZMQUdTLCAwLCA4LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRF X0NPTig2KSwgNCwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURShDTEtfTUlQSV9DQU1FUkFPVVRfTTIs ICJjbGtfbWlwaV9jYW1lcmFvdXRfbTIiLCBtdXhfMjRtX3NwbGxfZ3BsbF9jcGxsX3AsIDAsCj4g KwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDQwKSwgOCwgMiwgTUZMQUdTLCAwLCA4LCBERkxBR1MsCj4g KwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig2KSwgNSwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURShNQ0xL X1BETTBfU1JDX1RPUCwgIm1jbGtfcGRtMF9zcmNfdG9wIiwgYXVkaW9fZnJhY19pbnRfcCwgMCwK PiArCQkJUkszNTc2X0NMS1NFTF9DT04oNDEpLCA3LCAzLCBNRkxBR1MsIDIsIDUsIERGTEFHUywK PiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDYpLCA4LCBHRkxBR1MpLAo+ICsKPiArCS8qIGJ1cyAq Lwo+ICsJQ09NUE9TSVRFX05PRElWKEhDTEtfQlVTX1JPT1QsICJoY2xrX2J1c19yb290IiwgbXV4 XzIwMG1fMTAwbV81MG1fMjRtX3AsIENMS19JU19DUklUSUNBTCwKPiArCQkJUkszNTc2X0NMS1NF TF9DT04oNTUpLCAwLCAyLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxMSksIDAs IEdGTEFHUyksCj4gKwlDT01QT1NJVEVfTk9ESVYoUENMS19CVVNfUk9PVCwgInBjbGtfYnVzX3Jv b3QiLCBtdXhfMTAwbV81MG1fMjRtX3AsIENMS19JU19DUklUSUNBTCwKPiArCQkJUkszNTc2X0NM S1NFTF9DT04oNTUpLCAyLCAyLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxMSks IDEsIEdGTEFHUyksCj4gKwlDT01QT1NJVEUoQUNMS19CVVNfUk9PVCwgImFjbGtfYnVzX3Jvb3Qi LCBncGxsX2NwbGxfcCwgQ0xLX0lTX0NSSVRJQ0FMLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTig1 NSksIDksIDEsIE1GTEFHUywgNCwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04o MTEpLCAyLCBHRkxBR1MpLAo+ICsJR0FURShIQ0xLX0NBTjAsICJoY2xrX2NhbjAiLCAiaGNsa19i dXNfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxMSksIDYsIEdGTEFHUyksCj4g KwlDT01QT1NJVEUoQ0xLX0NBTjAsICJjbGtfY2FuMCIsIGdwbGxfY3BsbF8yNG1fcCwgMCwKPiAr CQkJUkszNTc2X0NMS1NFTF9DT04oNTYpLCA1LCAyLCBNRkxBR1MsIDAsIDUsIERGTEFHUywKPiAr CQkJUkszNTc2X0NMS0dBVEVfQ09OKDExKSwgNywgR0ZMQUdTKSwKPiArCUdBVEUoSENMS19DQU4x LCAiaGNsa19jYW4xIiwgImhjbGtfYnVzX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9D T04oMTEpLCA4LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKENMS19DQU4xLCAiY2xrX2NhbjEiLCBn cGxsX2NwbGxfMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDU2KSwgMTIsIDIsIE1G TEFHUywgNywgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTEpLCA5LCBHRkxB R1MpLAo+ICsJR0FURShDTEtfS0VZX1NISUZULCAiY2xrX2tleV9zaGlmdCIsICJ4aW4yNG0iLCBD TEtfSVNfQ1JJVElDQUwsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxMSksIDE1LCBHRkxBR1Mp LAo+ICsJR0FURShQQ0xLX0kyQzEsICJwY2xrX2kyYzEiLCAicGNsa19idXNfcm9vdCIsIDAsCj4g KwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxMiksIDAsIEdGTEFHUyksCj4gKwlHQVRFKFBDTEtfSTJD MiwgInBjbGtfaTJjMiIsICJwY2xrX2J1c19yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVf Q09OKDEyKSwgMSwgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19JMkMzLCAicGNsa19pMmMzIiwgInBj bGtfYnVzX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTIpLCAyLCBHRkxBR1Mp LAo+ICsJR0FURShQQ0xLX0kyQzQsICJwY2xrX2kyYzQiLCAicGNsa19idXNfcm9vdCIsIDAsCj4g KwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxMiksIDMsIEdGTEFHUyksCj4gKwlHQVRFKFBDTEtfSTJD NSwgInBjbGtfaTJjNSIsICJwY2xrX2J1c19yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVf Q09OKDEyKSwgNCwgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19JMkM2LCAicGNsa19pMmM2IiwgInBj bGtfYnVzX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTIpLCA1LCBHRkxBR1Mp LAo+ICsJR0FURShQQ0xLX0kyQzcsICJwY2xrX2kyYzciLCAicGNsa19idXNfcm9vdCIsIDAsCj4g KwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxMiksIDYsIEdGTEFHUyksCj4gKwlHQVRFKFBDTEtfSTJD OCwgInBjbGtfaTJjOCIsICJwY2xrX2J1c19yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVf Q09OKDEyKSwgNywgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19JMkM5LCAicGNsa19pMmM5IiwgInBj bGtfYnVzX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTIpLCA4LCBHRkxBR1Mp LAo+ICsJR0FURShQQ0xLX1dEVF9CVVNNQ1UsICJwY2xrX3dkdF9idXNtY3UiLCAicGNsa19idXNf cm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxMiksIDksIEdGTEFHUyksCj4gKwlH QVRFKFRDTEtfV0RUX0JVU01DVSwgInRjbGtfd2R0X2J1c21jdSIsICJ4aW4yNG0iLCAwLAo+ICsJ CQlSSzM1NzZfQ0xLR0FURV9DT04oMTIpLCAxMCwgR0ZMQUdTKSwKPiArCUdBVEUoQUNMS19HSUMs ICJhY2xrX2dpYyIsICJhY2xrX2J1c19yb290IiwgQ0xLX0lTX0NSSVRJQ0FMLAo+ICsJCQlSSzM1 NzZfQ0xLR0FURV9DT04oMTIpLCAxMSwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihDTEtf STJDMSwgImNsa19pMmMxIiwgbXV4XzIwMG1fMTAwbV81MG1fMjRtX3AsIDAsCj4gKwkJCVJLMzU3 Nl9DTEtTRUxfQ09OKDU3KSwgMCwgMiwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04o MTIpLCAxMiwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihDTEtfSTJDMiwgImNsa19pMmMy IiwgbXV4XzIwMG1fMTAwbV81MG1fMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDU3 KSwgMiwgMiwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTIpLCAxMywgR0ZMQUdT KSwKPiArCUNPTVBPU0lURV9OT0RJVihDTEtfSTJDMywgImNsa19pMmMzIiwgbXV4XzIwMG1fMTAw bV81MG1fMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDU3KSwgNCwgMiwgTUZMQUdT LAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTIpLCAxNCwgR0ZMQUdTKSwKPiArCUNPTVBPU0lU RV9OT0RJVihDTEtfSTJDNCwgImNsa19pMmM0IiwgbXV4XzIwMG1fMTAwbV81MG1fMjRtX3AsIDAs Cj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDU3KSwgNiwgMiwgTUZMQUdTLAo+ICsJCQlSSzM1NzZf Q0xLR0FURV9DT04oMTIpLCAxNSwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihDTEtfSTJD NSwgImNsa19pMmM1IiwgbXV4XzIwMG1fMTAwbV81MG1fMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9D TEtTRUxfQ09OKDU3KSwgOCwgMiwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTMp LCAwLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFX05PRElWKENMS19JMkM2LCAiY2xrX2kyYzYiLCBt dXhfMjAwbV8xMDBtXzUwbV8yNG1fcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oNTcpLCAx MCwgMiwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTMpLCAxLCBHRkxBR1MpLAo+ ICsJQ09NUE9TSVRFX05PRElWKENMS19JMkM3LCAiY2xrX2kyYzciLCBtdXhfMjAwbV8xMDBtXzUw bV8yNG1fcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oNTcpLCAxMiwgMiwgTUZMQUdTLAo+ ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTMpLCAyLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFX05P RElWKENMS19JMkM4LCAiY2xrX2kyYzgiLCBtdXhfMjAwbV8xMDBtXzUwbV8yNG1fcCwgMCwKPiAr CQkJUkszNTc2X0NMS1NFTF9DT04oNTcpLCAxNCwgMiwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xL R0FURV9DT04oMTMpLCAzLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFX05PRElWKENMS19JMkM5LCAi Y2xrX2kyYzkiLCBtdXhfMjAwbV8xMDBtXzUwbV8yNG1fcCwgMCwKPiArCQkJUkszNTc2X0NMS1NF TF9DT04oNTgpLCAwLCAyLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxMyksIDQs IEdGTEFHUyksCj4gKwlHQVRFKFBDTEtfU0FSQURDLCAicGNsa19zYXJhZGMiLCAicGNsa19idXNf cm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxMyksIDYsIEdGTEFHUyksCj4gKwlD T01QT1NJVEUoQ0xLX1NBUkFEQywgImNsa19zYXJhZGMiLCBncGxsXzI0bV9wLCAwLAo+ICsJCQlS SzM1NzZfQ0xLU0VMX0NPTig1OCksIDEyLCAxLCBNRkxBR1MsIDQsIDgsIERGTEFHUywKPiArCQkJ UkszNTc2X0NMS0dBVEVfQ09OKDEzKSwgNywgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19UU0FEQywg InBjbGtfdHNhZGMiLCAicGNsa19idXNfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NP TigxMyksIDgsIEdGTEFHUyksCj4gKwlDT01QT1NJVEVfTk9NVVgoQ0xLX1RTQURDLCAiY2xrX3Rz YWRjIiwgInhpbjI0bSIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDU5KSwgMCwgOCwgREZM QUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTMpLCA5LCBHRkxBR1MpLAo+ICsJR0FURShQ Q0xLX1VBUlQwLCAicGNsa191YXJ0MCIsICJwY2xrX2J1c19yb290IiwgMCwKPiArCQkJUkszNTc2 X0NMS0dBVEVfQ09OKDEzKSwgMTAsIEdGTEFHUyksCj4gKwlHQVRFKFBDTEtfVUFSVDIsICJwY2xr X3VhcnQyIiwgInBjbGtfYnVzX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTMp LCAxMSwgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19VQVJUMywgInBjbGtfdWFydDMiLCAicGNsa19i dXNfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxMyksIDEyLCBHRkxBR1MpLAo+ ICsJR0FURShQQ0xLX1VBUlQ0LCAicGNsa191YXJ0NCIsICJwY2xrX2J1c19yb290IiwgMCwKPiAr CQkJUkszNTc2X0NMS0dBVEVfQ09OKDEzKSwgMTMsIEdGTEFHUyksCj4gKwlHQVRFKFBDTEtfVUFS VDUsICJwY2xrX3VhcnQ1IiwgInBjbGtfYnVzX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FU RV9DT04oMTMpLCAxNCwgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19VQVJUNiwgInBjbGtfdWFydDYi LCAicGNsa19idXNfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxMyksIDE1LCBH RkxBR1MpLAo+ICsJR0FURShQQ0xLX1VBUlQ3LCAicGNsa191YXJ0NyIsICJwY2xrX2J1c19yb290 IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDE0KSwgMCwgR0ZMQUdTKSwKPiArCUdBVEUo UENMS19VQVJUOCwgInBjbGtfdWFydDgiLCAicGNsa19idXNfcm9vdCIsIDAsCj4gKwkJCVJLMzU3 Nl9DTEtHQVRFX0NPTigxNCksIDEsIEdGTEFHUyksCj4gKwlHQVRFKFBDTEtfVUFSVDksICJwY2xr X3VhcnQ5IiwgInBjbGtfYnVzX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTQp LCAyLCBHRkxBR1MpLAo+ICsJR0FURShQQ0xLX1VBUlQxMCwgInBjbGtfdWFydDEwIiwgInBjbGtf YnVzX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTQpLCAzLCBHRkxBR1MpLAo+ ICsJR0FURShQQ0xLX1VBUlQxMSwgInBjbGtfdWFydDExIiwgInBjbGtfYnVzX3Jvb3QiLCAwLAo+ ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTQpLCA0LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKFND TEtfVUFSVDAsICJzY2xrX3VhcnQwIiwgY2xrX3VhcnRfcCwgMCwKPiArCQkJUkszNTc2X0NMS1NF TF9DT04oNjApLCA4LCAzLCBNRkxBR1MsIDAsIDgsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dB VEVfQ09OKDE0KSwgNSwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURShTQ0xLX1VBUlQyLCAic2Nsa191 YXJ0MiIsIGNsa191YXJ0X3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDYxKSwgOCwgMywg TUZMQUdTLCAwLCA4LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxNCksIDYsIEdG TEFHUyksCj4gKwlDT01QT1NJVEUoU0NMS19VQVJUMywgInNjbGtfdWFydDMiLCBjbGtfdWFydF9w LCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTig2MiksIDgsIDMsIE1GTEFHUywgMCwgOCwgREZM QUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTQpLCA5LCBHRkxBR1MpLAo+ICsJQ09NUE9T SVRFKFNDTEtfVUFSVDQsICJzY2xrX3VhcnQ0IiwgY2xrX3VhcnRfcCwgMCwKPiArCQkJUkszNTc2 X0NMS1NFTF9DT04oNjMpLCA4LCAzLCBNRkxBR1MsIDAsIDgsIERGTEFHUywKPiArCQkJUkszNTc2 X0NMS0dBVEVfQ09OKDE0KSwgMTIsIEdGTEFHUyksCj4gKwlDT01QT1NJVEUoU0NMS19VQVJUNSwg InNjbGtfdWFydDUiLCBjbGtfdWFydF9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTig2NCks IDgsIDMsIE1GTEFHUywgMCwgOCwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTQp LCAxNSwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURShTQ0xLX1VBUlQ2LCAic2Nsa191YXJ0NiIsIGNs a191YXJ0X3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDY1KSwgOCwgMywgTUZMQUdTLCAw LCA4LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxNSksIDIsIEdGTEFHUyksCj4g KwlDT01QT1NJVEUoU0NMS19VQVJUNywgInNjbGtfdWFydDciLCBjbGtfdWFydF9wLCAwLAo+ICsJ CQlSSzM1NzZfQ0xLU0VMX0NPTig2NiksIDgsIDMsIE1GTEFHUywgMCwgOCwgREZMQUdTLAo+ICsJ CQlSSzM1NzZfQ0xLR0FURV9DT04oMTUpLCA1LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKFNDTEtf VUFSVDgsICJzY2xrX3VhcnQ4IiwgY2xrX3VhcnRfcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9D T04oNjcpLCA4LCAzLCBNRkxBR1MsIDAsIDgsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVf Q09OKDE1KSwgOCwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURShTQ0xLX1VBUlQ5LCAic2Nsa191YXJ0 OSIsIGNsa191YXJ0X3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDY4KSwgOCwgMywgTUZM QUdTLCAwLCA4LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxNSksIDksIEdGTEFH UyksCj4gKwlDT01QT1NJVEUoU0NMS19VQVJUMTAsICJzY2xrX3VhcnQxMCIsIGNsa191YXJ0X3As IDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDY5KSwgOCwgMywgTUZMQUdTLCAwLCA4LCBERkxB R1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxNSksIDEwLCBHRkxBR1MpLAo+ICsJQ09NUE9T SVRFKFNDTEtfVUFSVDExLCAic2Nsa191YXJ0MTEiLCBjbGtfdWFydF9wLCAwLAo+ICsJCQlSSzM1 NzZfQ0xLU0VMX0NPTig3MCksIDgsIDMsIE1GTEFHUywgMCwgOCwgREZMQUdTLAo+ICsJCQlSSzM1 NzZfQ0xLR0FURV9DT04oMTUpLCAxMSwgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19TUEkwLCAicGNs a19zcGkwIiwgInBjbGtfYnVzX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTUp LCAxMywgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19TUEkxLCAicGNsa19zcGkxIiwgInBjbGtfYnVz X3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTUpLCAxNCwgR0ZMQUdTKSwKPiAr CUdBVEUoUENMS19TUEkyLCAicGNsa19zcGkyIiwgInBjbGtfYnVzX3Jvb3QiLCAwLAo+ICsJCQlS SzM1NzZfQ0xLR0FURV9DT04oMTUpLCAxNSwgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19TUEkzLCAi cGNsa19zcGkzIiwgInBjbGtfYnVzX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04o MTYpLCAwLCBHRkxBR1MpLAo+ICsJR0FURShQQ0xLX1NQSTQsICJwY2xrX3NwaTQiLCAicGNsa19i dXNfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxNiksIDEsIEdGTEFHUyksCj4g KwlDT01QT1NJVEVfTk9ESVYoQ0xLX1NQSTAsICJjbGtfc3BpMCIsIG11eF8yMDBtXzEwMG1fNTBt XzI0bV9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTig3MCksIDEzLCAyLCBNRkxBR1MsCj4g KwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxNiksIDIsIEdGTEFHUyksCj4gKwlDT01QT1NJVEVfTk9E SVYoQ0xLX1NQSTEsICJjbGtfc3BpMSIsIG11eF8yMDBtXzEwMG1fNTBtXzI0bV9wLCAwLAo+ICsJ CQlSSzM1NzZfQ0xLU0VMX0NPTig3MSksIDAsIDIsIE1GTEFHUywKPiArCQkJUkszNTc2X0NMS0dB VEVfQ09OKDE2KSwgMywgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihDTEtfU1BJMiwgImNs a19zcGkyIiwgbXV4XzIwMG1fMTAwbV81MG1fMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxf Q09OKDcxKSwgMiwgMiwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTYpLCA0LCBH RkxBR1MpLAo+ICsJQ09NUE9TSVRFX05PRElWKENMS19TUEkzLCAiY2xrX3NwaTMiLCBtdXhfMjAw bV8xMDBtXzUwbV8yNG1fcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oNzEpLCA0LCAyLCBN RkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxNiksIDUsIEdGTEFHUyksCj4gKwlDT01Q T1NJVEVfTk9ESVYoQ0xLX1NQSTQsICJjbGtfc3BpNCIsIG11eF8yMDBtXzEwMG1fNTBtXzI0bV9w LCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTig3MSksIDYsIDIsIE1GTEFHUywKPiArCQkJUksz NTc2X0NMS0dBVEVfQ09OKDE2KSwgNiwgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19XRFQwLCAicGNs a193ZHQwIiwgInBjbGtfYnVzX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTYp LCA3LCBHRkxBR1MpLAo+ICsJR0FURShUQ0xLX1dEVDAsICJ0Y2xrX3dkdDAiLCAieGluMjRtIiwg MCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDE2KSwgOCwgR0ZMQUdTKSwKPiArCUdBVEUoUENM S19QV00xLCAicGNsa19wd20xIiwgInBjbGtfYnVzX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xL R0FURV9DT04oMTYpLCAxMCwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihDTEtfUFdNMSwg ImNsa19wd20xIiwgbXV4XzEwMG1fNTBtXzI0bV9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NP Tig3MSksIDgsIDIsIE1GTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDE2KSwgMTEsIEdG TEFHUyksCj4gKwlHQVRFKENMS19PU0NfUFdNMSwgImNsa19vc2NfcHdtMSIsICJ4aW4yNG0iLCAw LAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTYpLCAxMywgR0ZMQUdTKSwKPiArCUdBVEUoQ0xL X1JDX1BXTTEsICJjbGtfcmNfcHdtMSIsICJjbGtfcHZ0bV9jbGtvdXQiLCAwLAo+ICsJCQlSSzM1 NzZfQ0xLR0FURV9DT04oMTYpLCAxNSwgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19CVVNUSU1FUjAs ICJwY2xrX2J1c3RpbWVyMCIsICJwY2xrX2J1c19yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dB VEVfQ09OKDE3KSwgMywgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19CVVNUSU1FUjEsICJwY2xrX2J1 c3RpbWVyMSIsICJwY2xrX2J1c19yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDE3 KSwgNCwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihDTEtfVElNRVIwX1JPT1QsICJjbGtf dGltZXIwX3Jvb3QiLCBtdXhfMTAwbV8yNG1fcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04o NzEpLCAxNCwgMSwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTcpLCA1LCBHRkxB R1MpLAo+ICsJR0FURShDTEtfVElNRVIwLCAiY2xrX3RpbWVyMCIsICJjbGtfdGltZXIwX3Jvb3Qi LCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTcpLCA2LCBHRkxBR1MpLAo+ICsJR0FURShD TEtfVElNRVIxLCAiY2xrX3RpbWVyMSIsICJjbGtfdGltZXIwX3Jvb3QiLCAwLAo+ICsJCQlSSzM1 NzZfQ0xLR0FURV9DT04oMTcpLCA3LCBHRkxBR1MpLAo+ICsJR0FURShDTEtfVElNRVIyLCAiY2xr X3RpbWVyMiIsICJjbGtfdGltZXIwX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04o MTcpLCA4LCBHRkxBR1MpLAo+ICsJR0FURShDTEtfVElNRVIzLCAiY2xrX3RpbWVyMyIsICJjbGtf dGltZXIwX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTcpLCA5LCBHRkxBR1Mp LAo+ICsJR0FURShDTEtfVElNRVI0LCAiY2xrX3RpbWVyNCIsICJjbGtfdGltZXIwX3Jvb3QiLCAw LAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTcpLCAxMCwgR0ZMQUdTKSwKPiArCUdBVEUoQ0xL X1RJTUVSNSwgImNsa190aW1lcjUiLCAiY2xrX3RpbWVyMF9yb290IiwgMCwKPiArCQkJUkszNTc2 X0NMS0dBVEVfQ09OKDE3KSwgMTEsIEdGTEFHUyksCj4gKwlHQVRFKFBDTEtfTUFJTEJPWDAsICJw Y2xrX21haWxib3gwIiwgInBjbGtfYnVzX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9D T04oMTcpLCAxMywgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19HUElPMSwgInBjbGtfZ3BpbzEiLCAi cGNsa19idXNfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxNyksIDE1LCBHRkxB R1MpLAo+ICsJR0FURShEQkNMS19HUElPMSwgImRiY2xrX2dwaW8xIiwgInhpbjI0bSIsIDAsCj4g KwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxOCksIDAsIEdGTEFHUyksCj4gKwlHQVRFKFBDTEtfR1BJ TzIsICJwY2xrX2dwaW8yIiwgInBjbGtfYnVzX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FU RV9DT04oMTgpLCAxLCBHRkxBR1MpLAo+ICsJR0FURShEQkNMS19HUElPMiwgImRiY2xrX2dwaW8y IiwgInhpbjI0bSIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxOCksIDIsIEdGTEFHUyks Cj4gKwlHQVRFKFBDTEtfR1BJTzMsICJwY2xrX2dwaW8zIiwgInBjbGtfYnVzX3Jvb3QiLCAwLAo+ ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTgpLCAzLCBHRkxBR1MpLAo+ICsJR0FURShEQkNMS19H UElPMywgImRiY2xrX2dwaW8zIiwgInhpbjI0bSIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NP TigxOCksIDQsIEdGTEFHUyksCj4gKwlHQVRFKFBDTEtfR1BJTzQsICJwY2xrX2dwaW80IiwgInBj bGtfYnVzX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTgpLCA1LCBHRkxBR1Mp LAo+ICsJR0FURShEQkNMS19HUElPNCwgImRiY2xrX2dwaW80IiwgInhpbjI0bSIsIDAsCj4gKwkJ CVJLMzU3Nl9DTEtHQVRFX0NPTigxOCksIDYsIEdGTEFHUyksCj4gKwlHQVRFKEFDTEtfREVDT00s ICJhY2xrX2RlY29tIiwgImFjbGtfYnVzX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9D T04oMTgpLCA3LCBHRkxBR1MpLAo+ICsJR0FURShQQ0xLX0RFQ09NLCAicGNsa19kZWNvbSIsICJw Y2xrX2J1c19yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDE4KSwgOCwgR0ZMQUdT KSwKPiArCUNPTVBPU0lURShEQ0xLX0RFQ09NLCAiZGNsa19kZWNvbSIsIGdwbGxfc3BsbF9wLCAw LAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTig3MiksIDUsIDEsIE1GTEFHUywgMCwgNSwgREZMQUdT LAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTgpLCA5LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRF X05PRElWKENMS19USU1FUjFfUk9PVCwgImNsa190aW1lcjFfcm9vdCIsIG11eF8xMDBtXzI0bV9w LCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTig3MiksIDYsIDEsIE1GTEFHUywKPiArCQkJUksz NTc2X0NMS0dBVEVfQ09OKDE4KSwgMTAsIEdGTEFHUyksCj4gKwlHQVRFKENMS19USU1FUjYsICJj bGtfdGltZXI2IiwgImNsa190aW1lcjFfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NP TigxOCksIDExLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKENMS19USU1FUjcsICJjbGtfdGltZXI3 IiwgbXV4XzEwMG1fMjRtX2xjbGswX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDcyKSwg MTIsIDIsIE1GTEFHUywgNywgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTgp LCAxMiwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURShDTEtfVElNRVI4LCAiY2xrX3RpbWVyOCIsIG11 eF8xMDBtXzI0bV9sY2xrMV9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTig3MyksIDUsIDIs IE1GTEFHUywgMCwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTgpLCAxMywg R0ZMQUdTKSwKPiArCUdBVEUoQ0xLX1RJTUVSOSwgImNsa190aW1lcjkiLCAiY2xrX3RpbWVyMV9y b290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDE4KSwgMTQsIEdGTEFHUyksCj4gKwlH QVRFKENMS19USU1FUjEwLCAiY2xrX3RpbWVyMTAiLCAiY2xrX3RpbWVyMV9yb290IiwgMCwKPiAr CQkJUkszNTc2X0NMS0dBVEVfQ09OKDE4KSwgMTUsIEdGTEFHUyksCj4gKwlHQVRFKENMS19USU1F UjExLCAiY2xrX3RpbWVyMTEiLCAiY2xrX3RpbWVyMV9yb290IiwgMCwKPiArCQkJUkszNTc2X0NM S0dBVEVfQ09OKDE5KSwgMCwgR0ZMQUdTKSwKPiArCUdBVEUoQUNMS19ETUFDMCwgImFjbGtfZG1h YzAiLCAiYWNsa19idXNfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxOSksIDEs IEdGTEFHUyksCj4gKwlHQVRFKEFDTEtfRE1BQzEsICJhY2xrX2RtYWMxIiwgImFjbGtfYnVzX3Jv b3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTkpLCAyLCBHRkxBR1MpLAo+ICsJR0FU RShBQ0xLX0RNQUMyLCAiYWNsa19kbWFjMiIsICJhY2xrX2J1c19yb290IiwgMCwKPiArCQkJUksz NTc2X0NMS0dBVEVfQ09OKDE5KSwgMywgR0ZMQUdTKSwKPiArCUdBVEUoQUNMS19TUElOTE9DSywg ImFjbGtfc3BpbmxvY2siLCAiYWNsa19idXNfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRF X0NPTigxOSksIDQsIEdGTEFHUyksCj4gKwlHQVRFKEhDTEtfSTNDMCwgImhjbGtfaTNjMCIsICJo Y2xrX2J1c19yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDE5KSwgNywgR0ZMQUdT KSwKPiArCUdBVEUoSENMS19JM0MxLCAiaGNsa19pM2MxIiwgImhjbGtfYnVzX3Jvb3QiLCAwLAo+ ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTkpLCA5LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFX05P RElWKEhDTEtfQlVTX0NNMF9ST09ULCAiaGNsa19idXNfY20wX3Jvb3QiLCBtdXhfNDAwbV8yMDBt XzEwMG1fMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDczKSwgMTMsIDIsIE1GTEFH UywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDE5KSwgMTAsIEdGTEFHUyksCj4gKwlHQVRFKEZD TEtfQlVTX0NNMF9DT1JFLCAiZmNsa19idXNfY20wX2NvcmUiLCAiaGNsa19idXNfY20wX3Jvb3Qi LCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTkpLCAxMiwgR0ZMQUdTKSwKPiArCUNPTVBP U0lURShDTEtfQlVTX0NNMF9SVEMsICJjbGtfYnVzX2NtMF9ydGMiLCBtdXhfMjRtXzMya19wLCAw LAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTig3NCksIDUsIDEsIE1GTEFHUywgMCwgNSwgREZMQUdT LAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMTkpLCAxNCwgR0ZMQUdTKSwKPiArCUdBVEUoUENM S19QTVUyLCAicGNsa19wbXUyIiwgInBjbGtfYnVzX3Jvb3QiLCBDTEtfSVNfQ1JJVElDQUwsCj4g KwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigxOSksIDE1LCBHRkxBR1MpLAo+ICsJR0FURShQQ0xLX1BX TTIsICJwY2xrX3B3bTIiLCAicGNsa19idXNfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRF X0NPTigyMCksIDQsIEdGTEFHUyksCj4gKwlDT01QT1NJVEVfTk9ESVYoQ0xLX1BXTTIsICJjbGtf cHdtMiIsIG11eF8xMDBtXzUwbV8yNG1fcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oNzQp LCA2LCAyLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigyMCksIDUsIEdGTEFHUyks Cj4gKwlHQVRFKENMS19PU0NfUFdNMiwgImNsa19vc2NfcHdtMiIsICJ4aW4yNG0iLCAwLAo+ICsJ CQlSSzM1NzZfQ0xLR0FURV9DT04oMjApLCA3LCBHRkxBR1MpLAo+ICsJR0FURShDTEtfUkNfUFdN MiwgImNsa19yY19wd20yIiwgImNsa19wdnRtX2Nsa291dCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtH QVRFX0NPTigyMCksIDYsIEdGTEFHUyksCj4gKwlDT01QT1NJVEVfTk9ESVYoQ0xLX0ZSRVFfUFdN MSwgImNsa19mcmVxX3B3bTEiLCBjbGtfZnJlcV9wd20xX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtT RUxfQ09OKDc0KSwgOCwgMywgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMjApLCA4 LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFX05PRElWKENMS19DT1VOVEVSX1BXTTEsICJjbGtfY291 bnRlcl9wd20xIiwgY2xrX2NvdW50ZXJfcHdtMV9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NP Tig3NCksIDExLCAzLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigyMCksIDksIEdG TEFHUyksCj4gKwlDT01QT1NJVEVfTk9ESVYoU0FJX1NDTEtJTl9GUkVRLCAic2FpX3NjbGtpbl9m cmVxIiwgc2FpX3NjbGtpbl9mcmVxX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDc1KSwg MCwgMywgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMjApLCAxMCwgR0ZMQUdTKSwK PiArCUNPTVBPU0lURV9OT0RJVihTQUlfU0NMS0lOX0NPVU5URVIsICJzYWlfc2Nsa2luX2NvdW50 ZXIiLCBzYWlfc2Nsa2luX2ZyZXFfcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oNzUpLCAz LCAzLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigyMCksIDExLCBHRkxBR1MpLAo+ ICsJQ09NUE9TSVRFKENMS19JM0MwLCAiY2xrX2kzYzAiLCBncGxsX2NwbGxfYXVwbGxfc3BsbF9w LCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTig3OCksIDUsIDIsIE1GTEFHUywgMCwgNSwgREZM QUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMjApLCAxMiwgR0ZMQUdTKSwKPiArCUNPTVBP U0lURShDTEtfSTNDMSwgImNsa19pM2MxIiwgZ3BsbF9jcGxsX2F1cGxsX3NwbGxfcCwgMCwKPiAr CQkJUkszNTc2X0NMS1NFTF9DT04oNzgpLCAxMiwgMiwgTUZMQUdTLCA3LCA1LCBERkxBR1MsCj4g KwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigyMCksIDEzLCBHRkxBR1MpLAo+ICsJR0FURShQQ0xLX0NT SURQSFkxLCAicGNsa19jc2lkcGh5MSIsICJwY2xrX2J1c19yb290IiwgMCwKPiArCQkJUkszNTc2 X0NMS0dBVEVfQ09OKDQwKSwgMiwgR0ZMQUdTKSwKPiArCj4gKwkvKiBjY2kgKi8KPiArCUNPTVBP U0lURShQQ0xLX0NDSV9ST09ULCAicGNsa19jY2lfcm9vdCIsIG11eF8yNG1fY2NpcHZ0cGxsX2dw bGxfbHBsbF9wLCBDTEtfSVNfQ1JJVElDQUwsCj4gKwkJCVJLMzU3Nl9DQ0lfQ0xLU0VMX0NPTig0 KSwgNSwgMiwgTUZMQUdTLCAwLCA1LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DQ0lfQ0xLR0FURV9D T04oMSksIDEwLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKEFDTEtfQ0NJX1JPT1QsICJhY2xrX2Nj aV9yb290IiwgbXV4XzI0bV9jY2lwdnRwbGxfZ3BsbF9scGxsX3AsIENMS19JU19DUklUSUNBTCwK PiArCQkJUkszNTc2X0NDSV9DTEtTRUxfQ09OKDQpLCAxMiwgMiwgTUZMQUdTLCA3LCA1LCBERkxB R1MsCj4gKwkJCVJLMzU3Nl9DQ0lfQ0xLR0FURV9DT04oMSksIDExLCBHRkxBR1MpLAo+ICsKPiAr CS8qIGNlbnRlciAqLwo+ICsJQ09NUE9TSVRFX0RJVl9PRkZTRVQoQUNMS19DRU5URVJfUk9PVCwg ImFjbGtfY2VudGVyX3Jvb3QiLCBncGxsX2NwbGxfc3BsbF9hdXBsbF9icGxsX3AsIENMS19JU19D UklUSUNBTCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oMTY4KSwgNSwgMywgTUZMQUdTLAo+ICsJ CQlSSzM1NzZfQ0xLU0VMX0NPTigxNjcpLCA5LCA1LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtH QVRFX0NPTig3MiksIDAsIEdGTEFHUyksCj4gKwlDT01QT1NJVEVfTk9ESVYoQUNMS19DRU5URVJf TE9XX1JPT1QsICJhY2xrX2NlbnRlcl9sb3dfcm9vdCIsIG11eF81MDBtXzI1MG1fMTAwbV8yNG1f cCwgQ0xLX0lTX0NSSVRJQ0FMLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxNjgpLCA4LCAyLCBN RkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig3MiksIDEsIEdGTEFHUyksCj4gKwlDT01Q T1NJVEVfTk9ESVYoSENMS19DRU5URVJfUk9PVCwgImhjbGtfY2VudGVyX3Jvb3QiLCBtdXhfMjAw bV8xMDBtXzUwbV8yNG1fcCwgQ0xLX0lTX0NSSVRJQ0FMLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NP TigxNjgpLCAxMCwgMiwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNzIpLCAyLCBH RkxBR1MpLAo+ICsJQ09NUE9TSVRFX05PRElWKFBDTEtfQ0VOVEVSX1JPT1QsICJwY2xrX2NlbnRl cl9yb290IiwgbXV4XzIwMG1fMTAwbV81MG1fMjRtX3AsIENMS19JU19DUklUSUNBTCwKPiArCQkJ UkszNTc2X0NMS1NFTF9DT04oMTY4KSwgMTIsIDIsIE1GTEFHUywKPiArCQkJUkszNTc2X0NMS0dB VEVfQ09OKDcyKSwgMywgR0ZMQUdTKSwKPiArCUdBVEUoQUNMS19ETUEyRERSLCAiYWNsa19kbWEy ZGRyIiwgImFjbGtfY2VudGVyX3Jvb3QiLCBDTEtfSUdOT1JFX1VOVVNFRCwKPiArCQkJUkszNTc2 X0NMS0dBVEVfQ09OKDcyKSwgNSwgR0ZMQUdTKSwKPiArCUdBVEUoQUNMS19ERFJfU0hBUkVNRU0s ICJhY2xrX2Rkcl9zaGFyZW1lbSIsICJhY2xrX2NlbnRlcl9sb3dfcm9vdCIsIENMS19JR05PUkVf VU5VU0VELAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNzIpLCA2LCBHRkxBR1MpLAo+ICsJR0FU RShQQ0xLX0RNQTJERFIsICJwY2xrX2RtYTJkZHIiLCAicGNsa19jZW50ZXJfcm9vdCIsIENMS19J R05PUkVfVU5VU0VELAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNzIpLCAxMCwgR0ZMQUdTKSwK PiArCUdBVEUoUENMS19TSEFSRU1FTSwgInBjbGtfc2hhcmVtZW0iLCAicGNsa19jZW50ZXJfcm9v dCIsIENMS19JR05PUkVfVU5VU0VELAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNzIpLCAxMSwg R0ZMQUdTKSwKPiArCj4gKwkvKiBkZHIgKi8KPiArCUNPTVBPU0lURShQQ0xLX0REUl9ST09ULCAi cGNsa19kZHJfcm9vdCIsIGdwbGxfY3BsbF8yNG1fcCwgQ0xLX0lTX0NSSVRJQ0FMLAo+ICsJCQlS SzM1NzZfQ0xLU0VMX0NPTig3NiksIDUsIDIsIE1GTEFHUywgMCwgNSwgREZMQUdTLAo+ICsJCQlS SzM1NzZfQ0xLR0FURV9DT04oMjEpLCAwLCBHRkxBR1MpLAo+ICsJR0FURShQQ0xLX0REUl9NT05f Q0gwLCAicGNsa19kZHJfbW9uX2NoMCIsICJwY2xrX2Rkcl9yb290IiwgQ0xLX0lHTk9SRV9VTlVT RUQsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigyMSksIDEsIEdGTEFHUyksCj4gKwlDT01QT1NJ VEUoSENMS19ERFJfUk9PVCwgImhjbGtfZGRyX3Jvb3QiLCBncGxsX2NwbGxfcCwgQ0xLX0lHTk9S RV9VTlVTRUQsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDc3KSwgNSwgMSwgTUZMQUdTLCAwLCA1 LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigyMiksIDExLCBHRkxBR1MpLAo+ICsJ R0FURShGQ0xLX0REUl9DTTBfQ09SRSwgImZjbGtfZGRyX2NtMF9jb3JlIiwgImhjbGtfZGRyX3Jv b3QiLCBDTEtfSVNfQ1JJVElDQUwsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigyMiksIDE1LCBH RkxBR1MpLAo+ICsJQ09NUE9TSVRFX05PRElWKENMS19ERFJfVElNRVJfUk9PVCwgImNsa19kZHJf dGltZXJfcm9vdCIsIG11eF8xMDBtXzI0bV9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTig3 NyksIDYsIDEsIE1GTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDIzKSwgMywgR0ZMQUdT KSwKPiArCUdBVEUoQ0xLX0REUl9USU1FUjAsICJjbGtfZGRyX3RpbWVyMCIsICJjbGtfZGRyX3Rp bWVyX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMjMpLCA0LCBHRkxBR1MpLAo+ ICsJR0FURShDTEtfRERSX1RJTUVSMSwgImNsa19kZHJfdGltZXIxIiwgImNsa19kZHJfdGltZXJf cm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigyMyksIDUsIEdGTEFHUyksCj4gKwlH QVRFKFRDTEtfV0RUX0REUiwgInRjbGtfd2R0X2RkciIsICJ4aW4yNG0iLCAwLAo+ICsJCQlSSzM1 NzZfQ0xLR0FURV9DT04oMjMpLCA2LCBHRkxBR1MpLAo+ICsJR0FURShQQ0xLX1dEVCwgInBjbGtf d2R0IiwgInBjbGtfZGRyX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMjMpLCA3 LCBHRkxBR1MpLAo+ICsJR0FURShQQ0xLX1RJTUVSLCAicGNsa190aW1lciIsICJwY2xrX2Rkcl9y b290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDIzKSwgOCwgR0ZMQUdTKSwKPiArCUNP TVBPU0lURShDTEtfRERSX0NNMF9SVEMsICJjbGtfZGRyX2NtMF9ydGMiLCBtdXhfMjRtXzMya19w LCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTig3NyksIDEyLCAxLCBNRkxBR1MsIDcsIDUsIERG TEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDIzKSwgMTAsIEdGTEFHUyksCj4gKwo+ICsJ LyogZ3B1ICovCj4gKwlDT01QT1NJVEUoQ0xLX0dQVV9TUkNfUFJFLCAiY2xrX2dwdV9zcmNfcHJl IiwgZ3BsbF9jcGxsX2F1cGxsX3NwbGxfbHBsbF9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NP TigxNjUpLCA1LCAzLCBNRkxBR1MsIDAsIDUsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVf Q09OKDY5KSwgMSwgR0ZMQUdTKSwKPiArCUdBVEUoQ0xLX0dQVSwgImNsa19ncHUiLCAiY2xrX2dw dV9zcmNfcHJlIiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDY5KSwgMywgR0ZMQUdTKSwK PiArCUNPTVBPU0lURV9OT0RJVihQQ0xLX0dQVV9ST09ULCAicGNsa19ncHVfcm9vdCIsIG11eF8x MDBtXzUwbV8yNG1fcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oMTY2KSwgMTAsIDIsIE1G TEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDY5KSwgOCwgR0ZMQUdTKSwKPiArCj4gKwkv KiBucHUgKi8KPiArCUNPTVBPU0lURV9OT0RJVihIQ0xLX1JLTk5fUk9PVCwgImhjbGtfcmtubl9y b290IiwgbXV4XzIwMG1fMTAwbV81MG1fMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09O KDg2KSwgMCwgMiwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMzEpLCA0LCBHRkxB R1MpLAo+ICsJQ09NUE9TSVRFKENMS19SS05OX0RTVTAsICJjbGtfcmtubl9kc3UwIiwgZ3BsbF9j cGxsX2F1cGxsX3NwbGxfcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oODYpLCA3LCAyLCBN RkxBR1MsIDIsIDUsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDMxKSwgNSwgR0ZM QUdTKSwKPiArCUdBVEUoQUNMS19SS05OMCwgImFjbGtfcmtubjAiLCAiY2xrX3Jrbm5fZHN1MCIs IDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigyOCksIDksIEdGTEFHUyksCj4gKwlHQVRFKEFD TEtfUktOTjEsICJhY2xrX3Jrbm4xIiwgImNsa19ya25uX2RzdTAiLCAwLAo+ICsJCQlSSzM1NzZf Q0xLR0FURV9DT04oMjkpLCAwLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFX05PRElWKFBDTEtfTlBV VE9QX1JPT1QsICJwY2xrX25wdXRvcF9yb290IiwgbXV4XzEwMG1fNTBtXzI0bV9wLCAwLAo+ICsJ CQlSSzM1NzZfQ0xLU0VMX0NPTig4NyksIDAsIDIsIE1GTEFHUywKPiArCQkJUkszNTc2X0NMS0dB VEVfQ09OKDMxKSwgOCwgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19OUFVfVElNRVIsICJwY2xrX25w dV90aW1lciIsICJwY2xrX25wdXRvcF9yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09O KDMxKSwgMTAsIEdGTEFHUyksCj4gKwlDT01QT1NJVEVfTk9ESVYoQ0xLX05QVVRJTUVSX1JPT1Qs ICJjbGtfbnB1dGltZXJfcm9vdCIsIG11eF8xMDBtXzI0bV9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xL U0VMX0NPTig4NyksIDIsIDEsIE1GTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDMxKSwg MTEsIEdGTEFHUyksCj4gKwlHQVRFKENMS19OUFVUSU1FUjAsICJjbGtfbnB1dGltZXIwIiwgImNs a19ucHV0aW1lcl9yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDMxKSwgMTIsIEdG TEFHUyksCj4gKwlHQVRFKENMS19OUFVUSU1FUjEsICJjbGtfbnB1dGltZXIxIiwgImNsa19ucHV0 aW1lcl9yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDMxKSwgMTMsIEdGTEFHUyks Cj4gKwlHQVRFKFBDTEtfTlBVX1dEVCwgInBjbGtfbnB1X3dkdCIsICJwY2xrX25wdXRvcF9yb290 IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDMxKSwgMTQsIEdGTEFHUyksCj4gKwlHQVRF KFRDTEtfTlBVX1dEVCwgInRjbGtfbnB1X3dkdCIsICJ4aW4yNG0iLCAwLAo+ICsJCQlSSzM1NzZf Q0xLR0FURV9DT04oMzEpLCAxNSwgR0ZMQUdTKSwKPiArCUdBVEUoQUNMS19SS05OX0NCVUYsICJh Y2xrX3Jrbm5fY2J1ZiIsICJjbGtfcmtubl9kc3UwIiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVf Q09OKDMyKSwgMCwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihIQ0xLX05QVV9DTTBfUk9P VCwgImhjbGtfbnB1X2NtMF9yb290IiwgbXV4XzQwMG1fMjAwbV8xMDBtXzI0bV9wLCAwLAo+ICsJ CQlSSzM1NzZfQ0xLU0VMX0NPTig4NyksIDMsIDIsIE1GTEFHUywKPiArCQkJUkszNTc2X0NMS0dB VEVfQ09OKDMyKSwgNSwgR0ZMQUdTKSwKPiArCUdBVEUoRkNMS19OUFVfQ00wX0NPUkUsICJmY2xr X25wdV9jbTBfY29yZSIsICJoY2xrX25wdV9jbTBfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtH QVRFX0NPTigzMiksIDcsIEdGTEFHUyksCj4gKwlDT01QT1NJVEUoQ0xLX05QVV9DTTBfUlRDLCAi Y2xrX25wdV9jbTBfcnRjIiwgbXV4XzI0bV8zMmtfcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9D T04oODcpLCAxMCwgMSwgTUZMQUdTLCA1LCA1LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRF X0NPTigzMiksIDksIEdGTEFHUyksCj4gKwlHQVRFKEhDTEtfUktOTl9DQlVGLCAiaGNsa19ya25u X2NidWYiLCAiaGNsa19ya25uX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMzIp LCAxMiwgR0ZMQUdTKSwKPiArCj4gKwkvKiBudm0gKi8KPiArCUNPTVBPU0lURV9OT0RJVihIQ0xL X05WTV9ST09ULCAiaGNsa19udm1fcm9vdCIsIG11eF8yMDBtXzEwMG1fNTBtXzI0bV9wLCBDTEtf SVNfQ1JJVElDQUwsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDg4KSwgMCwgMiwgTUZMQUdTLAo+ ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMzMpLCAwLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKEFD TEtfTlZNX1JPT1QsICJhY2xrX252bV9yb290IiwgZ3BsbF9jcGxsX3AsIENMS19JU19DUklUSUNB TCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oODgpLCA3LCAxLCBNRkxBR1MsIDIsIDUsIERGTEFH UywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDMzKSwgMSwgR0ZMQUdTKSwKPiArCUNPTVBPU0lU RShTQ0xLX0ZTUElfWDIsICJzY2xrX2ZzcGlfeDIiLCBncGxsX2NwbGxfMjRtX3AsIDAsCj4gKwkJ CVJLMzU3Nl9DTEtTRUxfQ09OKDg5KSwgNiwgMiwgTUZMQUdTLCAwLCA2LCBERkxBR1MsCj4gKwkJ CVJLMzU3Nl9DTEtHQVRFX0NPTigzMyksIDYsIEdGTEFHUyksCj4gKwlHQVRFKEhDTEtfRlNQSSwg ImhjbGtfZnNwaSIsICJoY2xrX252bV9yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09O KDMzKSwgNywgR0ZMQUdTKSwKPiArCUNPTVBPU0lURShDQ0xLX1NSQ19FTU1DLCAiY2Nsa19zcmNf ZW1tYyIsIGdwbGxfY3BsbF8yNG1fcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oODkpLCAx NCwgMiwgTUZMQUdTLCA4LCA2LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigzMyks IDgsIEdGTEFHUyksCj4gKwlHQVRFKEhDTEtfRU1NQywgImhjbGtfZW1tYyIsICJoY2xrX252bV9y b290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDMzKSwgOSwgR0ZMQUdTKSwKPiArCUdB VEUoQUNMS19FTU1DLCAiYWNsa19lbW1jIiwgImFjbGtfbnZtX3Jvb3QiLCAwLAo+ICsJCQlSSzM1 NzZfQ0xLR0FURV9DT04oMzMpLCAxMCwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihCQ0xL X0VNTUMsICJiY2xrX2VtbWMiLCBtdXhfMjAwbV8xMDBtXzUwbV8yNG1fcCwgMCwKPiArCQkJUksz NTc2X0NMS1NFTF9DT04oOTApLCAwLCAyLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NP TigzMyksIDExLCBHRkxBR1MpLAo+ICsJR0FURShUQ0xLX0VNTUMsICJ0Y2xrX2VtbWMiLCAieGlu MjRtIiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDMzKSwgMTIsIEdGTEFHUyksCj4gKwo+ ICsJLyogdXNiICovCj4gKwlDT01QT1NJVEUoQUNMS19VRlNfUk9PVCwgImFjbGtfdWZzX3Jvb3Qi LCBncGxsX2NwbGxfcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oMTE1KSwgNSwgMSwgTUZM QUdTLCAwLCA1LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig0NyksIDAsIEdGTEFH UyksCj4gKwlDT01QT1NJVEUoQUNMS19VU0JfUk9PVCwgImFjbGtfdXNiX3Jvb3QiLCBncGxsX2Nw bGxfcCwgQ0xLX0lTX0NSSVRJQ0FMLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxMTUpLCAxMSwg MSwgTUZMQUdTLCA2LCA1LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig0NyksIDEs IEdGTEFHUyksCj4gKwlDT01QT1NJVEVfTk9ESVYoUENMS19VU0JfUk9PVCwgInBjbGtfdXNiX3Jv b3QiLCBtdXhfMTAwbV81MG1fMjRtX3AsIENMS19JU19DUklUSUNBTCwKPiArCQkJUkszNTc2X0NM S1NFTF9DT04oMTE1KSwgMTIsIDIsIE1GTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDQ3 KSwgMiwgR0ZMQUdTKSwKPiArCUdBVEUoQUNMS19VU0IzT1RHMCwgImFjbGtfdXNiM290ZzAiLCAi YWNsa191c2Jfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig0NyksIDUsIEdGTEFH UyksCj4gKwlHQVRFKENMS19SRUZfVVNCM09URzAsICJjbGtfcmVmX3VzYjNvdGcwIiwgInhpbjI0 bSIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig0NyksIDYsIEdGTEFHUyksCj4gKwlHQVRF KENMS19TVVNQRU5EX1VTQjNPVEcwLCAiY2xrX3N1c3BlbmRfdXNiM290ZzAiLCAieGluMjRtIiwg MCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDQ3KSwgNywgR0ZMQUdTKSwKPiArCUdBVEUoQUNM S19NTVUyLCAiYWNsa19tbXUyIiwgImFjbGtfdXNiX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xL R0FURV9DT04oNDcpLCAxMiwgR0ZMQUdTKSwKPiArCUdBVEUoQUNMS19TTFZfTU1VMiwgImFjbGtf c2x2X21tdTIiLCAiYWNsa191c2Jfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig0 NyksIDEzLCBHRkxBR1MpLAo+ICsJR0FURShBQ0xLX1VGU19TWVMsICJhY2xrX3Vmc19zeXMiLCAi YWNsa191ZnNfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig0NyksIDE1LCBHRkxB R1MpLAo+ICsKPiArCS8qIHZkZWMgKi8KPiArCUNPTVBPU0lURV9OT0RJVihIQ0xLX1JLVkRFQ19S T09ULCAiaGNsa19ya3ZkZWNfcm9vdCIsIG11eF8yMDBtXzEwMG1fNTBtXzI0bV9wLCAwLAo+ICsJ CQlSSzM1NzZfQ0xLU0VMX0NPTigxMTApLCAwLCAyLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtH QVRFX0NPTig0NSksIDAsIEdGTEFHUyksCj4gKwlDT01QT1NJVEUoQUNMS19SS1ZERUNfUk9PVCwg ImFjbGtfcmt2ZGVjX3Jvb3QiLCBncGxsX2NwbGxfYXVwbGxfc3BsbF9wLCAwLAo+ICsJCQlSSzM1 NzZfQ0xLU0VMX0NPTigxMTApLCA3LCAyLCBNRkxBR1MsIDIsIDUsIERGTEFHUywKPiArCQkJUksz NTc2X0NMS0dBVEVfQ09OKDQ1KSwgMSwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURShBQ0xLX1JLVkRF Q19ST09UX0JBSywgImFjbGtfcmt2ZGVjX3Jvb3RfYmFrIiwgY3BsbF92cGxsX2xwbGxfYnBsbF9w LCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxMTApLCAxNCwgMiwgTUZMQUdTLCA5LCA1LCBE RkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig0NSksIDIsIEdGTEFHUyksCj4gKwlHQVRF KEhDTEtfUktWREVDLCAiaGNsa19ya3ZkZWMiLCAiaGNsa19ya3ZkZWNfcm9vdCIsIDAsCj4gKwkJ CVJLMzU3Nl9DTEtHQVRFX0NPTig0NSksIDMsIEdGTEFHUyksCj4gKwlDT01QT1NJVEUoQ0xLX1JL VkRFQ19IRVZDX0NBLCAiY2xrX3JrdmRlY19oZXZjX2NhIiwgZ3BsbF9jcGxsX2xwbGxfYnBsbF9w LCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxMTEpLCA1LCAyLCBNRkxBR1MsIDAsIDUsIERG TEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDQ1KSwgOCwgR0ZMQUdTKSwKPiArCUdBVEUo Q0xLX1JLVkRFQ19DT1JFLCAiY2xrX3JrdmRlY19jb3JlIiwgImFjbGtfcmt2ZGVjX3Jvb3QiLCAw LAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNDUpLCA5LCBHRkxBR1MpLAo+ICsKPiArCS8qIHZl bmMgKi8KPiArCUNPTVBPU0lURV9OT0RJVihIQ0xLX1ZFUFUwX1JPT1QsICJoY2xrX3ZlcHUwX3Jv b3QiLCBtdXhfMjAwbV8xMDBtXzUwbV8yNG1fcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04o MTI0KSwgMCwgMiwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNTEpLCAwLCBHRkxB R1MpLAo+ICsJQ09NUE9TSVRFKEFDTEtfVkVQVTBfUk9PVCwgImFjbGtfdmVwdTBfcm9vdCIsIGdw bGxfY3BsbF9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxMjQpLCA3LCAxLCBNRkxBR1Ms IDIsIDUsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDUxKSwgMSwgR0ZMQUdTKSwK PiArCUNPTVBPU0lURShDTEtfVkVQVTBfQ09SRSwgImNsa192ZXB1MF9jb3JlIiwgZ3BsbF9jcGxs X3NwbGxfbHBsbF9icGxsX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDEyNCksIDEzLCAz LCBNRkxBR1MsIDgsIDUsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDUxKSwgNiwg R0ZMQUdTKSwKPiArCUdBVEUoSENMS19WRVBVMCwgImhjbGtfdmVwdTAiLCAiaGNsa192ZXB1MF9y b290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDUxKSwgNCwgR0ZMQUdTKSwKPiArCUdB VEUoQUNMS19WRVBVMCwgImFjbGtfdmVwdTAiLCAiYWNsa192ZXB1MF9yb290IiwgMCwKPiArCQkJ UkszNTc2X0NMS0dBVEVfQ09OKDUxKSwgNSwgR0ZMQUdTKSwKPiArCj4gKwkvKiB2aSAqLwo+ICsJ Q09NUE9TSVRFKEFDTEtfVklfUk9PVCwgImFjbGtfdmlfcm9vdCIsIGdwbGxfc3BsbF9pc3BwdnRw bGxfYnBsbF9scGxsX3AsIENMS19JU19DUklUSUNBTCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04o MTI4KSwgNSwgMywgTUZMQUdTLCAwLCA1LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NP Tig1MyksIDAsIEdGTEFHUyksCj4gKwlDT01QT1NJVEVfTk9NVVgoQUNMS19WSV9ST09UX0lOVEVS LCAiYWNsa192aV9yb290X2ludGVyIiwgImFjbGtfdmlfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9D TEtTRUxfQ09OKDEzMCksIDEwLCAzLCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig1 NCksIDEzLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFX05PRElWKEhDTEtfVklfUk9PVCwgImhjbGtf dmlfcm9vdCIsIGhjbGtfdmlfcm9vdF9wLCBDTEtfSVNfQ1JJVElDQUwsCj4gKwkJCVJLMzU3Nl9D TEtTRUxfQ09OKDEyOCksIDgsIDIsIE1GTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDUz KSwgMSwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihQQ0xLX1ZJX1JPT1QsICJwY2xrX3Zp X3Jvb3QiLCBtdXhfMTAwbV81MG1fMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDEy OCksIDEwLCAyLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig1MyksIDIsIEdGTEFH UyksCj4gKwlDT01QT1NJVEUoRENMS19WSUNBUCwgImRjbGtfdmljYXAiLCBncGxsX2NwbGxfcCwg MCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oMTI5KSwgNSwgMSwgTUZMQUdTLCAwLCA1LCBERkxB R1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig1MyksIDYsIEdGTEFHUyksCj4gKwlHQVRFKEFD TEtfVklDQVAsICJhY2xrX3ZpY2FwIiwgImFjbGtfdmlfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9D TEtHQVRFX0NPTig1MyksIDcsIEdGTEFHUyksCj4gKwlHQVRFKEhDTEtfVklDQVAsICJoY2xrX3Zp Y2FwIiwgImhjbGtfdmlfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig1MyksIDgs IEdGTEFHUyksCj4gKwlDT01QT1NJVEUoQ0xLX0lTUF9DT1JFLCAiY2xrX2lzcF9jb3JlIiwgZ3Bs bF9zcGxsX2lzcHB2dHBsbF9icGxsX2xwbGxfcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04o MTI5KSwgMTEsIDMsIE1GTEFHUywgNiwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9D T04oNTMpLCA5LCBHRkxBR1MpLAo+ICsJR0FURShDTEtfSVNQX0NPUkVfTUFSVklOLCAiY2xrX2lz cF9jb3JlX21hcnZpbiIsICJjbGtfaXNwX2NvcmUiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9D T04oNTMpLCAxMCwgR0ZMQUdTKSwKPiArCUdBVEUoQ0xLX0lTUF9DT1JFX1ZJQ0FQLCAiY2xrX2lz cF9jb3JlX3ZpY2FwIiwgImNsa19pc3BfY29yZSIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NP Tig1MyksIDExLCBHRkxBR1MpLAo+ICsJR0FURShBQ0xLX0lTUCwgImFjbGtfaXNwIiwgImFjbGtf dmlfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig1MyksIDEyLCBHRkxBR1MpLAo+ ICsJR0FURShIQ0xLX0lTUCwgImhjbGtfaXNwIiwgImhjbGtfdmlfcm9vdCIsIDAsCj4gKwkJCVJL MzU3Nl9DTEtHQVRFX0NPTig1MyksIDEzLCBHRkxBR1MpLAo+ICsJR0FURShBQ0xLX1ZQU1MsICJh Y2xrX3Zwc3MiLCAiYWNsa192aV9yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDUz KSwgMTUsIEdGTEFHUyksCj4gKwlHQVRFKEhDTEtfVlBTUywgImhjbGtfdnBzcyIsICJoY2xrX3Zp X3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNTQpLCAwLCBHRkxBR1MpLAo+ICsJ R0FURShDTEtfQ09SRV9WUFNTLCAiY2xrX2NvcmVfdnBzcyIsICJjbGtfaXNwX2NvcmUiLCAwLAo+ ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNTQpLCAxLCBHRkxBR1MpLAo+ICsJR0FURShQQ0xLX0NT SV9IT1NUXzAsICJwY2xrX2NzaV9ob3N0XzAiLCAicGNsa192aV9yb290IiwgMCwKPiArCQkJUksz NTc2X0NMS0dBVEVfQ09OKDU0KSwgNCwgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19DU0lfSE9TVF8x LCAicGNsa19jc2lfaG9zdF8xIiwgInBjbGtfdmlfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtH QVRFX0NPTig1NCksIDUsIEdGTEFHUyksCj4gKwlHQVRFKFBDTEtfQ1NJX0hPU1RfMiwgInBjbGtf Y3NpX2hvc3RfMiIsICJwY2xrX3ZpX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04o NTQpLCA2LCBHRkxBR1MpLAo+ICsJR0FURShQQ0xLX0NTSV9IT1NUXzMsICJwY2xrX2NzaV9ob3N0 XzMiLCAicGNsa192aV9yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDU0KSwgNywg R0ZMQUdTKSwKPiArCUdBVEUoUENMS19DU0lfSE9TVF80LCAicGNsa19jc2lfaG9zdF80IiwgInBj bGtfdmlfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig1NCksIDgsIEdGTEFHUyks Cj4gKwlDT01QT1NJVEVfTk9ESVYoSUNMS19DU0lIT1NUMDEsICJpY2xrX2NzaWhvc3QwMSIsIG11 eF80MDBtXzIwMG1fMTAwbV8yNG1fcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oMTMwKSwg NywgMiwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNTQpLCAxMCwgR0ZMQUdTKSwK PiArCUdBVEUoSUNMS19DU0lIT1NUMCwgImljbGtfY3NpaG9zdDAiLCAiaWNsa19jc2lob3N0MDEi LCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNTQpLCAxMSwgR0ZMQUdTKSwKPiArCUNPTVBP U0lURShBQ0xLX1ZPUF9ST09ULCAiYWNsa192b3Bfcm9vdCIsIGdwbGxfY3BsbF9hdXBsbF9zcGxs X2xwbGxfcCwgQ0xLX0lTX0NSSVRJQ0FMLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxNDQpLCA1 LCAzLCBNRkxBR1MsIDAsIDUsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDYxKSwg MCwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihIQ0xLX1ZPUF9ST09ULCAiaGNsa192b3Bf cm9vdCIsIG11eF8yMDBtXzEwMG1fNTBtXzI0bV9wLCBDTEtfSVNfQ1JJVElDQUwsCj4gKwkJCVJL MzU3Nl9DTEtTRUxfQ09OKDE0NCksIDEwLCAyLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRF X0NPTig2MSksIDIsIEdGTEFHUyksCj4gKwlDT01QT1NJVEVfTk9ESVYoUENMS19WT1BfUk9PVCwg InBjbGtfdm9wX3Jvb3QiLCBtdXhfMTAwbV81MG1fMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtT RUxfQ09OKDE0NCksIDEyLCAyLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig2MSks IDMsIEdGTEFHUyksCj4gKwlHQVRFKEhDTEtfVk9QLCAiaGNsa192b3AiLCAiaGNsa192b3Bfcm9v dCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig2MSksIDgsIEdGTEFHUyksCj4gKwlHQVRF KEFDTEtfVk9QLCAiYWNsa192b3AiLCAiYWNsa192b3Bfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9D TEtHQVRFX0NPTig2MSksIDksIEdGTEFHUyksCj4gKwlDT01QT1NJVEUoRENMS19WUDBfU1JDLCAi ZGNsa192cDBfc3JjIiwgZ3BsbF9jcGxsX3ZwbGxfYnBsbF9scGxsX3AsIENMS19TRVRfUkFURV9O T19SRVBBUkVOVCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oMTQ1KSwgOCwgMywgTUZMQUdTLCAw LCA4LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig2MSksIDEwLCBHRkxBR1MpLAo+ ICsJQ09NUE9TSVRFKERDTEtfVlAxX1NSQywgImRjbGtfdnAxX3NyYyIsIGdwbGxfY3BsbF92cGxs X2JwbGxfbHBsbF9wLCBDTEtfU0VUX1JBVEVfTk9fUkVQQVJFTlQsCj4gKwkJCVJLMzU3Nl9DTEtT RUxfQ09OKDE0NiksIDgsIDMsIE1GTEFHUywgMCwgOCwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xL R0FURV9DT04oNjEpLCAxMSwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURShEQ0xLX1ZQMl9TUkMsICJk Y2xrX3ZwMl9zcmMiLCBncGxsX2NwbGxfdnBsbF9icGxsX2xwbGxfcCwgQ0xLX1NFVF9SQVRFX05P X1JFUEFSRU5ULAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxNDcpLCA4LCAzLCBNRkxBR1MsIDAs IDgsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDYxKSwgMTIsIEdGTEFHUyksCj4g KwlDT01QT1NJVEVfTk9ESVYoRENMS19WUDAsICJkY2xrX3ZwMCIsIGRjbGtfdnAwX3AsIENMS19T RVRfUkFURV9QQVJFTlQgfCBDTEtfU0VUX1JBVEVfTk9fUkVQQVJFTlQsCj4gKwkJCVJLMzU3Nl9D TEtTRUxfQ09OKDE0NyksIDExLCAxLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig2 MSksIDEzLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFX05PRElWKERDTEtfVlAxLCAiZGNsa192cDEi LCBkY2xrX3ZwMV9wLCBDTEtfU0VUX1JBVEVfUEFSRU5UIHwgQ0xLX1NFVF9SQVRFX05PX1JFUEFS RU5ULAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxNDcpLCAxMiwgMSwgTUZMQUdTLAo+ICsJCQlS SzM1NzZfQ0xLR0FURV9DT04oNjIpLCAwLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFX05PRElWKERD TEtfVlAyLCAiZGNsa192cDIiLCBkY2xrX3ZwMl9wLCBDTEtfU0VUX1JBVEVfUEFSRU5UIHwgQ0xL X1NFVF9SQVRFX05PX1JFUEFSRU5ULAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxNDcpLCAxMywg MSwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNjIpLCAxLCBHRkxBR1MpLAo+ICsK PiArCS8qIHZvMCAqLwo+ICsJQ09NUE9TSVRFKEFDTEtfVk8wX1JPT1QsICJhY2xrX3ZvMF9yb290 IiwgZ3BsbF9jcGxsX2xwbGxfYnBsbF9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxNDkp LCA1LCAyLCBNRkxBR1MsIDAsIDUsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDYz KSwgMCwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihIQ0xLX1ZPMF9ST09ULCAiaGNsa192 bzBfcm9vdCIsIG11eF8yMDBtXzEwMG1fNTBtXzI0bV9wLCBDTEtfSVNfQ1JJVElDQUwsCj4gKwkJ CVJLMzU3Nl9DTEtTRUxfQ09OKDE0OSksIDcsIDIsIE1GTEFHUywKPiArCQkJUkszNTc2X0NMS0dB VEVfQ09OKDYzKSwgMSwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihQQ0xLX1ZPMF9ST09U LCAicGNsa192bzBfcm9vdCIsIG11eF8xNTBtXzEwMG1fNTBtXzI0bV9wLCAwLAo+ICsJCQlSSzM1 NzZfQ0xLU0VMX0NPTigxNDkpLCAxMSwgMiwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9D T04oNjMpLCAzLCBHRkxBR1MpLAo+ICsJR0FURShBQ0xLX0hEQ1AwLCAiYWNsa19oZGNwMCIsICJh Y2xrX3ZvMF9yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDYzKSwgMTIsIEdGTEFH UyksCj4gKwlHQVRFKEhDTEtfSERDUDAsICJoY2xrX2hkY3AwIiwgImhjbGtfdm8wX3Jvb3QiLCAw LAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNjMpLCAxMywgR0ZMQUdTKSwKPiArCUdBVEUoUENM S19IRENQMCwgInBjbGtfaGRjcDAiLCAicGNsa192bzBfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9D TEtHQVRFX0NPTig2MyksIDE0LCBHRkxBR1MpLAo+ICsJR0FURShDTEtfVFJORzBfU0tQLCAiY2xr X3RybmcwX3NrcCIsICJhY2xrX2hkY3AwIiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDY0 KSwgNCwgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19EU0lIT1NUMCwgInBjbGtfZHNpaG9zdDAiLCAi cGNsa192bzBfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig2NCksIDUsIEdGTEFH UyksCj4gKwlDT01QT1NJVEUoQ0xLX0RTSUhPU1QwLCAiY2xrX2RzaWhvc3QwIiwgZ3BsbF9jcGxs X3NwbGxfdnBsbF9icGxsX2xwbGxfcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oMTUxKSwg NywgMywgTUZMQUdTLCAwLCA3LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig2NCks IDYsIEdGTEFHUyksCj4gKwlHQVRFKFBDTEtfSERNSVRYMCwgInBjbGtfaGRtaXR4MCIsICJwY2xr X3ZvMF9yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDY0KSwgNywgR0ZMQUdTKSwK PiArCUNPTVBPU0lURShDTEtfSERNSVRYMF9FQVJDLCAiY2xrX2hkbWl0eDBfZWFyYyIsIGdwbGxf Y3BsbF9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxNTEpLCAxNSwgMSwgTUZMQUdTLCAx MCwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNjQpLCA4LCBHRkxBR1MpLAo+ ICsJR0FURShDTEtfSERNSVRYMF9SRUYsICJjbGtfaGRtaXR4MF9yZWYiLCAiYWNsa192bzBfcm9v dCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig2NCksIDksIEdGTEFHUyksCj4gKwlHQVRF KFBDTEtfRURQMCwgInBjbGtfZWRwMCIsICJwY2xrX3ZvMF9yb290IiwgMCwKPiArCQkJUkszNTc2 X0NMS0dBVEVfQ09OKDY0KSwgMTMsIEdGTEFHUyksCj4gKwlHQVRFKENMS19FRFAwXzI0TSwgImNs a19lZHAwXzI0bSIsICJ4aW4yNG0iLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNjQpLCAx NCwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihDTEtfRURQMF8yMDBNLCAiY2xrX2VkcDBf MjAwbSIsIG11eF8yMDBtXzEwMG1fNTBtXzI0bV9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NP TigxNTIpLCAxLCAyLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig2NCksIDE1LCBH RkxBR1MpLAo+ICsJQ09NUE9TSVRFKE1DTEtfU0FJNV84Q0hfU1JDLCAibWNsa19zYWk1XzhjaF9z cmMiLCBhdWRpb19mcmFjX2ludF9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxNTQpLCAx MCwgMywgTUZMQUdTLCAyLCA4LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig2NSks IDMsIEdGTEFHUyksCj4gKwlDT01QT1NJVEVfTk9ESVYoTUNMS19TQUk1XzhDSCwgIm1jbGtfc2Fp NV84Y2giLCBtY2xrX3NhaTVfOGNoX3AsIENMS19TRVRfUkFURV9QQVJFTlQsCj4gKwkJCVJLMzU3 Nl9DTEtTRUxfQ09OKDE1NCksIDEzLCAxLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NP Tig2NSksIDQsIEdGTEFHUyksCj4gKwlHQVRFKEhDTEtfU0FJNV84Q0gsICJoY2xrX3NhaTVfOGNo IiwgImhjbGtfdm8wX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNjUpLCA1LCBH RkxBR1MpLAo+ICsJQ09NUE9TSVRFKE1DTEtfU0FJNl84Q0hfU1JDLCAibWNsa19zYWk2XzhjaF9z cmMiLCBhdWRpb19mcmFjX2ludF9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxNTUpLCA4 LCAzLCBNRkxBR1MsIDAsIDgsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDY1KSwg NywgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihNQ0xLX1NBSTZfOENILCAibWNsa19zYWk2 XzhjaCIsIG1jbGtfc2FpNl84Y2hfcCwgQ0xLX1NFVF9SQVRFX1BBUkVOVCwKPiArCQkJUkszNTc2 X0NMS1NFTF9DT04oMTU1KSwgMTEsIDEsIE1GTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09O KDY1KSwgOCwgR0ZMQUdTKSwKPiArCUdBVEUoSENMS19TQUk2XzhDSCwgImhjbGtfc2FpNl84Y2gi LCAiaGNsa192bzBfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig2NSksIDksIEdG TEFHUyksCj4gKwlHQVRFKEhDTEtfU1BESUZfVFgyLCAiaGNsa19zcGRpZl90eDIiLCAiaGNsa192 bzBfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig2NSksIDEwLCBHRkxBR1MpLAo+ ICsJQ09NUE9TSVRFKE1DTEtfU1BESUZfVFgyLCAibWNsa19zcGRpZl90eDIiLCBhdWRpb19mcmFj X2ludF9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxNTYpLCA1LCAzLCBNRkxBR1MsIDAs IDUsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDY1KSwgMTMsIEdGTEFHUyksCj4g KwlHQVRFKEhDTEtfU1BESUZfUlgyLCAiaGNsa19zcGRpZl9yeDIiLCAiaGNsa192bzBfcm9vdCIs IDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig2NSksIDE0LCBHRkxBR1MpLAo+ICsJQ09NUE9T SVRFKE1DTEtfU1BESUZfUlgyLCAibWNsa19zcGRpZl9yeDIiLCBncGxsX2NwbGxfYXVwbGxfcCwg MCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oMTU2KSwgMTMsIDIsIE1GTEFHUywgOCwgNSwgREZM QUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNjUpLCAxNSwgR0ZMQUdTKSwKPiArCj4gKwkv KiB2bzEgKi8KPiArCUNPTVBPU0lURShBQ0xLX1ZPMV9ST09ULCAiYWNsa192bzFfcm9vdCIsIGdw bGxfY3BsbF9scGxsX2JwbGxfcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oMTU4KSwgNSwg MiwgTUZMQUdTLCAwLCA1LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig2NyksIDEs IEdGTEFHUyksCj4gKwlDT01QT1NJVEVfTk9ESVYoSENMS19WTzFfUk9PVCwgImhjbGtfdm8xX3Jv b3QiLCBtdXhfMjAwbV8xMDBtXzUwbV8yNG1fcCwgQ0xLX0lTX0NSSVRJQ0FMLAo+ICsJCQlSSzM1 NzZfQ0xLU0VMX0NPTigxNTgpLCA3LCAyLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NP Tig2NyksIDIsIEdGTEFHUyksCj4gKwlDT01QT1NJVEVfTk9ESVYoUENMS19WTzFfUk9PVCwgInBj bGtfdm8xX3Jvb3QiLCBtdXhfMTAwbV81MG1fMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxf Q09OKDE1OCksIDksIDIsIE1GTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDY3KSwgMywg R0ZMQUdTKSwKPiArCUNPTVBPU0lURShNQ0xLX1NBSThfOENIX1NSQywgIm1jbGtfc2FpOF84Y2hf c3JjIiwgYXVkaW9fZnJhY19pbnRfcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oMTU3KSwg OCwgMywgTUZMQUdTLCAwLCA4LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig2Niks IDEsIEdGTEFHUyksCj4gKwlDT01QT1NJVEVfTk9ESVYoTUNMS19TQUk4XzhDSCwgIm1jbGtfc2Fp OF84Y2giLCBtY2xrX3NhaThfOGNoX3AsIENMS19TRVRfUkFURV9QQVJFTlQsCj4gKwkJCVJLMzU3 Nl9DTEtTRUxfQ09OKDE1NyksIDExLCAxLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NP Tig2NiksIDIsIEdGTEFHUyksCj4gKwlHQVRFKEhDTEtfU0FJOF84Q0gsICJoY2xrX3NhaThfOGNo IiwgImhjbGtfdm8xX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNjYpLCAwLCBH RkxBR1MpLAo+ICsJQ09NUE9TSVRFKE1DTEtfU0FJN184Q0hfU1JDLCAibWNsa19zYWk3XzhjaF9z cmMiLCBhdWRpb19mcmFjX2ludF9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxNTkpLCA4 LCAzLCBNRkxBR1MsIDAsIDgsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDY3KSwg OCwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihNQ0xLX1NBSTdfOENILCAibWNsa19zYWk3 XzhjaCIsIG1jbGtfc2FpN184Y2hfcCwgQ0xLX1NFVF9SQVRFX1BBUkVOVCwKPiArCQkJUkszNTc2 X0NMS1NFTF9DT04oMTU5KSwgMTEsIDEsIE1GTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09O KDY3KSwgOSwgR0ZMQUdTKSwKPiArCUdBVEUoSENMS19TQUk3XzhDSCwgImhjbGtfc2FpN184Y2gi LCAiaGNsa192bzFfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig2NyksIDEwLCBH RkxBR1MpLAo+ICsJR0FURShIQ0xLX1NQRElGX1RYMywgImhjbGtfc3BkaWZfdHgzIiwgImhjbGtf dm8xX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNjcpLCAxMSwgR0ZMQUdTKSwK PiArCUdBVEUoSENMS19TUERJRl9UWDQsICJoY2xrX3NwZGlmX3R4NCIsICJoY2xrX3ZvMV9yb290 IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDY3KSwgMTIsIEdGTEFHUyksCj4gKwlHQVRF KEhDTEtfU1BESUZfVFg1LCAiaGNsa19zcGRpZl90eDUiLCAiaGNsa192bzFfcm9vdCIsIDAsCj4g KwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig2NyksIDEzLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKE1D TEtfU1BESUZfVFgzLCAibWNsa19zcGRpZl90eDMiLCBhdWRpb19mcmFjX2ludF9wLCAwLAo+ICsJ CQlSSzM1NzZfQ0xLU0VMX0NPTigxNjApLCA4LCAzLCBNRkxBR1MsIDAsIDgsIERGTEFHUywKPiAr CQkJUkszNTc2X0NMS0dBVEVfQ09OKDY3KSwgMTQsIEdGTEFHUyksCj4gKwlDT01QT1NJVEVfTk9N VVgoQ0xLX0FVWDE2TUhaXzAsICJjbGtfYXV4MTZtaHpfMCIsICJncGxsIiwgMCwKPiArCQkJUksz NTc2X0NMS1NFTF9DT04oMTYxKSwgMCwgOCwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9D T04oNjcpLCAxNSwgR0ZMQUdTKSwKPiArCUdBVEUoQUNMS19EUDAsICJhY2xrX2RwMCIsICJhY2xr X3ZvMV9yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDY4KSwgMCwgR0ZMQUdTKSwK PiArCUdBVEUoUENMS19EUDAsICJwY2xrX2RwMCIsICJwY2xrX3ZvMV9yb290IiwgMCwKPiArCQkJ UkszNTc2X0NMS0dBVEVfQ09OKDY4KSwgMSwgR0ZMQUdTKSwKPiArCUdBVEUoQUNMS19IRENQMSwg ImFjbGtfaGRjcDEiLCAiYWNsa192bzFfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NP Tig2OCksIDQsIEdGTEFHUyksCj4gKwlHQVRFKEhDTEtfSERDUDEsICJoY2xrX2hkY3AxIiwgImhj bGtfdm8xX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNjgpLCA1LCBHRkxBR1Mp LAo+ICsJR0FURShQQ0xLX0hEQ1AxLCAicGNsa19oZGNwMSIsICJwY2xrX3ZvMV9yb290IiwgMCwK PiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDY4KSwgNiwgR0ZMQUdTKSwKPiArCUdBVEUoQ0xLX1RS TkcxX1NLUCwgImNsa190cm5nMV9za3AiLCAiYWNsa19oZGNwMSIsIDAsCj4gKwkJCVJLMzU3Nl9D TEtHQVRFX0NPTig2OCksIDcsIEdGTEFHUyksCj4gKwlHQVRFKEhDTEtfU0FJOV84Q0gsICJoY2xr X3NhaTlfOGNoIiwgImhjbGtfdm8xX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04o NjgpLCA5LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKE1DTEtfU0FJOV84Q0hfU1JDLCAibWNsa19z YWk5XzhjaF9zcmMiLCBhdWRpb19mcmFjX2ludF9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NP TigxNjIpLCA4LCAzLCBNRkxBR1MsIDAsIDgsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVf Q09OKDY4KSwgMTAsIEdGTEFHUyksCj4gKwlDT01QT1NJVEVfTk9ESVYoTUNMS19TQUk5XzhDSCwg Im1jbGtfc2FpOV84Y2giLCBtY2xrX3NhaTlfOGNoX3AsIENMS19TRVRfUkFURV9QQVJFTlQsCj4g KwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDE2MiksIDExLCAxLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9D TEtHQVRFX0NPTig2OCksIDExLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKE1DTEtfU1BESUZfVFg0 LCAibWNsa19zcGRpZl90eDQiLCBhdWRpb19mcmFjX2ludF9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xL U0VMX0NPTigxNjMpLCA4LCAzLCBNRkxBR1MsIDAsIDgsIERGTEFHUywKPiArCQkJUkszNTc2X0NM S0dBVEVfQ09OKDY4KSwgMTIsIEdGTEFHUyksCj4gKwlDT01QT1NJVEUoTUNMS19TUERJRl9UWDUs ICJtY2xrX3NwZGlmX3R4NSIsIGF1ZGlvX2ZyYWNfaW50X3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtT RUxfQ09OKDE2NCksIDgsIDMsIE1GTEFHUywgMCwgOCwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xL R0FURV9DT04oNjgpLCAxMywgR0ZMQUdTKSwKPiArCj4gKwkvKiB2cHUgKi8KPiArCUNPTVBPU0lU RShBQ0xLX1ZQVV9ST09ULCAiYWNsa192cHVfcm9vdCIsIGdwbGxfc3BsbF9jcGxsX2JwbGxfbHBs bF9wLCBDTEtfSVNfQ1JJVElDQUwsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDExOCksIDUsIDMs IE1GTEFHUywgMCwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNDkpLCAwLCBH RkxBR1MpLAo+ICsJQ09NUE9TSVRFX05PRElWKEFDTEtfVlBVX01JRF9ST09ULCAiYWNsa192cHVf bWlkX3Jvb3QiLCBtdXhfNjAwbV80MDBtXzMwMG1fMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtT RUxfQ09OKDExOCksIDgsIDIsIE1GTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDQ5KSwg MSwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihIQ0xLX1ZQVV9ST09ULCAiaGNsa192cHVf cm9vdCIsIG11eF8yMDBtXzEwMG1fNTBtXzI0bV9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NP TigxMTgpLCAxMCwgMiwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNDkpLCAyLCBH RkxBR1MpLAo+ICsJQ09NUE9TSVRFKEFDTEtfSlBFR19ST09ULCAiYWNsa19qcGVnX3Jvb3QiLCBn cGxsX2NwbGxfYXVwbGxfc3BsbF9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxMTkpLCA1 LCAyLCBNRkxBR1MsIDAsIDUsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDQ5KSwg MywgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihBQ0xLX1ZQVV9MT1dfUk9PVCwgImFjbGtf dnB1X2xvd19yb290IiwgbXV4XzQwMG1fMjAwbV8xMDBtXzI0bV9wLCAwLAo+ICsJCQlSSzM1NzZf Q0xLU0VMX0NPTigxMTkpLCA3LCAyLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig0 OSksIDQsIEdGTEFHUyksCj4gKwlHQVRFKEhDTEtfUkdBMkVfMCwgImhjbGtfcmdhMmVfMCIsICJo Y2xrX3ZwdV9yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDQ5KSwgMTMsIEdGTEFH UyksCj4gKwlHQVRFKEFDTEtfUkdBMkVfMCwgImFjbGtfcmdhMmVfMCIsICJhY2xrX3ZwdV9yb290 IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDQ5KSwgMTQsIEdGTEFHUyksCj4gKwlDT01Q T1NJVEUoQ0xLX0NPUkVfUkdBMkVfMCwgImNsa19jb3JlX3JnYTJlXzAiLCBncGxsX3NwbGxfY3Bs bF9icGxsX2xwbGxfcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oMTIwKSwgNSwgMywgTUZM QUdTLCAwLCA1LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig0OSksIDE1LCBHRkxB R1MpLAo+ICsJR0FURShBQ0xLX0pQRUcsICJhY2xrX2pwZWciLCAiYWNsa19qcGVnX3Jvb3QiLCAw LAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNTApLCAwLCBHRkxBR1MpLAo+ICsJR0FURShIQ0xL X0pQRUcsICJoY2xrX2pwZWciLCAiaGNsa192cHVfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtH QVRFX0NPTig1MCksIDEsIEdGTEFHUyksCj4gKwlHQVRFKEhDTEtfVkRQUCwgImhjbGtfdmRwcCIs ICJoY2xrX3ZwdV9yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDUwKSwgMiwgR0ZM QUdTKSwKPiArCUdBVEUoQUNMS19WRFBQLCAiYWNsa192ZHBwIiwgImFjbGtfdnB1X21pZF9yb290 IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDUwKSwgMywgR0ZMQUdTKSwKPiArCUNPTVBP U0lURShDTEtfQ09SRV9WRFBQLCAiY2xrX2NvcmVfdmRwcCIsIGdwbGxfY3BsbF9wLCAwLAo+ICsJ CQlSSzM1NzZfQ0xLU0VMX0NPTigxMjApLCAxMywgMSwgTUZMQUdTLCA4LCA1LCBERkxBR1MsCj4g KwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig1MCksIDQsIEdGTEFHUyksCj4gKwlHQVRFKEhDTEtfUkdB MkVfMSwgImhjbGtfcmdhMmVfMSIsICJoY2xrX3ZwdV9yb290IiwgMCwKPiArCQkJUkszNTc2X0NM S0dBVEVfQ09OKDUwKSwgNSwgR0ZMQUdTKSwKPiArCUdBVEUoQUNMS19SR0EyRV8xLCAiYWNsa19y Z2EyZV8xIiwgImFjbGtfdnB1X3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNTAp LCA2LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKENMS19DT1JFX1JHQTJFXzEsICJjbGtfY29yZV9y Z2EyZV8xIiwgZ3BsbF9zcGxsX2NwbGxfYnBsbF9scGxsX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtT RUxfQ09OKDEyMSksIDUsIDMsIE1GTEFHUywgMCwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xL R0FURV9DT04oNTApLCA3LCBHRkxBR1MpLAo+ICsJTVVYKDAsICJkY2xrX2ViY19mcmFjX3NyY19w IiwgZ3BsbF9jcGxsX3ZwbGxfYXVwbGxfMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09O KDEyMyksIDAsIDMsIE1GTEFHUyksCj4gKwlDT01QT1NJVEVfRlJBQyhEQ0xLX0VCQ19GUkFDX1NS QywgImRjbGtfZWJjX2ZyYWNfc3JjIiwgImRjbGtfZWJjX2ZyYWNfc3JjX3AiLCAwLAo+ICsJCQlS SzM1NzZfQ0xLU0VMX0NPTigxMjIpLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNTApLCA5 LCBHRkxBR1MpLAo+ICsJR0FURShBQ0xLX0VCQywgImFjbGtfZWJjIiwgImFjbGtfdnB1X2xvd19y b290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDUwKSwgMTEsIEdGTEFHUyksCj4gKwlH QVRFKEhDTEtfRUJDLCAiaGNsa19lYmMiLCAiaGNsa192cHVfcm9vdCIsIDAsCj4gKwkJCVJLMzU3 Nl9DTEtHQVRFX0NPTig1MCksIDEwLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKERDTEtfRUJDLCAi ZGNsa19lYmMiLCBkY2xrX2ViY19wLCBDTEtfU0VUX1JBVEVfTk9fUkVQQVJFTlQsCj4gKwkJCVJL MzU3Nl9DTEtTRUxfQ09OKDEyMyksIDEyLCAzLCBNRkxBR1MsIDMsIDksIERGTEFHUywKPiArCQkJ UkszNTc2X0NMS0dBVEVfQ09OKDUwKSwgMTIsIEdGTEFHUyksCj4gKwo+ICsJLyogdmVwdSAqLwo+ ICsJQ09NUE9TSVRFX05PRElWKEhDTEtfVkVQVTFfUk9PVCwgImhjbGtfdmVwdTFfcm9vdCIsIG11 eF8yMDBtXzEwMG1fNTBtXzI0bV9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxNzgpLCAw LCAyLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig3OCksIDAsIEdGTEFHUyksCj4g KwlDT01QT1NJVEUoQUNMS19WRVBVMV9ST09ULCAiYWNsa192ZXB1MV9yb290IiwgZ3BsbF9jcGxs X3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDE4MCksIDUsIDEsIE1GTEFHUywgMCwgNSwg REZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNzkpLCAwLCBHRkxBR1MpLAo+ICsJR0FU RShIQ0xLX1ZFUFUxLCAiaGNsa192ZXB1MSIsICJoY2xrX3ZlcHUxX3Jvb3QiLCAwLAo+ICsJCQlS SzM1NzZfQ0xLR0FURV9DT04oNzkpLCAzLCBHRkxBR1MpLAo+ICsJR0FURShBQ0xLX1ZFUFUxLCAi YWNsa192ZXB1MSIsICJhY2xrX3ZlcHUxX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9D T04oNzkpLCA0LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKENMS19WRVBVMV9DT1JFLCAiY2xrX3Zl cHUxX2NvcmUiLCBncGxsX2NwbGxfc3BsbF9scGxsX2JwbGxfcCwgMCwKPiArCQkJUkszNTc2X0NM S1NFTF9DT04oMTgwKSwgMTEsIDMsIE1GTEFHUywgNiwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZf Q0xLR0FURV9DT04oNzkpLCA1LCBHRkxBR1MpLAo+ICsKPiArCS8qIHBocCAqLwo+ICsJQ09NUE9T SVRFX05PRElWKFBDTEtfUEhQX1JPT1QsICJwY2xrX3BocF9yb290IiwgbXV4XzEwMG1fNTBtXzI0 bV9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTig5MiksIDAsIDIsIE1GTEFHUywKPiArCQkJ UkszNTc2X0NMS0dBVEVfQ09OKDM0KSwgMCwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURShBQ0xLX1BI UF9ST09ULCAiYWNsa19waHBfcm9vdCIsIGdwbGxfY3BsbF9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xL U0VMX0NPTig5MiksIDksIDEsIE1GTEFHUywgNCwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xL R0FURV9DT04oMzQpLCA3LCBHRkxBR1MpLAo+ICsJR0FURShQQ0xLX1BDSUUwLCAicGNsa19wY2ll MCIsICJwY2xrX3BocF9yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDM0KSwgMTMs IEdGTEFHUyksCj4gKwlHQVRFKENMS19QQ0lFMF9BVVgsICJjbGtfcGNpZTBfYXV4IiwgInhpbjI0 bSIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigzNCksIDE0LCBHRkxBR1MpLAo+ICsJR0FU RShBQ0xLX1BDSUUwX01TVCwgImFjbGtfcGNpZTBfbXN0IiwgImFjbGtfcGhwX3Jvb3QiLCAwLAo+ ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMzQpLCAxNSwgR0ZMQUdTKSwKPiArCUdBVEUoQUNMS19Q Q0lFMF9TTFYsICJhY2xrX3BjaWUwX3NsdiIsICJhY2xrX3BocF9yb290IiwgMCwKPiArCQkJUksz NTc2X0NMS0dBVEVfQ09OKDM1KSwgMCwgR0ZMQUdTKSwKPiArCUdBVEUoQUNMS19QQ0lFMF9EQkks ICJhY2xrX3BjaWUwX2RiaSIsICJhY2xrX3BocF9yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dB VEVfQ09OKDM1KSwgMSwgR0ZMQUdTKSwKPiArCUdBVEUoQUNMS19VU0IzT1RHMSwgImFjbGtfdXNi M290ZzEiLCAiYWNsa19waHBfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigzNSks IDMsIEdGTEFHUyksCj4gKwlHQVRFKENMS19SRUZfVVNCM09URzEsICJjbGtfcmVmX3VzYjNvdGcx IiwgInhpbjI0bSIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigzNSksIDQsIEdGTEFHUyks Cj4gKwlHQVRFKENMS19TVVNQRU5EX1VTQjNPVEcxLCAiY2xrX3N1c3BlbmRfdXNiM290ZzEiLCAi eGluMjRtIiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDM1KSwgNSwgR0ZMQUdTKSwKPiAr CUdBVEUoQUNMS19NTVUwLCAiYWNsa19tbXUwIiwgImFjbGtfcGhwX3Jvb3QiLCAwLAo+ICsJCQlS SzM1NzZfQ0xLR0FURV9DT04oMzUpLCAxMSwgR0ZMQUdTKSwKPiArCUdBVEUoQUNMS19TTFZfTU1V MCwgImFjbGtfc2x2X21tdTAiLCAiYWNsa19waHBfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtH QVRFX0NPTigzNSksIDEzLCBHRkxBR1MpLAo+ICsJR0FURShBQ0xLX01NVTEsICJhY2xrX21tdTEi LCAiYWNsa19waHBfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigzNSksIDE0LCBH RkxBR1MpLAo+ICsJR0FURShBQ0xLX1NMVl9NTVUxLCAiYWNsa19zbHZfbW11MSIsICJhY2xrX3Bo cF9yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDM2KSwgMCwgR0ZMQUdTKSwKPiAr CUdBVEUoUENMS19QQ0lFMSwgInBjbGtfcGNpZTEiLCAicGNsa19waHBfcm9vdCIsIDAsCj4gKwkJ CVJLMzU3Nl9DTEtHQVRFX0NPTigzNiksIDcsIEdGTEFHUyksCj4gKwlHQVRFKENMS19QQ0lFMV9B VVgsICJjbGtfcGNpZTFfYXV4IiwgInhpbjI0bSIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NP TigzNiksIDgsIEdGTEFHUyksCj4gKwlHQVRFKEFDTEtfUENJRTFfTVNULCAiYWNsa19wY2llMV9t c3QiLCAiYWNsa19waHBfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigzNiksIDks IEdGTEFHUyksCj4gKwlHQVRFKEFDTEtfUENJRTFfU0xWLCAiYWNsa19wY2llMV9zbHYiLCAiYWNs a19waHBfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTigzNiksIDEwLCBHRkxBR1Mp LAo+ICsJR0FURShBQ0xLX1BDSUUxX0RCSSwgImFjbGtfcGNpZTFfZGJpIiwgImFjbGtfcGhwX3Jv b3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMzYpLCAxMSwgR0ZMQUdTKSwKPiArCUNP TVBPU0lURShDTEtfUlhPT0IwLCAiY2xrX3J4b29iMCIsIGdwbGxfY3BsbF9wLCAwLAo+ICsJCQlS SzM1NzZfQ0xLU0VMX0NPTig5MyksIDcsIDEsIE1GTEFHUywgMCwgNywgREZMQUdTLAo+ICsJCQlS SzM1NzZfQ0xLR0FURV9DT04oMzcpLCAwLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKENMS19SWE9P QjEsICJjbGtfcnhvb2IxIiwgZ3BsbF9jcGxsX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09O KDkzKSwgMTUsIDEsIE1GTEFHUywgOCwgNywgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9D T04oMzcpLCAxLCBHRkxBR1MpLAo+ICsJR0FURShDTEtfUE1BTElWRTAsICJjbGtfcG1hbGl2ZTAi LCAieGluMjRtIiwgQ0xLX0lTX0NSSVRJQ0FMLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMzcp LCAyLCBHRkxBR1MpLAo+ICsJR0FURShDTEtfUE1BTElWRTEsICJjbGtfcG1hbGl2ZTEiLCAieGlu MjRtIiwgQ0xLX0lTX0NSSVRJQ0FMLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oMzcpLCAzLCBH RkxBR1MpLAo+ICsJR0FURShBQ0xLX1NBVEEwLCAiYWNsa19zYXRhMCIsICJhY2xrX3BocF9yb290 IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDM3KSwgNCwgR0ZMQUdTKSwKPiArCUdBVEUo QUNMS19TQVRBMSwgImFjbGtfc2F0YTEiLCAiYWNsa19waHBfcm9vdCIsIDAsCj4gKwkJCVJLMzU3 Nl9DTEtHQVRFX0NPTigzNyksIDUsIEdGTEFHUyksCj4gKwo+ICsJLyogYXVkaW8gKi8KPiArCUNP TVBPU0lURV9OT0RJVihIQ0xLX0FVRElPX1JPT1QsICJoY2xrX2F1ZGlvX3Jvb3QiLCBtdXhfMjAw bV8xMDBtXzUwbV8yNG1fcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oNDIpLCAwLCAyLCBN RkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig3KSwgMSwgR0ZMQUdTKSwKPiArCUdBVEUo SENMS19BU1JDXzJDSF8wLCAiaGNsa19hc3JjXzJjaF8wIiwgImhjbGtfYXVkaW9fcm9vdCIsIDAs Cj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig3KSwgMywgR0ZMQUdTKSwKPiArCUdBVEUoSENMS19B U1JDXzJDSF8xLCAiaGNsa19hc3JjXzJjaF8xIiwgImhjbGtfYXVkaW9fcm9vdCIsIDAsCj4gKwkJ CVJLMzU3Nl9DTEtHQVRFX0NPTig3KSwgNCwgR0ZMQUdTKSwKPiArCUdBVEUoSENMS19BU1JDXzRD SF8wLCAiaGNsa19hc3JjXzRjaF8wIiwgImhjbGtfYXVkaW9fcm9vdCIsIDAsCj4gKwkJCVJLMzU3 Nl9DTEtHQVRFX0NPTig3KSwgNSwgR0ZMQUdTKSwKPiArCUdBVEUoSENMS19BU1JDXzRDSF8xLCAi aGNsa19hc3JjXzRjaF8xIiwgImhjbGtfYXVkaW9fcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtH QVRFX0NPTig3KSwgNiwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURShDTEtfQVNSQ18yQ0hfMCwgImNs a19hc3JjXzJjaF8wIiwgZ3BsbF9jcGxsX2F1cGxsX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxf Q09OKDQyKSwgNywgMiwgTUZMQUdTLCAyLCA1LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRF X0NPTig3KSwgNywgR0ZMQUdTKSwKPiArCUNPTVBPU0lURShDTEtfQVNSQ18yQ0hfMSwgImNsa19h c3JjXzJjaF8xIiwgZ3BsbF9jcGxsX2F1cGxsX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09O KDQyKSwgMTQsIDIsIE1GTEFHUywgOSwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9D T04oNyksIDgsIEdGTEFHUyksCj4gKwlDT01QT1NJVEUoQ0xLX0FTUkNfNENIXzAsICJjbGtfYXNy Y180Y2hfMCIsIGdwbGxfY3BsbF9hdXBsbF9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTig0 MyksIDUsIDIsIE1GTEFHUywgMCwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04o NyksIDksIEdGTEFHUyksCj4gKwlDT01QT1NJVEUoQ0xLX0FTUkNfNENIXzEsICJjbGtfYXNyY180 Y2hfMSIsIGdwbGxfY3BsbF9hdXBsbF9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTig0Myks IDEyLCAyLCBNRkxBR1MsIDcsIDUsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDcp LCAxMCwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURShNQ0xLX1NBSTBfOENIX1NSQywgIm1jbGtfc2Fp MF84Y2hfc3JjIiwgYXVkaW9fZnJhY19pbnRfcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04o NDQpLCA4LCAzLCBNRkxBR1MsIDAsIDgsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09O KDcpLCAxMSwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihNQ0xLX1NBSTBfOENILCAibWNs a19zYWkwXzhjaCIsIG1jbGtfc2FpMF84Y2hfcCwgQ0xLX1NFVF9SQVRFX1BBUkVOVCwKPiArCQkJ UkszNTc2X0NMS1NFTF9DT04oNDQpLCAxMSwgMiwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FU RV9DT04oNyksIDEyLCBHRkxBR1MpLAo+ICsJR0FURShIQ0xLX1NBSTBfOENILCAiaGNsa19zYWkw XzhjaCIsICJoY2xrX2F1ZGlvX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNyks IDEzLCBHRkxBR1MpLAo+ICsJR0FURShIQ0xLX1NQRElGX1JYMCwgImhjbGtfc3BkaWZfcngwIiwg ImhjbGtfYXVkaW9fcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig3KSwgMTQsIEdG TEFHUyksCj4gKwlDT01QT1NJVEUoTUNMS19TUERJRl9SWDAsICJtY2xrX3NwZGlmX3J4MCIsIGdw bGxfY3BsbF9hdXBsbF9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTig0NSksIDUsIDIsIE1G TEFHUywgMCwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNyksIDE1LCBHRkxB R1MpLAo+ICsJR0FURShIQ0xLX1NQRElGX1JYMSwgImhjbGtfc3BkaWZfcngxIiwgImhjbGtfYXVk aW9fcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig4KSwgMCwgR0ZMQUdTKSwKPiAr CUNPTVBPU0lURShNQ0xLX1NQRElGX1JYMSwgIm1jbGtfc3BkaWZfcngxIiwgZ3BsbF9jcGxsX2F1 cGxsX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDQ1KSwgMTIsIDIsIE1GTEFHUywgNywg NSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oOCksIDEsIEdGTEFHUyksCj4gKwlD T01QT1NJVEUoTUNMS19TQUkxXzhDSF9TUkMsICJtY2xrX3NhaTFfOGNoX3NyYyIsIGF1ZGlvX2Zy YWNfaW50X3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDQ2KSwgOCwgMywgTUZMQUdTLCAw LCA4LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig4KSwgNCwgR0ZMQUdTKSwKPiAr CUNPTVBPU0lURV9OT0RJVihNQ0xLX1NBSTFfOENILCAibWNsa19zYWkxXzhjaCIsIG1jbGtfc2Fp MV84Y2hfcCwgQ0xLX1NFVF9SQVRFX1BBUkVOVCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oNDYp LCAxMSwgMSwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oOCksIDUsIEdGTEFHUyks Cj4gKwlHQVRFKEhDTEtfU0FJMV84Q0gsICJoY2xrX3NhaTFfOGNoIiwgImhjbGtfYXVkaW9fcm9v dCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig4KSwgNiwgR0ZMQUdTKSwKPiArCUNPTVBP U0lURShNQ0xLX1NBSTJfMkNIX1NSQywgIm1jbGtfc2FpMl8yY2hfc3JjIiwgYXVkaW9fZnJhY19p bnRfcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oNDcpLCA4LCAzLCBNRkxBR1MsIDAsIDgs IERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDgpLCA3LCBHRkxBR1MpLAo+ICsJQ09N UE9TSVRFX05PRElWKE1DTEtfU0FJMl8yQ0gsICJtY2xrX3NhaTJfMmNoIiwgbWNsa19zYWkyXzJj aF9wLCBDTEtfU0VUX1JBVEVfUEFSRU5ULAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTig0NyksIDEx LCAyLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig4KSwgOCwgR0ZMQUdTKSwKPiAr CUdBVEUoSENMS19TQUkyXzJDSCwgImhjbGtfc2FpMl8yY2giLCAiaGNsa19hdWRpb19yb290Iiwg MCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDgpLCAxMCwgR0ZMQUdTKSwKPiArCUNPTVBPU0lU RShNQ0xLX1NBSTNfMkNIX1NSQywgIm1jbGtfc2FpM18yY2hfc3JjIiwgYXVkaW9fZnJhY19pbnRf cCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oNDgpLCA4LCAzLCBNRkxBR1MsIDAsIDgsIERG TEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDgpLCAxMSwgR0ZMQUdTKSwKPiArCUNPTVBP U0lURV9OT0RJVihNQ0xLX1NBSTNfMkNILCAibWNsa19zYWkzXzJjaCIsIG1jbGtfc2FpM18yY2hf cCwgQ0xLX1NFVF9SQVRFX1BBUkVOVCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oNDgpLCAxMSwg MiwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oOCksIDEyLCBHRkxBR1MpLAo+ICsJ R0FURShIQ0xLX1NBSTNfMkNILCAiaGNsa19zYWkzXzJjaCIsICJoY2xrX2F1ZGlvX3Jvb3QiLCAw LAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oOCksIDE0LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRF KE1DTEtfU0FJNF8yQ0hfU1JDLCAibWNsa19zYWk0XzJjaF9zcmMiLCBhdWRpb19mcmFjX2ludF9w LCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTig0OSksIDgsIDMsIE1GTEFHUywgMCwgOCwgREZM QUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oOCksIDE1LCBHRkxBR1MpLAo+ICsJQ09NUE9T SVRFX05PRElWKE1DTEtfU0FJNF8yQ0gsICJtY2xrX3NhaTRfMmNoIiwgbWNsa19zYWk0XzJjaF9w LCBDTEtfU0VUX1JBVEVfUEFSRU5ULAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTig0OSksIDExLCAy LCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig5KSwgMCwgR0ZMQUdTKSwKPiArCUdB VEUoSENMS19TQUk0XzJDSCwgImhjbGtfc2FpNF8yY2giLCAiaGNsa19hdWRpb19yb290IiwgMCwK PiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDkpLCAyLCBHRkxBR1MpLAo+ICsJR0FURShIQ0xLX0FD RENESUdfRFNNLCAiaGNsa19hY2RjZGlnX2RzbSIsICJoY2xrX2F1ZGlvX3Jvb3QiLCAwLAo+ICsJ CQlSSzM1NzZfQ0xLR0FURV9DT04oOSksIDMsIEdGTEFHUyksCj4gKwlHQVRFKE1DTEtfQUNEQ0RJ R19EU00sICJtY2xrX2FjZGNkaWdfZHNtIiwgIm1jbGtfc2FpNF8yY2giLCAwLAo+ICsJCQlSSzM1 NzZfQ0xLR0FURV9DT04oOSksIDQsIEdGTEFHUyksCj4gKwlDT01QT1NJVEUoQ0xLX1BETTEsICJj bGtfcGRtMSIsIGF1ZGlvX2ZyYWNfaW50X3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDUw KSwgOSwgMywgTUZMQUdTLCAwLCA5LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig5 KSwgNSwgR0ZMQUdTKSwKPiArCUdBVEUoSENMS19QRE0xLCAiaGNsa19wZG0xIiwgImhjbGtfYXVk aW9fcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig5KSwgNywgR0ZMQUdTKSwKPiAr CUdBVEUoQ0xLX1BETTFfT1VULCAiY2xrX3BkbTFfb3V0IiwgImNsa19wZG0xIiwgMCwKPiArCQkJ UkszNTc2X0NMS0dBVEVfQ09OKDMpLCA1LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKE1DTEtfUERN MSwgIm1jbGtfcGRtMSIsIGF1ZGlvX2ZyYWNfaW50X3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxf Q09OKDUxKSwgNSwgMywgTUZMQUdTLCAwLCA1LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRF X0NPTig5KSwgOCwgR0ZMQUdTKSwKPiArCUdBVEUoSENMS19TUERJRl9UWDAsICJoY2xrX3NwZGlm X3R4MCIsICJoY2xrX2F1ZGlvX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oOSks IDksIEdGTEFHUyksCj4gKwlDT01QT1NJVEUoTUNMS19TUERJRl9UWDAsICJtY2xrX3NwZGlmX3R4 MCIsIGF1ZGlvX2ZyYWNfaW50X3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDUyKSwgOCwg MywgTUZMQUdTLCAwLCA4LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig5KSwgMTAs IEdGTEFHUyksCj4gKwlHQVRFKEhDTEtfU1BESUZfVFgxLCAiaGNsa19zcGRpZl90eDEiLCAiaGNs a19hdWRpb19yb290IiwgMCwKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDkpLCAxMSwgR0ZMQUdT KSwKPiArCUNPTVBPU0lURShNQ0xLX1NQRElGX1RYMSwgIm1jbGtfc3BkaWZfdHgxIiwgYXVkaW9f ZnJhY19pbnRfcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oNTMpLCA4LCAzLCBNRkxBR1Ms IDAsIDgsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDkpLCAxMiwgR0ZMQUdTKSwK PiArCUdBVEUoQ0xLX1NBSTFfTUNMS09VVCwgImNsa19zYWkxX21jbGtvdXQiLCAibWNsa19zYWkx XzhjaCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig5KSwgMTMsIEdGTEFHUyksCj4gKwlH QVRFKENMS19TQUkyX01DTEtPVVQsICJjbGtfc2FpMl9tY2xrb3V0IiwgIm1jbGtfc2FpMl8yY2gi LCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oOSksIDE0LCBHRkxBR1MpLAo+ICsJR0FURShD TEtfU0FJM19NQ0xLT1VULCAiY2xrX3NhaTNfbWNsa291dCIsICJtY2xrX3NhaTNfMmNoIiwgMCwK PiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDkpLCAxNSwgR0ZMQUdTKSwKPiArCUdBVEUoQ0xLX1NB STRfTUNMS09VVCwgImNsa19zYWk0X21jbGtvdXQiLCAibWNsa19zYWk0XzJjaCIsIDAsCj4gKwkJ CVJLMzU3Nl9DTEtHQVRFX0NPTigxMCksIDAsIEdGTEFHUyksCj4gKwlHQVRFKENMS19TQUkwX01D TEtPVVQsICJjbGtfc2FpMF9tY2xrb3V0IiwgIm1jbGtfc2FpMF84Y2giLCAwLAo+ICsJCQlSSzM1 NzZfQ0xLR0FURV9DT04oMTApLCAxLCBHRkxBR1MpLAo+ICsKPiArCS8qIHNkZ21hYyAqLwo+ICsJ Q09NUE9TSVRFX05PRElWKEhDTEtfU0RHTUFDX1JPT1QsICJoY2xrX3NkZ21hY19yb290IiwgbXV4 XzIwMG1fMTAwbV81MG1fMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDEwMyksIDAs IDIsIE1GTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDQyKSwgMCwgR0ZMQUdTKSwKPiAr CUNPTVBPU0lURShBQ0xLX1NER01BQ19ST09ULCAiYWNsa19zZGdtYWNfcm9vdCIsIGdwbGxfY3Bs bF9wLCBDTEtfSVNfQ1JJVElDQUwsCj4gKwkJCVJLMzU3Nl9DTEtTRUxfQ09OKDEwMyksIDcsIDEs IE1GTEFHUywgMiwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNDIpLCAxLCBH RkxBR1MpLAo+ICsJQ09NUE9TSVRFX05PRElWKFBDTEtfU0RHTUFDX1JPT1QsICJwY2xrX3NkZ21h Y19yb290IiwgbXV4XzEwMG1fNTBtXzI0bV9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigx MDMpLCA4LCAyLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig0MiksIDIsIEdGTEFH UyksCj4gKwlHQVRFKEFDTEtfR01BQzAsICJhY2xrX2dtYWMwIiwgImFjbGtfc2RnbWFjX3Jvb3Qi LCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNDIpLCA3LCBHRkxBR1MpLAo+ICsJR0FURShB Q0xLX0dNQUMxLCAiYWNsa19nbWFjMSIsICJhY2xrX3NkZ21hY19yb290IiwgMCwKPiArCQkJUksz NTc2X0NMS0dBVEVfQ09OKDQyKSwgOCwgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19HTUFDMCwgInBj bGtfZ21hYzAiLCAicGNsa19zZGdtYWNfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NP Tig0MiksIDksIEdGTEFHUyksCj4gKwlHQVRFKFBDTEtfR01BQzEsICJwY2xrX2dtYWMxIiwgInBj bGtfc2RnbWFjX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNDIpLCAxMCwgR0ZM QUdTKSwKPiArCUNPTVBPU0lURShDQ0xLX1NSQ19TRElPLCAiY2Nsa19zcmNfc2RpbyIsIGdwbGxf Y3BsbF8yNG1fcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9DT04oMTA0KSwgNiwgMiwgTUZMQUdT LCAwLCA2LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig0MiksIDExLCBHRkxBR1Mp LAo+ICsJR0FURShIQ0xLX1NESU8sICJoY2xrX3NkaW8iLCAiaGNsa19zZGdtYWNfcm9vdCIsIDAs Cj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig0MiksIDEyLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRF KENMS19HTUFDMV9QVFBfUkVGX1NSQywgImNsa19nbWFjMV9wdHBfcmVmX3NyYyIsIGNsa19nbWFj MV9wdHBfcmVmX3NyY19wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxMDQpLCAxMywgMiwg TUZMQUdTLCA4LCA1LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig0MiksIDE1LCBH RkxBR1MpLAo+ICsJQ09NUE9TSVRFKENMS19HTUFDMF9QVFBfUkVGX1NSQywgImNsa19nbWFjMF9w dHBfcmVmX3NyYyIsIGNsa19nbWFjMF9wdHBfcmVmX3NyY19wLCAwLAo+ICsJCQlSSzM1NzZfQ0xL U0VMX0NPTigxMDUpLCA1LCAyLCBNRkxBR1MsIDAsIDUsIERGTEFHUywKPiArCQkJUkszNTc2X0NM S0dBVEVfQ09OKDQzKSwgMCwgR0ZMQUdTKSwKPiArCUdBVEUoQ0xLX0dNQUMxX1BUUF9SRUYsICJj bGtfZ21hYzFfcHRwX3JlZiIsICJjbGtfZ21hYzFfcHRwX3JlZl9zcmMiLCAwLAo+ICsJCQlSSzM1 NzZfQ0xLR0FURV9DT04oNDIpLCAxMywgR0ZMQUdTKSwKPiArCUdBVEUoQ0xLX0dNQUMwX1BUUF9S RUYsICJjbGtfZ21hYzBfcHRwX3JlZiIsICJjbGtfZ21hYzBfcHRwX3JlZl9zcmMiLCAwLAo+ICsJ CQlSSzM1NzZfQ0xLR0FURV9DT04oNDIpLCAxNCwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURShDQ0xL X1NSQ19TRE1NQzAsICJjY2xrX3NyY19zZG1tYzAiLCBncGxsX2NwbGxfMjRtX3AsIDAsCj4gKwkJ CVJLMzU3Nl9DTEtTRUxfQ09OKDEwNSksIDEzLCAyLCBNRkxBR1MsIDcsIDYsIERGTEFHUywKPiAr CQkJUkszNTc2X0NMS0dBVEVfQ09OKDQzKSwgMSwgR0ZMQUdTKSwKPiArCUdBVEUoSENMS19TRE1N QzAsICJoY2xrX3NkbW1jMCIsICJoY2xrX3NkZ21hY19yb290IiwgMCwKPiArCQkJUkszNTc2X0NM S0dBVEVfQ09OKDQzKSwgMiwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURShTQ0xLX0ZTUEkxX1gyLCAi c2Nsa19mc3BpMV94MiIsIGdwbGxfY3BsbF8yNG1fcCwgMCwKPiArCQkJUkszNTc2X0NMS1NFTF9D T04oMTA2KSwgNiwgMiwgTUZMQUdTLCAwLCA2LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRF X0NPTig0MyksIDMsIEdGTEFHUyksCj4gKwlHQVRFKEhDTEtfRlNQSTEsICJoY2xrX2ZzcGkxIiwg ImhjbGtfc2RnbWFjX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfQ0xLR0FURV9DT04oNDMpLCA0LCBH RkxBR1MpLAo+ICsJQ09NUE9TSVRFKEFDTEtfRFNNQ19ST09ULCAiYWNsa19kc21jX3Jvb3QiLCBn cGxsX2NwbGxfcCwgQ0xLX0lTX0NSSVRJQ0FMLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxMDYp LCAxMywgMSwgTUZMQUdTLCA4LCA1LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig0 MyksIDUsIEdGTEFHUyksCj4gKwlHQVRFKEFDTEtfRFNNQywgImFjbGtfZHNtYyIsICJhY2xrX2Rz bWNfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig0MyksIDcsIEdGTEFHUyksCj4g KwlHQVRFKFBDTEtfRFNNQywgInBjbGtfZHNtYyIsICJwY2xrX3NkZ21hY19yb290IiwgMCwKPiAr CQkJUkszNTc2X0NMS0dBVEVfQ09OKDQzKSwgOCwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURShDTEtf RFNNQ19TWVMsICJjbGtfZHNtY19zeXMiLCBncGxsX2NwbGxfcCwgMCwKPiArCQkJUkszNTc2X0NM S1NFTF9DT04oMTA3KSwgNSwgMSwgTUZMQUdTLCAwLCA1LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9D TEtHQVRFX0NPTig0MyksIDksIEdGTEFHUyksCj4gKwlHQVRFKEhDTEtfSFNHUElPLCAiaGNsa19o c2dwaW8iLCAiaGNsa19zZGdtYWNfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig0 MyksIDEwLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKENMS19IU0dQSU9fVFgsICJjbGtfaHNncGlv X3R4IiwgZ3BsbF9jcGxsXzI0bV9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxMDcpLCAx MSwgMiwgTUZMQUdTLCA2LCA1LCBERkxBR1MsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig0Myks IDExLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFKENMS19IU0dQSU9fUlgsICJjbGtfaHNncGlvX3J4 IiwgZ3BsbF9jcGxsXzI0bV9wLCAwLAo+ICsJCQlSSzM1NzZfQ0xLU0VMX0NPTigxMDgpLCA1LCAy LCBNRkxBR1MsIDAsIDUsIERGTEFHUywKPiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDQzKSwgMTIs IEdGTEFHUyksCj4gKwlHQVRFKEFDTEtfSFNHUElPLCAiYWNsa19oc2dwaW8iLCAiYWNsa19zZGdt YWNfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig0MyksIDEzLCBHRkxBR1MpLAo+ ICsKPiArCS8qIHBocHBoeSAqLwo+ICsJR0FURShQQ0xLX1BIUFBIWV9ST09ULCAicGNsa19waHBw aHlfcm9vdCIsICJwY2xrX2J1c19yb290IiwgQ0xLX0lTX0NSSVRJQ0FMLAo+ICsJCQlSSzM1NzZf UEhQX0NMS0dBVEVfQ09OKDApLCAyLCBHRkxBR1MpLAo+ICsJR0FURShQQ0xLX1BDSUUyX0NPTUJP UEhZMCwgInBjbGtfcGNpZTJfY29tYm9waHkwIiwgInBjbGtfcGhwcGh5X3Jvb3QiLCAwLAo+ICsJ CQlSSzM1NzZfUEhQX0NMS0dBVEVfQ09OKDApLCA1LCBHRkxBR1MpLAo+ICsJR0FURShQQ0xLX1BD SUUyX0NPTUJPUEhZMSwgInBjbGtfcGNpZTJfY29tYm9waHkxIiwgInBjbGtfcGhwcGh5X3Jvb3Qi LCAwLAo+ICsJCQlSSzM1NzZfUEhQX0NMS0dBVEVfQ09OKDApLCA3LCBHRkxBR1MpLAo+ICsJQ09N UE9TSVRFX05PTVVYKENMS19QQ0lFXzEwME1fU1JDLCAiY2xrX3BjaWVfMTAwbV9zcmMiLCAicHBs bCIsIDAsCj4gKwkJCVJLMzU3Nl9QSFBfQ0xLU0VMX0NPTigwKSwgMiwgNSwgREZMQUdTLAo+ICsJ CQlSSzM1NzZfUEhQX0NMS0dBVEVfQ09OKDEpLCAxLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFX05P TVVYKENMS19QQ0lFXzEwME1fTkRVVFlfU1JDLCAiY2xrX3BjaWVfMTAwbV9uZHV0eV9zcmMiLCAi cHBsbCIsIDAsCj4gKwkJCVJLMzU3Nl9QSFBfQ0xLU0VMX0NPTigwKSwgNywgNSwgREZMQUdTLAo+ ICsJCQlSSzM1NzZfUEhQX0NMS0dBVEVfQ09OKDEpLCAyLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRF X05PRElWKENMS19SRUZfUENJRTBfUEhZLCAiY2xrX3JlZl9wY2llMF9waHkiLCBjbGtfcmVmX3Bj aWUwX3BoeV9wLCAwLAo+ICsJCQlSSzM1NzZfUEhQX0NMS1NFTF9DT04oMCksIDEyLCAyLCBNRkxB R1MsCj4gKwkJCVJLMzU3Nl9QSFBfQ0xLR0FURV9DT04oMSksIDUsIEdGTEFHUyksCj4gKwlDT01Q T1NJVEVfTk9ESVYoQ0xLX1JFRl9QQ0lFMV9QSFksICJjbGtfcmVmX3BjaWUxX3BoeSIsIGNsa19y ZWZfcGNpZTBfcGh5X3AsIDAsCj4gKwkJCVJLMzU3Nl9QSFBfQ0xLU0VMX0NPTigwKSwgMTQsIDIs IE1GTEFHUywKPiArCQkJUkszNTc2X1BIUF9DTEtHQVRFX0NPTigxKSwgOCwgR0ZMQUdTKSwKPiAr CUNPTVBPU0lURV9OT01VWChDTEtfUkVGX01QSFlfMjZNLCAiY2xrX3JlZl9tcGh5XzI2bSIsICJw cGxsIiwgQ0xLX0lTX0NSSVRJQ0FMLAo+ICsJCQlSSzM1NzZfUEhQX0NMS1NFTF9DT04oMSksIDAs IDgsIERGTEFHUywKPiArCQkJUkszNTc2X1BIUF9DTEtHQVRFX0NPTigxKSwgOSwgR0ZMQUdTKSwK PiArCj4gKwkvKiBwbXUgKi8KPiArCUdBVEUoQ0xLXzIwME1fUE1VX1NSQywgImNsa18yMDBtX3Bt dV9zcmMiLCAiY2xrX2dwbGxfZGl2NiIsIDAsCj4gKwkJCVJLMzU3Nl9QTVVfQ0xLR0FURV9DT04o MyksIDIsIEdGTEFHUyksCj4gKwlDT01QT1NJVEVfTk9NVVgoQ0xLXzEwME1fUE1VX1NSQywgImNs a18xMDBtX3BtdV9zcmMiLCAiY3BsbCIsIDAsCj4gKwkJCVJLMzU3Nl9QTVVfQ0xLU0VMX0NPTig0 KSwgNCwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfUE1VX0NMS0dBVEVfQ09OKDMpLCAzLCBHRkxB R1MpLAo+ICsJRkFDVE9SX0dBVEUoQ0xLXzUwTV9QTVVfU1JDLCAiY2xrXzUwbV9wbXVfc3JjIiwg ImNsa18xMDBtX3BtdV9zcmMiLCAwLCAxLCAyLAo+ICsJCQlSSzM1NzZfUE1VX0NMS0dBVEVfQ09O KDMpLCA0LCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFX05PRElWKEhDTEtfUE1VMV9ST09ULCAiaGNs a19wbXUxX3Jvb3QiLCBtdXhfcG11MjAwbV9wbXUxMDBtX3BtdTUwbV8yNG1fcCwgQ0xLX0lTX0NS SVRJQ0FMLAo+ICsJCQlSSzM1NzZfUE1VX0NMS1NFTF9DT04oNCksIDAsIDIsIE1GTEFHUywKPiAr CQkJUkszNTc2X1BNVV9DTEtHQVRFX0NPTigzKSwgMCwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9O T0RJVihIQ0xLX1BNVV9DTTBfUk9PVCwgImhjbGtfcG11X2NtMF9yb290IiwgbXV4X3BtdTIwMG1f cG11MTAwbV9wbXU1MG1fMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9QTVVfQ0xLU0VMX0NPTig0KSwg MiwgMiwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfUE1VX0NMS0dBVEVfQ09OKDMpLCAxLCBHRkxBR1Mp LAo+ICsJQ09NUE9TSVRFX05PRElWKFBDTEtfUE1VMF9ST09ULCAicGNsa19wbXUwX3Jvb3QiLCBt dXhfcG11MTAwbV9wbXU1MG1fMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9QTVVfQ0xLU0VMX0NPTigy MCksIDAsIDIsIE1GTEFHUywKPiArCQkJUkszNTc2X1BNVV9DTEtHQVRFX0NPTig3KSwgMCwgR0ZM QUdTKSwKPiArCUdBVEUoUENMS19QTVUwLCAicGNsa19wbXUwIiwgInBjbGtfcG11MF9yb290Iiwg Q0xLX0lTX0NSSVRJQ0FMLAo+ICsJCQlSSzM1NzZfUE1VX0NMS0dBVEVfQ09OKDcpLCAzLCBHRkxB R1MpLAo+ICsJR0FURShQQ0xLX1BNVTFfUk9PVCwgInBjbGtfcG11MV9yb290IiwgInBjbGtfcG11 MF9yb290IiwgQ0xLX0lTX0NSSVRJQ0FMLAo+ICsJCQlSSzM1NzZfUE1VX0NMS0dBVEVfQ09OKDcp LCA5LCBHRkxBR1MpLAo+ICsJR0FURShQQ0xLX1BNVTEsICJwY2xrX3BtdTEiLCAicGNsa19wbXUx X3Jvb3QiLCBDTEtfSVNfQ1JJVElDQUwsCj4gKwkJCVJLMzU3Nl9QTVVfQ0xLR0FURV9DT04oMyks IDE1LCBHRkxBR1MpLAo+ICsJR0FURShDTEtfUE1VMSwgImNsa19wbXUxIiwgInhpbjI0bSIsIENM S19JU19DUklUSUNBTCwKPiArCQkJUkszNTc2X1BNVV9DTEtHQVRFX0NPTig0KSwgMiwgR0ZMQUdT KSwKPiArCUdBVEUoUENMS19QTVVQSFlfUk9PVCwgInBjbGtfcG11cGh5X3Jvb3QiLCAicGNsa19w bXUxX3Jvb3QiLCBDTEtfSVNfQ1JJVElDQUwsCj4gKwkJCVJLMzU3Nl9QTVVfQ0xLR0FURV9DT04o NSksIDAsIEdGTEFHUyksCj4gKwlHQVRFKFBDTEtfSERQVFhfQVBCLCAicGNsa19oZHB0eF9hcGIi LCAicGNsa19wbXVwaHlfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9QTVVfQ0xLR0FURV9DT04oMCks IDEsIEdGTEFHUyksCj4gKwlHQVRFKFBDTEtfTUlQSV9EQ1BIWSwgInBjbGtfbWlwaV9kY3BoeSIs ICJwY2xrX3BtdXBoeV9yb290IiwgMCwKPiArCQkJUkszNTc2X1BNVV9DTEtHQVRFX0NPTigwKSwg MiwgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19DU0lEUEhZLCAicGNsa19jc2lkcGh5IiwgInBjbGtf cG11cGh5X3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfUE1VX0NMS0dBVEVfQ09OKDApLCA4LCBHRkxB R1MpLAo+ICsJR0FURShQQ0xLX1VTQkRQUEhZLCAicGNsa191c2JkcHBoeSIsICJwY2xrX3BtdXBo eV9yb290IiwgMCwKPiArCQkJUkszNTc2X1BNVV9DTEtHQVRFX0NPTigwKSwgMTIsIEdGTEFHUyks Cj4gKwlDT01QT1NJVEVfTk9NVVgoQ0xLX1BNVVBIWV9SRUZfU1JDLCAiY2xrX3BtdXBoeV9yZWZf c3JjIiwgImNwbGwiLCAwLAo+ICsJCQlSSzM1NzZfUE1VX0NMS1NFTF9DT04oMCksIDAsIDUsIERG TEFHUywKPiArCQkJUkszNTc2X1BNVV9DTEtHQVRFX0NPTigwKSwgMTMsIEdGTEFHUyksCj4gKwlH QVRFKENMS19VU0JEUF9DT01CT19QSFlfSU1NT1JUQUwsICJjbGtfdXNiZHBfY29tYm9fcGh5X2lt bW9ydGFsIiwgInhpbjI0bSIsIDAsCj4gKwkJCVJLMzU3Nl9QTVVfQ0xLR0FURV9DT04oMCksIDE1 LCBHRkxBR1MpLAo+ICsJR0FURShDTEtfSERNSVRYSFBELCAiY2xrX2hkbWl0eGhwZCIsICJ4aW4y NG0iLCAwLAo+ICsJCQlSSzM1NzZfUE1VX0NMS0dBVEVfQ09OKDEpLCAxMywgR0ZMQUdTKSwKPiAr CUdBVEUoUENMS19NUEhZLCAicGNsa19tcGh5IiwgInBjbGtfcG11cGh5X3Jvb3QiLCAwLAo+ICsJ CQlSSzM1NzZfUE1VX0NMS0dBVEVfQ09OKDIpLCAwLCBHRkxBR1MpLAo+ICsJTVVYKENMS19SRUZf T1NDX01QSFksICJjbGtfcmVmX29zY19tcGh5IiwgY2xrX3JlZl9vc2NfbXBoeV9wLCAwLAo+ICsJ CQlSSzM1NzZfUE1VX0NMS1NFTF9DT04oMyksIDAsIDIsIE1GTEFHUyksCj4gKwlHQVRFKENMS19S RUZfVUZTX0NMS09VVCwgImNsa19yZWZfdWZzX2Nsa291dCIsICJjbGtfcmVmX29zY19tcGh5Iiwg MCwKPiArCQkJUkszNTc2X1BNVV9DTEtHQVRFX0NPTigyKSwgNSwgR0ZMQUdTKSwKPiArCUdBVEUo RkNMS19QTVVfQ00wX0NPUkUsICJmY2xrX3BtdV9jbTBfY29yZSIsICJoY2xrX3BtdV9jbTBfcm9v dCIsIDAsCj4gKwkJCVJLMzU3Nl9QTVVfQ0xLR0FURV9DT04oMyksIDEyLCBHRkxBR1MpLAo+ICsJ Q09NUE9TSVRFKENMS19QTVVfQ00wX1JUQywgImNsa19wbXVfY20wX3J0YyIsIG11eF8yNG1fMzJr X3AsIDAsCj4gKwkJCVJLMzU3Nl9QTVVfQ0xLU0VMX0NPTig0KSwgMTQsIDEsIE1GTEFHUywgOSwg NSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfUE1VX0NMS0dBVEVfQ09OKDMpLCAxNCwgR0ZMQUdTKSwK PiArCUdBVEUoUENMS19QTVUxV0RULCAicGNsa19wbXUxd2R0IiwgInBjbGtfcG11MV9yb290Iiwg MCwKPiArCQkJUkszNTc2X1BNVV9DTEtHQVRFX0NPTig0KSwgNSwgR0ZMQUdTKSwKPiArCUNPTVBP U0lURV9OT0RJVihUQ0xLX1BNVTFXRFQsICJ0Y2xrX3BtdTF3ZHQiLCBtdXhfMjRtXzMya19wLCAw LAo+ICsJCQlSSzM1NzZfUE1VX0NMS1NFTF9DT04oNCksIDE1LCAxLCBNRkxBR1MsCj4gKwkJCVJL MzU3Nl9QTVVfQ0xLR0FURV9DT04oNCksIDYsIEdGTEFHUyksCj4gKwlHQVRFKFBDTEtfUE1VVElN RVIsICJwY2xrX3BtdXRpbWVyIiwgInBjbGtfcG11MV9yb290IiwgMCwKPiArCQkJUkszNTc2X1BN VV9DTEtHQVRFX0NPTig0KSwgNywgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihDTEtfUE1V VElNRVJfUk9PVCwgImNsa19wbXV0aW1lcl9yb290IiwgbXV4X3BtdTEwMG1fMjRtXzMya19wLCAw LAo+ICsJCQlSSzM1NzZfUE1VX0NMS1NFTF9DT04oNSksIDAsIDIsIE1GTEFHUywKPiArCQkJUksz NTc2X1BNVV9DTEtHQVRFX0NPTig0KSwgOCwgR0ZMQUdTKSwKPiArCUdBVEUoQ0xLX1BNVVRJTUVS MCwgImNsa19wbXV0aW1lcjAiLCAiY2xrX3BtdXRpbWVyX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZf UE1VX0NMS0dBVEVfQ09OKDQpLCA5LCBHRkxBR1MpLAo+ICsJR0FURShDTEtfUE1VVElNRVIxLCAi Y2xrX3BtdXRpbWVyMSIsICJjbGtfcG11dGltZXJfcm9vdCIsIDAsCj4gKwkJCVJLMzU3Nl9QTVVf Q0xLR0FURV9DT04oNCksIDEwLCBHRkxBR1MpLAo+ICsJR0FURShQQ0xLX1BNVTFQV00sICJwY2xr X3BtdTFwd20iLCAicGNsa19wbXUxX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfUE1VX0NMS0dBVEVf Q09OKDQpLCAxMSwgR0ZMQUdTKSwKPiArCUNPTVBPU0lURV9OT0RJVihDTEtfUE1VMVBXTSwgImNs a19wbXUxcHdtIiwgbXV4X3BtdTEwMG1fcG11NTBtXzI0bV9wLCAwLAo+ICsJCQlSSzM1NzZfUE1V X0NMS1NFTF9DT04oNSksIDIsIDIsIE1GTEFHUywKPiArCQkJUkszNTc2X1BNVV9DTEtHQVRFX0NP Tig0KSwgMTIsIEdGTEFHUyksCj4gKwlHQVRFKENMS19QTVUxUFdNX09TQywgImNsa19wbXUxcHdt X29zYyIsICJ4aW4yNG0iLCAwLAo+ICsJCQlSSzM1NzZfUE1VX0NMS0dBVEVfQ09OKDQpLCAxMywg R0ZMQUdTKSwKPiArCUdBVEUoUENMS19JMkMwLCAicGNsa19pMmMwIiwgInBjbGtfcG11MV9yb290 IiwgMCwKPiArCQkJUkszNTc2X1BNVV9DTEtHQVRFX0NPTig1KSwgMSwgR0ZMQUdTKSwKPiArCUNP TVBPU0lURV9OT0RJVihDTEtfSTJDMCwgImNsa19pMmMwIiwgbXV4X3BtdTIwMG1fcG11MTAwbV9w bXU1MG1fMjRtX3AsIDAsCj4gKwkJCVJLMzU3Nl9QTVVfQ0xLU0VMX0NPTig2KSwgNywgMiwgTUZM QUdTLAo+ICsJCQlSSzM1NzZfUE1VX0NMS0dBVEVfQ09OKDUpLCAyLCBHRkxBR1MpLAo+ICsJQ09N UE9TSVRFX05PRElWKFNDTEtfVUFSVDEsICJzY2xrX3VhcnQxIiwgdWFydDFfcCwgMCwKPiArCQkJ UkszNTc2X1BNVV9DTEtTRUxfQ09OKDgpLCAwLCAxLCBNRkxBR1MsCj4gKwkJCVJLMzU3Nl9QTVVf Q0xLR0FURV9DT04oNSksIDUsIEdGTEFHUyksCj4gKwlHQVRFKFBDTEtfVUFSVDEsICJwY2xrX3Vh cnQxIiwgInBjbGtfcG11MV9yb290IiwgMCwKPiArCQkJUkszNTc2X1BNVV9DTEtHQVRFX0NPTig1 KSwgNiwgR0ZMQUdTKSwKPiArCUdBVEUoQ0xLX1BETTAsICJjbGtfcGRtMCIsICJjbGtfcGRtMF9z cmNfdG9wIiwgMCwKPiArCQkJUkszNTc2X1BNVV9DTEtHQVRFX0NPTig1KSwgMTMsIEdGTEFHUyks Cj4gKwlHQVRFKEhDTEtfUERNMCwgImhjbGtfcGRtMCIsICJoY2xrX3BtdTFfcm9vdCIsIDAsCj4g KwkJCVJLMzU3Nl9QTVVfQ0xLR0FURV9DT04oNSksIDE1LCBHRkxBR1MpLAo+ICsJR0FURShNQ0xL X1BETTAsICJtY2xrX3BkbTAiLCAibWNsa19wZG0wX3NyY190b3AiLCAwLAo+ICsJCQlSSzM1NzZf UE1VX0NMS0dBVEVfQ09OKDYpLCAwLCBHRkxBR1MpLAo+ICsJR0FURShIQ0xLX1ZBRCwgImhjbGtf dmFkIiwgImhjbGtfcG11MV9yb290IiwgMCwKPiArCQkJUkszNTc2X1BNVV9DTEtHQVRFX0NPTig2 KSwgMSwgR0ZMQUdTKSwKPiArCUdBVEUoQ0xLX1BETTBfT1VULCAiY2xrX3BkbTBfb3V0IiwgImNs a19wZG0wIiwgMCwKPiArCQkJUkszNTc2X1BNVV9DTEtHQVRFX0NPTig2KSwgOCwgR0ZMQUdTKSwK PiArCUNPTVBPU0lURShDTEtfSFBUSU1FUl9TUkMsICJjbGtfaHB0aW1lcl9zcmMiLCBjcGxsXzI0 bV9wLCBDTEtfSVNfQ1JJVElDQUwsCj4gKwkJCVJLMzU3Nl9QTVVfQ0xLU0VMX0NPTigxMSksIDYs IDEsIE1GTEFHUywgMSwgNSwgREZMQUdTLAo+ICsJCQlSSzM1NzZfUE1VX0NMS0dBVEVfQ09OKDYp LCAxMCwgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19HUElPMCwgInBjbGtfZ3BpbzAiLCAicGNsa19w bXUwX3Jvb3QiLCAwLAo+ICsJCQlSSzM1NzZfUE1VX0NMS0dBVEVfQ09OKDcpLCA2LCBHRkxBR1Mp LAo+ICsJQ09NUE9TSVRFX05PRElWKERCQ0xLX0dQSU8wLCAiZGJjbGtfZ3BpbzAiLCBtdXhfMjRt XzMya19wLCAwLAo+ICsJCQlSSzM1NzZfUE1VX0NMS1NFTF9DT04oMjApLCAyLCAxLCBNRkxBR1Ms Cj4gKwkJCVJLMzU3Nl9QTVVfQ0xLR0FURV9DT04oNyksIDcsIEdGTEFHUyksCj4gKwlHQVRFKENM S19PU0MwX1BNVTEsICJjbGtfb3NjMF9wbXUxIiwgInhpbjI0bSIsIENMS19JU19DUklUSUNBTCwK PiArCQkJUkszNTc2X1BNVV9DTEtHQVRFX0NPTig3KSwgOCwgR0ZMQUdTKSwKPiArCUdBVEUoQ0xL X1BNVTFQV01fUkMsICJjbGtfcG11MXB3bV9yYyIsICJjbGtfcHZ0bV9jbGtvdXQiLCAwLAo+ICsJ CQlSSzM1NzZfUE1VX0NMS0dBVEVfQ09OKDUpLCA3LCBHRkxBR1MpLAo+ICsKPiArCS8qIHBoeSBy ZWYgKi8KPiArCU1VWEdSRihDTEtfUEhZX1JFRl9TUkMsICJjbGtfcGh5X3JlZl9zcmMiLCBjbGtf cGh5X3JlZl9zcmNfcCwgIDAsCj4gKwkJCVJLMzU3Nl9QTVUwX0dSRl9PU0NfQ09ONiwgNCwgMSwg TUZMQUdTKSwKPiArCU1VWEdSRihDTEtfVVNCUEhZX1JFRl9TUkMsICJjbGtfdXNicGh5X3JlZl9z cmMiLCBjbGtfdXNicGh5X3JlZl9zcmNfcCwgIDAsCj4gKwkJCVJLMzU3Nl9QTVUwX0dSRl9PU0Nf Q09ONiwgMiwgMSwgTUZMQUdTKSwKPiArCU1VWEdSRihDTEtfQ1BMTF9SRUZfU1JDLCAiY2xrX2Nw bGxfcmVmX3NyYyIsIGNsa19jcGxsX3JlZl9zcmNfcCwgIDAsCj4gKwkJCVJLMzU3Nl9QTVUwX0dS Rl9PU0NfQ09ONiwgMSwgMSwgTUZMQUdTKSwKPiArCU1VWEdSRihDTEtfQVVQTExfUkVGX1NSQywg ImNsa19hdXBsbF9yZWZfc3JjIiwgY2xrX2F1cGxsX3JlZl9zcmNfcCwgIDAsCj4gKwkJCVJLMzU3 Nl9QTVUwX0dSRl9PU0NfQ09ONiwgMCwgMSwgTUZMQUdTKSwKPiArCj4gKwkvKiBzZWN1cmUgbnMg Ki8KPiArCUNPTVBPU0lURV9OT0RJVihBQ0xLX1NFQ1VSRV9OUywgImFjbGtfc2VjdXJlX25zIiwg bXV4XzM1MG1fMTc1bV8xMTZtXzI0bV9wLCBDTEtfSVNfQ1JJVElDQUwsCj4gKwkJCVJLMzU3Nl9T RUNVUkVfTlNfQ0xLU0VMX0NPTigwKSwgMCwgMiwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfU0VDVVJF X05TX0NMS0dBVEVfQ09OKDApLCAwLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFX05PRElWKEhDTEtf U0VDVVJFX05TLCAiaGNsa19zZWN1cmVfbnMiLCBtdXhfMTc1bV8xMTZtXzU4bV8yNG1fcCwgQ0xL X0lTX0NSSVRJQ0FMLAo+ICsJCQlSSzM1NzZfU0VDVVJFX05TX0NMS1NFTF9DT04oMCksIDIsIDIs IE1GTEFHUywKPiArCQkJUkszNTc2X1NFQ1VSRV9OU19DTEtHQVRFX0NPTigwKSwgMSwgR0ZMQUdT KSwKPiArCUNPTVBPU0lURV9OT0RJVihQQ0xLX1NFQ1VSRV9OUywgInBjbGtfc2VjdXJlX25zIiwg bXV4XzExNm1fNThtXzI0bV9wLCBDTEtfSVNfQ1JJVElDQUwsCj4gKwkJCVJLMzU3Nl9TRUNVUkVf TlNfQ0xLU0VMX0NPTigwKSwgNCwgMiwgTUZMQUdTLAo+ICsJCQlSSzM1NzZfU0VDVVJFX05TX0NM S0dBVEVfQ09OKDApLCAyLCBHRkxBR1MpLAo+ICsJR0FURShIQ0xLX0NSWVBUT19OUywgImhjbGtf Y3J5cHRvX25zIiwgImhjbGtfc2VjdXJlX25zIiwgMCwKPiArCQkJUkszNTc2X1NFQ1VSRV9OU19D TEtHQVRFX0NPTigwKSwgMywgR0ZMQUdTKSwKPiArCUdBVEUoUENMS19PVFBDX05TLCAicGNsa19v dHBjX25zIiwgInBjbGtfc2VjdXJlX25zIiwgMCwKPiArCQkJUkszNTc2X1NFQ1VSRV9OU19DTEtH QVRFX0NPTigwKSwgOCwgR0ZMQUdTKSwKPiArCUdBVEUoQ0xLX09UUENfTlMsICJjbGtfb3RwY19u cyIsICJ4aW4yNG0iLCAwLAo+ICsJCQlSSzM1NzZfU0VDVVJFX05TX0NMS0dBVEVfQ09OKDApLCA5 LCBHRkxBR1MpLAo+ICsJR0FURShBQ0xLX0NSWVBUT19OUywgImFjbGtfY3J5cHRvX25zIiwgImFj bGtfc2VjdXJlX3MiLCAwLAo+ICsJCQlSSzM1NzZfTk9OX1NFQ1VSRV9HQVRJTkdfQ09OMDAsIDE0 LCBHRkxBR1MpLAo+ICsJR0FURShIQ0xLX1RSTkdfTlMsICJoY2xrX3RybmdfbnMiLCAiaGNsa19z ZWN1cmVfcyIsIDAsCj4gKwkJCVJLMzU3Nl9OT05fU0VDVVJFX0dBVElOR19DT04wMCwgMTMsIEdG TEFHUyksCj4gKwlHQVRFKENMS19QS0FfQ1JZUFRPX05TLCAiY2xrX3BrYV9jcnlwdG9fbnMiLCAi Y2xrX3BrYV9jcnlwdG9fcyIsIDAsCj4gKwkJCVJLMzU3Nl9OT05fU0VDVVJFX0dBVElOR19DT04w MCwgMSwgR0ZMQUdTKSwKPiArCj4gKwkvKiBpbyAqLwo+ICsJR0FURShDTEtfVklDQVBfSTBDTEss ICJjbGtfdmljYXBfaTBjbGsiLCAiY2xrX2NzaWhvc3QwX2Nsa2RhdGFfaSIsIDAsCj4gKwkJCVJL MzU3Nl9DTEtHQVRFX0NPTig1OSksIDEsIEdGTEFHUyksCj4gKwlHQVRFKENMS19WSUNBUF9JMUNM SywgImNsa192aWNhcF9pMWNsayIsICJjbGtfY3NpaG9zdDFfY2xrZGF0YV9pIiwgMCwKPiArCQkJ UkszNTc2X0NMS0dBVEVfQ09OKDU5KSwgMiwgR0ZMQUdTKSwKPiArCUdBVEUoQ0xLX1ZJQ0FQX0ky Q0xLLCAiY2xrX3ZpY2FwX2kyY2xrIiwgImNsa19jc2lob3N0Ml9jbGtkYXRhX2kiLCAwLAo+ICsJ CQlSSzM1NzZfQ0xLR0FURV9DT04oNTkpLCAzLCBHRkxBR1MpLAo+ICsJR0FURShDTEtfVklDQVBf STNDTEssICJjbGtfdmljYXBfaTNjbGsiLCAiY2xrX2NzaWhvc3QzX2Nsa2RhdGFfaSIsIDAsCj4g KwkJCVJLMzU3Nl9DTEtHQVRFX0NPTig1OSksIDQsIEdGTEFHUyksCj4gKwlHQVRFKENMS19WSUNB UF9JNENMSywgImNsa192aWNhcF9pNGNsayIsICJjbGtfY3NpaG9zdDRfY2xrZGF0YV9pIiwgMCwK PiArCQkJUkszNTc2X0NMS0dBVEVfQ09OKDU5KSwgNSwgR0ZMQUdTKSwKPiArfTsKPiArCj4gK3N0 YXRpYyB2b2lkIF9faW5pdCByazM1NzZfY2xrX2luaXQoc3RydWN0IGRldmljZV9ub2RlICpucCkK PiArewo+ICsJc3RydWN0IHJvY2tjaGlwX2Nsa19wcm92aWRlciAqY3R4Owo+ICsJdW5zaWduZWQg bG9uZyBjbGtfbnJfY2xrczsKPiArCXZvaWQgX19pb21lbSAqcmVnX2Jhc2U7Cj4gKwo+ICsJY2xr X25yX2Nsa3MgPSByb2NrY2hpcF9jbGtfZmluZF9tYXhfY2xrX2lkKHJrMzU3Nl9jbGtfYnJhbmNo ZXMsCj4gKwkJCQkJQVJSQVlfU0laRShyazM1NzZfY2xrX2JyYW5jaGVzKSkgKyAxOwo+ICsKPiAr CXJlZ19iYXNlID0gb2ZfaW9tYXAobnAsIDApOwo+ICsJaWYgKCFyZWdfYmFzZSkgewo+ICsJCXBy X2VycigiJXM6IGNvdWxkIG5vdCBtYXAgY3J1IHJlZ2lvblxuIiwgX19mdW5jX18pOwo+ICsJCXJl dHVybjsKPiArCX0KPiArCj4gKwljdHggPSByb2NrY2hpcF9jbGtfaW5pdChucCwgcmVnX2Jhc2Us IGNsa19ucl9jbGtzKTsKPiArCWlmIChJU19FUlIoY3R4KSkgewo+ICsJCXByX2VycigiJXM6IHJv Y2tjaGlwIGNsayBpbml0IGZhaWxlZFxuIiwgX19mdW5jX18pOwo+ICsJCWlvdW5tYXAocmVnX2Jh c2UpOwo+ICsJCXJldHVybjsKPiArCX0KPiArCj4gKwlyb2NrY2hpcF9jbGtfcmVnaXN0ZXJfcGxs cyhjdHgsIHJrMzU3Nl9wbGxfY2xrcywKPiArCQkJCSAgIEFSUkFZX1NJWkUocmszNTc2X3BsbF9j bGtzKSwKPiArCQkJCSAgIFJLMzU3Nl9HUkZfU09DX1NUQVRVUzApOwo+ICsKPiArCXJvY2tjaGlw X2Nsa19yZWdpc3Rlcl9hcm1jbGsoY3R4LCBBUk1DTEtfTCwgImFybWNsa19sIiwKPiArCQkJbXV4 X2FybWNsa2xfcCwgQVJSQVlfU0laRShtdXhfYXJtY2xrbF9wKSwKPiArCQkJJnJrMzU3Nl9jcHVs Y2xrX2RhdGEsIHJrMzU3Nl9jcHVsY2xrX3JhdGVzLAo+ICsJCQlBUlJBWV9TSVpFKHJrMzU3Nl9j cHVsY2xrX3JhdGVzKSk7Cj4gKwlyb2NrY2hpcF9jbGtfcmVnaXN0ZXJfYXJtY2xrKGN0eCwgQVJN Q0xLX0IsICJhcm1jbGtfYiIsCj4gKwkJCW11eF9hcm1jbGtiX3AsIEFSUkFZX1NJWkUobXV4X2Fy bWNsa2JfcCksCj4gKwkJCSZyazM1NzZfY3B1YmNsa19kYXRhLCByazM1NzZfY3B1YmNsa19yYXRl cywKPiArCQkJQVJSQVlfU0laRShyazM1NzZfY3B1YmNsa19yYXRlcykpOwo+ICsKPiArCXJvY2tj aGlwX2Nsa19yZWdpc3Rlcl9icmFuY2hlcyhjdHgsIHJrMzU3Nl9jbGtfYnJhbmNoZXMsCj4gKwkJ CQkgICAgICAgQVJSQVlfU0laRShyazM1NzZfY2xrX2JyYW5jaGVzKSk7Cj4gKwo+ICsJcmszNTc2 X3JzdF9pbml0KG5wLCByZWdfYmFzZSk7Cj4gKwo+ICsJcm9ja2NoaXBfcmVnaXN0ZXJfcmVzdGFy dF9ub3RpZmllcihjdHgsIFJLMzU3Nl9HTEJfU1JTVF9GU1QsIE5VTEwpOwo+ICsKPiArCXJvY2tj aGlwX2Nsa19vZl9hZGRfcHJvdmlkZXIobnAsIGN0eCk7Cj4gK30KPiArCj4gK0NMS19PRl9ERUNM QVJFKHJrMzU3Nl9jcnUsICJyb2NrY2hpcCxyazM1NzYtY3J1IiwgcmszNTc2X2Nsa19pbml0KTsK PiArCj4gKyNpZmRlZiBNT0RVTEUKPiArc3RydWN0IGNsa19yazM1NzZfaW5pdHMgewo+ICsJdm9p ZCAoKmluaXRzKShzdHJ1Y3QgZGV2aWNlX25vZGUgKm5wKTsKPiArfTsKPiArCj4gK3N0YXRpYyBj b25zdCBzdHJ1Y3QgY2xrX3JrMzU3Nl9pbml0cyBjbGtfcmszNTc2X2NydV9pbml0ID0gewo+ICsJ LmluaXRzID0gcmszNTc2X2Nsa19pbml0LAo+ICt9Owo+ICsKPiArc3RhdGljIGNvbnN0IHN0cnVj dCBvZl9kZXZpY2VfaWQgY2xrX3JrMzU3Nl9tYXRjaF90YWJsZVtdID0gewo+ICsJewo+ICsJCS5j b21wYXRpYmxlID0gInJvY2tjaGlwLHJrMzU3Ni1jcnUiLAo+ICsJCS5kYXRhID0gJmNsa19yazM1 NzZfY3J1X2luaXQsCj4gKwl9LAo+ICsJeyB9Cj4gK307Cj4gK01PRFVMRV9ERVZJQ0VfVEFCTEUo b2YsIGNsa19yazM1NzZfbWF0Y2hfdGFibGUpOwo+ICsKPiArc3RhdGljIGludCBjbGtfcmszNTc2 X3Byb2JlKHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpCj4gK3sKPiArCXN0cnVjdCBkZXZp Y2Vfbm9kZSAqbnAgPSBwZGV2LT5kZXYub2Zfbm9kZTsKPiArCWNvbnN0IHN0cnVjdCBvZl9kZXZp Y2VfaWQgKm1hdGNoOwo+ICsJY29uc3Qgc3RydWN0IGNsa19yazM1NzZfaW5pdHMgKmluaXRfZGF0 YTsKPiArCj4gKwltYXRjaCA9IG9mX21hdGNoX2RldmljZShjbGtfcmszNTc2X21hdGNoX3RhYmxl LCAmcGRldi0+ZGV2KTsKPiArCWlmICghbWF0Y2ggfHwgIW1hdGNoLT5kYXRhKQo+ICsJCXJldHVy biAtRUlOVkFMOwo+ICsKPiArCWluaXRfZGF0YSA9IG1hdGNoLT5kYXRhOwo+ICsJaWYgKGluaXRf ZGF0YS0+aW5pdHMpCj4gKwkJaW5pdF9kYXRhLT5pbml0cyhucCk7Cj4gKwo+ICsJcmV0dXJuIDA7 Cj4gK30KPiArCj4gK3N0YXRpYyBzdHJ1Y3QgcGxhdGZvcm1fZHJpdmVyIGNsa19yazM1NzZfZHJp dmVyID0gewo+ICsJLnByb2JlCQk9IGNsa19yazM1NzZfcHJvYmUsCj4gKwkuZHJpdmVyCQk9IHsK PiArCQkubmFtZQk9ICJjbGstcmszNTc2IiwKPiArCQkub2ZfbWF0Y2hfdGFibGUgPSBjbGtfcmsz NTc2X21hdGNoX3RhYmxlLAo+ICsJCS5zdXBwcmVzc19iaW5kX2F0dHJzID0gdHJ1ZSwKPiArCX0s Cj4gK307Cj4gK21vZHVsZV9wbGF0Zm9ybV9kcml2ZXIoY2xrX3JrMzU3Nl9kcml2ZXIpOwo+ICsK PiArTU9EVUxFX0RFU0NSSVBUSU9OKCJSb2NrY2hpcCBSSzM1NzYgQ2xvY2sgRHJpdmVyIik7Cj4g K01PRFVMRV9MSUNFTlNFKCJHUEwiKTsKPiArI2VuZGlmIC8qIE1PRFVMRSAqLwo+IGRpZmYgLS1n aXQgYS9kcml2ZXJzL2Nsay9yb2NrY2hpcC9jbGsuaCBiL2RyaXZlcnMvY2xrL3JvY2tjaGlwL2Ns ay5oCj4gaW5kZXggZmQzYjQ3NmRlZGRhOS4uNDNlYWVhYzhhOGY2MiAxMDA2NDQKPiAtLS0gYS9k cml2ZXJzL2Nsay9yb2NrY2hpcC9jbGsuaAo+ICsrKyBiL2RyaXZlcnMvY2xrL3JvY2tjaGlwL2Ns ay5oCj4gQEAgLTIzNSw2ICsyMzUsNTggQEAgc3RydWN0IGNsazsKPiAgICNkZWZpbmUgUkszNTY4 X1BNVV9DTEtHQVRFX0NPTih4KQkoKHgpICogMHg0ICsgMHgxODApCj4gICAjZGVmaW5lIFJLMzU2 OF9QTVVfU09GVFJTVF9DT04oeCkJKCh4KSAqIDB4NCArIDB4MjAwKQo+ICAgCj4gKyNkZWZpbmUg UkszNTc2X1BIUF9DUlVfQkFTRQkJMHg4MDAwCj4gKyNkZWZpbmUgUkszNTc2X1NFQ1VSRV9OU19D UlVfQkFTRQkweDEwMDAwCj4gKyNkZWZpbmUgUkszNTc2X1BNVV9DUlVfQkFTRQkJMHgyMDAwMAo+ ICsjZGVmaW5lIFJLMzU3Nl9CSUdDT1JFX0NSVV9CQVNFCQkweDM4MDAwCj4gKyNkZWZpbmUgUksz NTc2X0xJVENPUkVfQ1JVX0JBU0UJCTB4NDAwMDAKPiArI2RlZmluZSBSSzM1NzZfQ0NJX0NSVV9C QVNFCQkweDQ4MDAwCj4gKwo+ICsjZGVmaW5lIFJLMzU3Nl9QTExfQ09OKHgpCQlSSzI5MjhfUExM X0NPTih4KQo+ICsjZGVmaW5lIFJLMzU3Nl9NT0RFX0NPTjAJCTB4MjgwCj4gKyNkZWZpbmUgUksz NTc2X0JQTExfTU9ERV9DT04wCQkoUkszNTc2X0JJR0NPUkVfQ1JVX0JBU0UgKyAweDI4MCkKPiAr I2RlZmluZSBSSzM1NzZfTFBMTF9NT0RFX0NPTjAJCShSSzM1NzZfTElUQ09SRV9DUlVfQkFTRSAr IDB4MjgwKQo+ICsjZGVmaW5lIFJLMzU3Nl9QUExMX01PREVfQ09OMAkJKFJLMzU3Nl9QSFBfQ1JV X0JBU0UgKyAweDI4MCkKPiArI2RlZmluZSBSSzM1NzZfQ0xLU0VMX0NPTih4KQkJKCh4KSAqIDB4 NCArIDB4MzAwKQo+ICsjZGVmaW5lIFJLMzU3Nl9DTEtHQVRFX0NPTih4KQkJKCh4KSAqIDB4NCAr IDB4ODAwKQo+ICsjZGVmaW5lIFJLMzU3Nl9TT0ZUUlNUX0NPTih4KQkJKCh4KSAqIDB4NCArIDB4 YTAwKQo+ICsjZGVmaW5lIFJLMzU3Nl9HTEJfQ05UX1RICQkweGMwMAo+ICsjZGVmaW5lIFJLMzU3 Nl9HTEJfU1JTVF9GU1QJCTB4YzA4Cj4gKyNkZWZpbmUgUkszNTc2X0dMQl9TUlNUX1NORAkJMHhj MGMKPiArI2RlZmluZSBSSzM1NzZfR0xCX1JTVF9DT04JCTB4YzEwCj4gKyNkZWZpbmUgUkszNTc2 X0dMQl9SU1RfU1QJCTB4YzA0Cj4gKyNkZWZpbmUgUkszNTc2X1NESU9fQ09OMAkJMHhDMjQKPiAr I2RlZmluZSBSSzM1NzZfU0RJT19DT04xCQkweEMyOAo+ICsjZGVmaW5lIFJLMzU3Nl9TRE1NQ19D T04wCQkweEMzMAo+ICsjZGVmaW5lIFJLMzU3Nl9TRE1NQ19DT04xCQkweEMzNAo+ICsKPiArI2Rl ZmluZSBSSzM1NzZfUEhQX0NMS1NFTF9DT04oeCkJKCh4KSAqIDB4NCArIFJLMzU3Nl9QSFBfQ1JV X0JBU0UgKyAweDMwMCkKPiArI2RlZmluZSBSSzM1NzZfUEhQX0NMS0dBVEVfQ09OKHgpCSgoeCkg KiAweDQgKyBSSzM1NzZfUEhQX0NSVV9CQVNFICsgMHg4MDApCj4gKyNkZWZpbmUgUkszNTc2X1BI UF9TT0ZUUlNUX0NPTih4KQkoKHgpICogMHg0ICsgUkszNTc2X1BIUF9DUlVfQkFTRSArIDB4YTAw KQo+ICsKPiArI2RlZmluZSBSSzM1NzZfUE1VX1BMTF9DT04oeCkJCSgoeCkgKiAweDQgKyBSSzM1 NzZfUEhQX0NSVV9CQVNFKQo+ICsjZGVmaW5lIFJLMzU3Nl9QTVVfQ0xLU0VMX0NPTih4KQkoKHgp ICogMHg0ICsgUkszNTc2X1BNVV9DUlVfQkFTRSArIDB4MzAwKQo+ICsjZGVmaW5lIFJLMzU3Nl9Q TVVfQ0xLR0FURV9DT04oeCkJKCh4KSAqIDB4NCArIFJLMzU3Nl9QTVVfQ1JVX0JBU0UgKyAweDgw MCkKPiArI2RlZmluZSBSSzM1NzZfUE1VX1NPRlRSU1RfQ09OKHgpCSgoeCkgKiAweDQgKyBSSzM1 NzZfUE1VX0NSVV9CQVNFICsgMHhhMDApCj4gKwo+ICsjZGVmaW5lIFJLMzU3Nl9TRUNVUkVfTlNf Q0xLU0VMX0NPTih4KQkoKHgpICogMHg0ICsgUkszNTc2X1NFQ1VSRV9OU19DUlVfQkFTRSArIDB4 MzAwKQo+ICsjZGVmaW5lIFJLMzU3Nl9TRUNVUkVfTlNfQ0xLR0FURV9DT04oeCkJKCh4KSAqIDB4 NCArIFJLMzU3Nl9TRUNVUkVfTlNfQ1JVX0JBU0UgKyAweDgwMCkKPiArI2RlZmluZSBSSzM1NzZf U0VDVVJFX05TX1NPRlRSU1RfQ09OKHgpCSgoeCkgKiAweDQgKyBSSzM1NzZfU0VDVVJFX05TX0NS VV9CQVNFICsgMHhhMDApCj4gKwo+ICsjZGVmaW5lIFJLMzU3Nl9DQ0lfQ0xLU0VMX0NPTih4KQko KHgpICogMHg0ICsgUkszNTc2X0NDSV9DUlVfQkFTRSArIDB4MzAwKQo+ICsjZGVmaW5lIFJLMzU3 Nl9DQ0lfQ0xLR0FURV9DT04oeCkJKCh4KSAqIDB4NCArIFJLMzU3Nl9DQ0lfQ1JVX0JBU0UgKyAw eDgwMCkKPiArI2RlZmluZSBSSzM1NzZfQ0NJX1NPRlRSU1RfQ09OKHgpCSgoeCkgKiAweDQgKyBS SzM1NzZfQ0NJX0NSVV9CQVNFICsgMHhhMDApCj4gKwo+ICsjZGVmaW5lIFJLMzU3Nl9CUExMX0NP Tih4KQkJKCh4KSAqIDB4NCArIFJLMzU3Nl9CSUdDT1JFX0NSVV9CQVNFKQo+ICsjZGVmaW5lIFJL MzU3Nl9CSUdDT1JFX0NMS1NFTF9DT04oeCkJKCh4KSAqIDB4NCArIFJLMzU3Nl9CSUdDT1JFX0NS VV9CQVNFICsgMHgzMDApCj4gKyNkZWZpbmUgUkszNTc2X0JJR0NPUkVfQ0xLR0FURV9DT04oeCkJ KCh4KSAqIDB4NCArIFJLMzU3Nl9CSUdDT1JFX0NSVV9CQVNFICsgMHg4MDApCj4gKyNkZWZpbmUg UkszNTc2X0JJR0NPUkVfU09GVFJTVF9DT04oeCkJKCh4KSAqIDB4NCArIFJLMzU3Nl9CSUdDT1JF X0NSVV9CQVNFICsgMHhhMDApCj4gKyNkZWZpbmUgUkszNTc2X0xQTExfQ09OKHgpCQkoKHgpICog MHg0ICsgUkszNTc2X0NDSV9DUlVfQkFTRSkKPiArI2RlZmluZSBSSzM1NzZfTElUQ09SRV9DTEtT RUxfQ09OKHgpCSgoeCkgKiAweDQgKyBSSzM1NzZfTElUQ09SRV9DUlVfQkFTRSArIDB4MzAwKQo+ ICsjZGVmaW5lIFJLMzU3Nl9MSVRDT1JFX0NMS0dBVEVfQ09OKHgpCSgoeCkgKiAweDQgKyBSSzM1 NzZfTElUQ09SRV9DUlVfQkFTRSArIDB4ODAwKQo+ICsjZGVmaW5lIFJLMzU3Nl9MSVRDT1JFX1NP RlRSU1RfQ09OKHgpCSgoeCkgKiAweDQgKyBSSzM1NzZfTElUQ09SRV9DUlVfQkFTRSArIDB4YTAw KQo+ICsjZGVmaW5lIFJLMzU3Nl9OT05fU0VDVVJFX0dBVElOR19DT04wMAkweGM0OAo+ICsKPiAg ICNkZWZpbmUgUkszNTg4X1BIUF9DUlVfQkFTRQkJMHg4MDAwCj4gICAjZGVmaW5lIFJLMzU4OF9Q TVVfQ1JVX0JBU0UJCTB4MzAwMDAKPiAgICNkZWZpbmUgUkszNTg4X0JJR0NPUkUwX0NSVV9CQVNF CTB4NTAwMDAKPiBAQCAtMTAyNSw2ICsxMDc3LDcgQEAgc3RhdGljIGlubGluZSB2b2lkIHJvY2tj aGlwX3JlZ2lzdGVyX3NvZnRyc3Qoc3RydWN0IGRldmljZV9ub2RlICpucCwKPiAgIAlyZXR1cm4g cm9ja2NoaXBfcmVnaXN0ZXJfc29mdHJzdF9sdXQobnAsIE5VTEwsIG51bV9yZWdzLCBiYXNlLCBm bGFncyk7Cj4gICB9Cj4gICAKPiArdm9pZCByazM1NzZfcnN0X2luaXQoc3RydWN0IGRldmljZV9u b2RlICpucCwgdm9pZCBfX2lvbWVtICpyZWdfYmFzZSk7Cj4gICB2b2lkIHJrMzU4OF9yc3RfaW5p dChzdHJ1Y3QgZGV2aWNlX25vZGUgKm5wLCB2b2lkIF9faW9tZW0gKnJlZ19iYXNlKTsKPiAgIAo+ ICAgI2VuZGlmCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvY2xrL3JvY2tjaGlwL3JzdC1yazM1NzYu YyBiL2RyaXZlcnMvY2xrL3JvY2tjaGlwL3JzdC1yazM1NzYuYwo+IG5ldyBmaWxlIG1vZGUgMTAw NjQ0Cj4gaW5kZXggMDAwMDAwMDAwMDAwMC4uMzM4MGQ3M2M4NmM1Mgo+IC0tLSAvZGV2L251bGwK PiArKysgYi9kcml2ZXJzL2Nsay9yb2NrY2hpcC9yc3QtcmszNTc2LmMKPiBAQCAtMCwwICsxLDY1 MiBAQAo+ICsvLyBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BMLTIuMC1vci1sYXRlcgo+ICsv Kgo+ICsgKiBDb3B5cmlnaHQgKGMpIDIwMjEgUm9ja2NoaXAgRWxlY3Ryb25pY3MgQ28uLCBMdGQu Cj4gKyAqIENvcHlyaWdodCAoYykgMjAyNCBDb2xsYWJvcmEgTHRkLgo+ICsgKiBBdXRob3I6IERl dGxldiBDYXNhbm92YSA8ZGV0bGV2LmNhc2Fub3ZhQGNvbGxhYm9yYS5jb20+Cj4gKyAqIEJhc2Vk IG9uIFNlYmFzdGllbiBSZWljaGVsJ3MgaW1wbGVtZW50YXRpb24gZm9yIFJLMzU4OAo+ICsgKi8K PiArCj4gKyNpbmNsdWRlIDxsaW51eC9tb2R1bGUuaD4KPiArI2luY2x1ZGUgPGxpbnV4L29mLmg+ Cj4gKyNpbmNsdWRlIDxkdC1iaW5kaW5ncy9yZXNldC9yb2NrY2hpcCxyazM1NzYtY3J1Lmg+Cj4g KyNpbmNsdWRlICJjbGsuaCIKPiArCj4gKy8qIDB4MjcyMDAwMDAgKyAweDBBMDAgKi8KPiArI2Rl ZmluZSBSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChpZCwgcmVnLCBiaXQpIFtpZF0gPSAoMCArIHJl ZyAqIDE2ICsgYml0KQo+ICsvKiAweDI3MjA4MDAwICsgMHgwQTAwICovCj4gKyNkZWZpbmUgUksz NTc2X1BIUENSVV9SRVNFVF9PRkZTRVQoaWQsIHJlZywgYml0KSBbaWRdID0gKDB4ODAwMCo0ICsg cmVnICogMTYgKyBiaXQpCj4gKy8qIDB4MjcyMTAwMDAgKyAweDBBMDAgKi8KPiArI2RlZmluZSBS SzM1NzZfU0VDVVJFTlNDUlVfUkVTRVRfT0ZGU0VUKGlkLCByZWcsIGJpdCkgW2lkXSA9ICgweDEw MDAwKjQgKyByZWcgKiAxNiArIGJpdCkKPiArLyogMHgyNzIyMDAwMCArIDB4MEEwMCAqLwo+ICsj ZGVmaW5lIFJLMzU3Nl9QTVUxQ1JVX1JFU0VUX09GRlNFVChpZCwgcmVnLCBiaXQpIFtpZF0gPSAo MHgyMDAwMCo0ICsgcmVnICogMTYgKyBiaXQpCj4gKwo+ICsvKiBtYXBwaW5nIHRhYmxlIGZvciBy ZXNldCBJRCB0byByZWdpc3RlciBvZmZzZXQgKi8KPiArc3RhdGljIGNvbnN0IGludCByazM1NzZf cmVnaXN0ZXJfb2Zmc2V0W10gPSB7Cj4gKwkvKiBTT0ZUUlNUX0NPTjAxICovCj4gKwlSSzM1NzZf Q1JVX1JFU0VUX09GRlNFVChTUlNUX0FfVE9QX0JJVSwgMSwgMyksCj4gKwlSSzM1NzZfQ1JVX1JF U0VUX09GRlNFVChTUlNUX1BfVE9QX0JJVSwgMSwgNSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09G RlNFVChTUlNUX0FfVE9QX01JRF9CSVUsIDEsIDYpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZT RVQoU1JTVF9BX1NFQ1VSRV9ISUdIX0JJVSwgMSwgNyksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09G RlNFVChTUlNUX0hfVE9QX0JJVSwgMSwgMTQpLAo+ICsKPiArCS8qIFNPRlRSU1RfQ09OMDIgKi8K PiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9WTzBWT1BfQ0hBTk5FTF9CSVUsIDIs IDApLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX1ZPMFZPUF9DSEFOTkVMX0JJ VSwgMiwgMSksCj4gKwo+ICsJLyogU09GVFJTVF9DT04wNiAqLwo+ICsJUkszNTc2X0NSVV9SRVNF VF9PRkZTRVQoU1JTVF9CSVNSSU5URiwgNiwgMiksCj4gKwo+ICsJLyogU09GVFJTVF9DT04wNyAq Lwo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9IX0FVRElPX0JJVSwgNywgMiksCj4g KwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0hfQVNSQ18yQ0hfMCwgNywgMyksCj4gKwlS SzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0hfQVNSQ18yQ0hfMSwgNywgNCksCj4gKwlSSzM1 NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0hfQVNSQ180Q0hfMCwgNywgNSksCj4gKwlSSzM1NzZf Q1JVX1JFU0VUX09GRlNFVChTUlNUX0hfQVNSQ180Q0hfMSwgNywgNiksCj4gKwlSSzM1NzZfQ1JV X1JFU0VUX09GRlNFVChTUlNUX0FTUkNfMkNIXzAsIDcsIDcpLAo+ICsJUkszNTc2X0NSVV9SRVNF VF9PRkZTRVQoU1JTVF9BU1JDXzJDSF8xLCA3LCA4KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZG U0VUKFNSU1RfQVNSQ180Q0hfMCwgNywgOSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChT UlNUX0FTUkNfNENIXzEsIDcsIDEwKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1Rf TV9TQUkwXzhDSCwgNywgMTIpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9IX1NB STBfOENILCA3LCAxMyksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0hfU1BESUZf UlgwLCA3LCAxNCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX01fU1BESUZfUlgw LCA3LCAxNSksCj4gKwo+ICsJLyogU09GVFJTVF9DT04wOCAqLwo+ICsJUkszNTc2X0NSVV9SRVNF VF9PRkZTRVQoU1JTVF9IX1NQRElGX1JYMSwgOCwgMCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09G RlNFVChTUlNUX01fU1BESUZfUlgxLCA4LCAxKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VU KFNSU1RfTV9TQUkxXzhDSCwgOCwgNSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNU X0hfU0FJMV84Q0gsIDgsIDYpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9NX1NB STJfMkNILCA4LCA4KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9TQUkyXzJD SCwgOCwgMTApLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9NX1NBSTNfMkNILCA4 LCAxMiksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0hfU0FJM18yQ0gsIDgsIDE0 KSwKPiArCj4gKwkvKiBTT0ZUUlNUX0NPTjA5ICovCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNF VChTUlNUX01fU0FJNF8yQ0gsIDksIDApLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JT VF9IX1NBSTRfMkNILCA5LCAyKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9B Q0RDRElHX0RTTSwgOSwgMyksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX01fQUNE Q0RJR19EU00sIDksIDQpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9QRE0xLCA5 LCA1KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9QRE0xLCA5LCA3KSwKPiAr CVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfTV9QRE0xLCA5LCA4KSwKPiArCVJLMzU3Nl9D UlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9TUERJRl9UWDAsIDksIDkpLAo+ICsJUkszNTc2X0NSVV9S RVNFVF9PRkZTRVQoU1JTVF9NX1NQRElGX1RYMCwgOSwgMTApLAo+ICsJUkszNTc2X0NSVV9SRVNF VF9PRkZTRVQoU1JTVF9IX1NQRElGX1RYMSwgOSwgMTEpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9P RkZTRVQoU1JTVF9NX1NQRElGX1RYMSwgOSwgMTIpLAo+ICsKPiArCS8qIFNPRlRSU1RfQ09OMTEg Ki8KPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQV9CVVNfQklVLCAxMSwgMyksCj4g KwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfQlVTX0JJVSwgMTEsIDQpLAo+ICsJUksz NTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX0NSVSwgMTEsIDUpLAo+ICsJUkszNTc2X0NSVV9S RVNFVF9PRkZTRVQoU1JTVF9IX0NBTjAsIDExLCA2KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZG U0VUKFNSU1RfQ0FOMCwgMTEsIDcpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9I X0NBTjEsIDExLCA4KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQ0FOMSwgMTEs IDkpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX0lOVE1VWDJCVVMsIDExLCAx MiksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfVkNDSU9fSU9DLCAxMSwgMTMp LAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9IX0JVU19CSVUsIDExLCAxNCksCj4g KwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0tFWV9TSElGVCwgMTEsIDE1KSwKPiArCj4g KwkvKiBTT0ZUUlNUX0NPTjEyICovCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1Bf STJDMSwgMTIsIDApLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX0kyQzIsIDEy LCAxKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9JMkMzLCAxMiwgMiksCj4g KwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfSTJDNCwgMTIsIDMpLAo+ICsJUkszNTc2 X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX0kyQzUsIDEyLCA0KSwKPiArCVJLMzU3Nl9DUlVfUkVT RVRfT0ZGU0VUKFNSU1RfUF9JMkM2LCAxMiwgNSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNF VChTUlNUX1BfSTJDNywgMTIsIDYpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9Q X0kyQzgsIDEyLCA3KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9JMkM5LCAx MiwgOCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfV0RUX0JVU01DVSwgMTIs IDkpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9UX1dEVF9CVVNNQ1UsIDEyLCAx MCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0FfR0lDLCAxMiwgMTEpLAo+ICsJ UkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9JMkMxLCAxMiwgMTIpLAo+ICsJUkszNTc2X0NS VV9SRVNFVF9PRkZTRVQoU1JTVF9JMkMyLCAxMiwgMTMpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9P RkZTRVQoU1JTVF9JMkMzLCAxMiwgMTQpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JT VF9JMkM0LCAxMiwgMTUpLAo+ICsKPiArCS8qIFNPRlRSU1RfQ09OMTMgKi8KPiArCVJLMzU3Nl9D UlVfUkVTRVRfT0ZGU0VUKFNSU1RfSTJDNSwgMTMsIDApLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9P RkZTRVQoU1JTVF9JMkM2LCAxMywgMSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNU X0kyQzcsIDEzLCAyKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSTJDOCwgMTMs IDMpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9JMkM5LCAxMywgNCksCj4gKwlS SzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfU0FSQURDLCAxMywgNiksCj4gKwlSSzM1NzZf Q1JVX1JFU0VUX09GRlNFVChTUlNUX1NBUkFEQywgMTMsIDcpLAo+ICsJUkszNTc2X0NSVV9SRVNF VF9PRkZTRVQoU1JTVF9QX1RTQURDLCAxMywgOCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNF VChTUlNUX1RTQURDLCAxMywgOSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1Bf VUFSVDAsIDEzLCAxMCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfVUFSVDIs IDEzLCAxMSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfVUFSVDMsIDEzLCAx MiksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfVUFSVDQsIDEzLCAxMyksCj4g KwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfVUFSVDUsIDEzLCAxNCksCj4gKwlSSzM1 NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfVUFSVDYsIDEzLCAxNSksCj4gKwo+ICsJLyogU09G VFJTVF9DT04xNCAqLwo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX1VBUlQ3LCAx NCwgMCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfVUFSVDgsIDE0LCAxKSwK PiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9VQVJUOSwgMTQsIDIpLAo+ICsJUksz NTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX1VBUlQxMCwgMTQsIDMpLAo+ICsJUkszNTc2X0NS VV9SRVNFVF9PRkZTRVQoU1JTVF9QX1VBUlQxMSwgMTQsIDQpLAo+ICsJUkszNTc2X0NSVV9SRVNF VF9PRkZTRVQoU1JTVF9TX1VBUlQwLCAxNCwgNSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNF VChTUlNUX1NfVUFSVDIsIDE0LCA2KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1Rf U19VQVJUMywgMTQsIDkpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9TX1VBUlQ0 LCAxNCwgMTIpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9TX1VBUlQ1LCAxNCwg MTUpLAo+ICsKPiArCS8qIFNPRlRSU1RfQ09OMTUgKi8KPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZG U0VUKFNSU1RfU19VQVJUNiwgMTUsIDIpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JT VF9TX1VBUlQ3LCAxNSwgNSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1NfVUFS VDgsIDE1LCA4KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfU19VQVJUOSwgMTUs IDkpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9TX1VBUlQxMCwgMTUsIDEwKSwK PiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfU19VQVJUMTEsIDE1LCAxMSksCj4gKwlS SzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfU1BJMCwgMTUsIDEzKSwKPiArCVJLMzU3Nl9D UlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9TUEkxLCAxNSwgMTQpLAo+ICsJUkszNTc2X0NSVV9SRVNF VF9PRkZTRVQoU1JTVF9QX1NQSTIsIDE1LCAxNSksCj4gKwo+ICsJLyogU09GVFJTVF9DT04xNiAq Lwo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX1NQSTMsIDE2LCAwKSwKPiArCVJL MzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9TUEk0LCAxNiwgMSksCj4gKwlSSzM1NzZfQ1JV X1JFU0VUX09GRlNFVChTUlNUX1NQSTAsIDE2LCAyKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZG U0VUKFNSU1RfU1BJMSwgMTYsIDMpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9T UEkyLCAxNiwgNCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1NQSTMsIDE2LCA1 KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfU1BJNCwgMTYsIDYpLAo+ICsJUksz NTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX1dEVDAsIDE2LCA3KSwKPiArCVJLMzU3Nl9DUlVf UkVTRVRfT0ZGU0VUKFNSU1RfVF9XRFQwLCAxNiwgOCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09G RlNFVChTUlNUX1BfU1lTX0dSRiwgMTYsIDkpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQo U1JTVF9QX1BXTTEsIDE2LCAxMCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BX TTEsIDE2LCAxMSksCj4gKwo+ICsJLyogU09GVFJTVF9DT04xNyAqLwo+ICsJUkszNTc2X0NSVV9S RVNFVF9PRkZTRVQoU1JTVF9QX0JVU1RJTUVSMCwgMTcsIDMpLAo+ICsJUkszNTc2X0NSVV9SRVNF VF9PRkZTRVQoU1JTVF9QX0JVU1RJTUVSMSwgMTcsIDQpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9P RkZTRVQoU1JTVF9USU1FUjAsIDE3LCA2KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNS U1RfVElNRVIxLCAxNywgNyksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1RJTUVS MiwgMTcsIDgpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9USU1FUjMsIDE3LCA5 KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfVElNRVI0LCAxNywgMTApLAo+ICsJ UkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9USU1FUjUsIDE3LCAxMSksCj4gKwlSSzM1NzZf Q1JVX1JFU0VUX09GRlNFVChTUlNUX1BfQlVTSU9DLCAxNywgMTIpLAo+ICsJUkszNTc2X0NSVV9S RVNFVF9PRkZTRVQoU1JTVF9QX01BSUxCT1gwLCAxNywgMTMpLAo+ICsJUkszNTc2X0NSVV9SRVNF VF9PRkZTRVQoU1JTVF9QX0dQSU8xLCAxNywgMTUpLAo+ICsKPiArCS8qIFNPRlRSU1RfQ09OMTgg Ki8KPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfR1BJTzEsIDE4LCAwKSwKPiArCVJL MzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9HUElPMiwgMTgsIDEpLAo+ICsJUkszNTc2X0NS VV9SRVNFVF9PRkZTRVQoU1JTVF9HUElPMiwgMTgsIDIpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9P RkZTRVQoU1JTVF9QX0dQSU8zLCAxOCwgMyksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChT UlNUX0dQSU8zLCAxOCwgNCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfR1BJ TzQsIDE4LCA1KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfR1BJTzQsIDE4LCA2 KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQV9ERUNPTSwgMTgsIDcpLAo+ICsJ UkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX0RFQ09NLCAxOCwgOCksCj4gKwlSSzM1NzZf Q1JVX1JFU0VUX09GRlNFVChTUlNUX0RfREVDT00sIDE4LCA5KSwKPiArCVJLMzU3Nl9DUlVfUkVT RVRfT0ZGU0VUKFNSU1RfVElNRVI2LCAxOCwgMTEpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZT RVQoU1JTVF9USU1FUjcsIDE4LCAxMiksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNU X1RJTUVSOCwgMTgsIDEzKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfVElNRVI5 LCAxOCwgMTQpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9USU1FUjEwLCAxOCwg MTUpLAo+ICsKPiArCS8qIFNPRlRSU1RfQ09OMTkgKi8KPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZG U0VUKFNSU1RfVElNRVIxMSwgMTksIDApLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JT VF9BX0RNQUMwLCAxOSwgMSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0FfRE1B QzEsIDE5LCAyKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQV9ETUFDMiwgMTks IDMpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX1NQSU5MT0NLLCAxOSwgNCks Cj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1JFRl9QVlRQTExfQlVTLCAxOSwgNSks Cj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0hfSTNDMCwgMTksIDcpLAo+ICsJUksz NTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9IX0kzQzEsIDE5LCA5KSwKPiArCVJLMzU3Nl9DUlVf UkVTRVRfT0ZGU0VUKFNSU1RfSF9CVVNfQ00wX0JJVSwgMTksIDExKSwKPiArCVJLMzU3Nl9DUlVf UkVTRVRfT0ZGU0VUKFNSU1RfRl9CVVNfQ00wX0NPUkUsIDE5LCAxMiksCj4gKwlSSzM1NzZfQ1JV X1JFU0VUX09GRlNFVChTUlNUX1RfQlVTX0NNMF9KVEFHLCAxOSwgMTMpLAo+ICsKPiArCS8qIFNP RlRSU1RfQ09OMjAgKi8KPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9JTlRNVVgy UE1VLCAyMCwgMCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfSU5UTVVYMkRE UiwgMjAsIDEpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX1BWVFBMTF9CVVMs IDIwLCAzKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9QV00yLCAyMCwgNCks Cj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BXTTIsIDIwLCA1KSwKPiArCVJLMzU3 Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfRlJFUV9QV00xLCAyMCwgOCksCj4gKwlSSzM1NzZfQ1JV X1JFU0VUX09GRlNFVChTUlNUX0NPVU5URVJfUFdNMSwgMjAsIDkpLAo+ICsJUkszNTc2X0NSVV9S RVNFVF9PRkZTRVQoU1JTVF9JM0MwLCAyMCwgMTIpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZT RVQoU1JTVF9JM0MxLCAyMCwgMTMpLAo+ICsKPiArCS8qIFNPRlRSU1RfQ09OMjEgKi8KPiArCVJL MzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9ERFJfTU9OX0NIMCwgMjEsIDEpLAo+ICsJUksz NTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX0REUl9CSVUsIDIxLCAyKSwKPiArCVJLMzU3Nl9D UlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9ERFJfVVBDVExfQ0gwLCAyMSwgMyksCj4gKwlSSzM1NzZf Q1JVX1JFU0VUX09GRlNFVChTUlNUX1RNX0REUl9NT05fQ0gwLCAyMSwgNCksCj4gKwlSSzM1NzZf Q1JVX1JFU0VUX09GRlNFVChTUlNUX0FfRERSX0JJVSwgMjEsIDUpLAo+ICsJUkszNTc2X0NSVV9S RVNFVF9PRkZTRVQoU1JTVF9ERklfQ0gwLCAyMSwgNiksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09G RlNFVChTUlNUX0REUl9NT05fQ0gwLCAyMSwgMTApLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZT RVQoU1JTVF9QX0REUl9IV0xQX0NIMCwgMjEsIDEzKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZG U0VUKFNSU1RfUF9ERFJfTU9OX0NIMSwgMjEsIDE0KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZG U0VUKFNSU1RfUF9ERFJfSFdMUF9DSDEsIDIxLCAxNSksCj4gKwo+ICsJLyogU09GVFJTVF9DT04y MiAqLwo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX0REUl9VUENUTF9DSDEsIDIy LCAwKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfVE1fRERSX01PTl9DSDEsIDIy LCAxKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfREZJX0NIMSwgMjIsIDIpLAo+ ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX0REUjAxX01TQ0gwLCAyMiwgMyksCj4g KwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0FfRERSMDFfTVNDSDEsIDIyLCA0KSwKPiAr CVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfRERSX01PTl9DSDEsIDIyLCA2KSwKPiArCVJL MzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfRERSX1NDUkFNQkxFX0NIMCwgMjIsIDkpLAo+ICsJ UkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9ERFJfU0NSQU1CTEVfQ0gxLCAyMiwgMTApLAo+ ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX0FIQjJBUEIsIDIyLCAxMiksCj4gKwlS SzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0hfQUhCMkFQQiwgMjIsIDEzKSwKPiArCVJLMzU3 Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9ERFJfQklVLCAyMiwgMTQpLAo+ICsJUkszNTc2X0NS VV9SRVNFVF9PRkZTRVQoU1JTVF9GX0REUl9DTTBfQ09SRSwgMjIsIDE1KSwKPiArCj4gKwkvKiBT T0ZUUlNUX0NPTjIzICovCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfRERSMDFf TVNDSDAsIDIzLCAxKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9ERFIwMV9N U0NIMSwgMjMsIDIpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9ERFJfVElNRVIw LCAyMywgNCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0REUl9USU1FUjEsIDIz LCA1KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfVF9XRFRfRERSLCAyMywgNiks Cj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfV0RULCAyMywgNyksCj4gKwlSSzM1 NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfVElNRVIsIDIzLCA4KSwKPiArCVJLMzU3Nl9DUlVf UkVTRVRfT0ZGU0VUKFNSU1RfVF9ERFJfQ00wX0pUQUcsIDIzLCA5KSwKPiArCVJLMzU3Nl9DUlVf UkVTRVRfT0ZGU0VUKFNSU1RfUF9ERFJfR1JGLCAyMywgMTEpLAo+ICsKPiArCS8qIFNPRlRSU1Rf Q09OMjUgKi8KPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfRERSX1VQQ1RMX0NIMCwg MjUsIDEpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX0REUl9VUENUTF8wX0NI MCwgMjUsIDIpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX0REUl9VUENUTF8x X0NIMCwgMjUsIDMpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX0REUl9VUENU TF8yX0NIMCwgMjUsIDQpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX0REUl9V UENUTF8zX0NIMCwgMjUsIDUpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX0RE Ul9VUENUTF80X0NIMCwgMjUsIDYpLAo+ICsKPiArCS8qIFNPRlRSU1RfQ09OMjYgKi8KPiArCVJL MzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfRERSX1VQQ1RMX0NIMSwgMjYsIDEpLAo+ICsJUksz NTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX0REUl9VUENUTF8wX0NIMSwgMjYsIDIpLAo+ICsJ UkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX0REUl9VUENUTF8xX0NIMSwgMjYsIDMpLAo+ ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX0REUl9VUENUTF8yX0NIMSwgMjYsIDQp LAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX0REUl9VUENUTF8zX0NIMSwgMjYs IDUpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX0REUl9VUENUTF80X0NIMSwg MjYsIDYpLAo+ICsKPiArCS8qIFNPRlRSU1RfQ09OMjcgKi8KPiArCVJLMzU3Nl9DUlVfUkVTRVRf T0ZGU0VUKFNSU1RfUkVGX1BWVFBMTF9ERFIsIDI3LCAwKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRf T0ZGU0VUKFNSU1RfUF9QVlRQTExfRERSLCAyNywgMSksCj4gKwo+ICsJLyogU09GVFJTVF9DT04y OCAqLwo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX1JLTk4wLCAyOCwgOSksCj4g KwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0FfUktOTjBfQklVLCAyOCwgMTEpLAo+ICsJ UkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9MX1JLTk4wX0JJVSwgMjgsIDEyKSwKPiArCj4g KwkvKiBTT0ZUUlNUX0NPTjI5ICovCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0Ff UktOTjEsIDI5LCAwKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQV9SS05OMV9C SVUsIDI5LCAyKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfTF9SS05OMV9CSVUs IDI5LCAzKSwKPiArCj4gKwkvKiBTT0ZUUlNUX0NPTjMxICovCj4gKwlSSzM1NzZfQ1JVX1JFU0VU X09GRlNFVChTUlNUX05QVV9EQVAsIDMxLCAwKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VU KFNSU1RfTF9OUFVTVUJTWVNfQklVLCAzMSwgMSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNF VChTUlNUX1BfTlBVVE9QX0JJVSwgMzEsIDkpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQo U1JTVF9QX05QVV9USU1FUiwgMzEsIDEwKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNS U1RfTlBVVElNRVIwLCAzMSwgMTIpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9O UFVUSU1FUjEsIDMxLCAxMyksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfTlBV X1dEVCwgMzEsIDE0KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfVF9OUFVfV0RU LCAzMSwgMTUpLAo+ICsKPiArCS8qIFNPRlRSU1RfQ09OMzIgKi8KPiArCVJLMzU3Nl9DUlVfUkVT RVRfT0ZGU0VUKFNSU1RfQV9SS05OX0NCVUYsIDMyLCAwKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRf T0ZGU0VUKFNSU1RfQV9SVkNPUkUwLCAzMiwgMSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNF VChTUlNUX1BfTlBVX0dSRiwgMzIsIDIpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JT VF9QX1BWVFBMTF9OUFUsIDMyLCAzKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1Rf TlBVX1BWVFBMTCwgMzIsIDQpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9IX05Q VV9DTTBfQklVLCAzMiwgNiksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0ZfTlBV X0NNMF9DT1JFLCAzMiwgNyksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1RfTlBV X0NNMF9KVEFHLCAzMiwgOCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0FfUktO TlRPUF9CSVUsIDMyLCAxMSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0hfUktO Tl9DQlVGLCAzMiwgMTIpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9IX1JLTk5U T1BfQklVLCAzMiwgMTMpLAo+ICsKPiArCS8qIFNPRlRSU1RfQ09OMzMgKi8KPiArCVJLMzU3Nl9D UlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9OVk1fQklVLCAzMywgMiksCj4gKwlSSzM1NzZfQ1JVX1JF U0VUX09GRlNFVChTUlNUX0FfTlZNX0JJVSwgMzMsIDMpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9P RkZTRVQoU1JTVF9TX0ZTUEksIDMzLCA2KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNS U1RfSF9GU1BJLCAzMywgNyksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0NfRU1N QywgMzMsIDgpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9IX0VNTUMsIDMzLCA5 KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQV9FTU1DLCAzMywgMTApLAo+ICsJ UkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9CX0VNTUMsIDMzLCAxMSksCj4gKwlSSzM1NzZf Q1JVX1JFU0VUX09GRlNFVChTUlNUX1RfRU1NQywgMzMsIDEyKSwKPiArCj4gKwkvKiBTT0ZUUlNU X0NPTjM0ICovCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfR1JGLCAzNCwgMSks Cj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfUEhQX0JJVSwgMzQsIDUpLAo+ICsJ UkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX1BIUF9CSVUsIDM0LCA5KSwKPiArCVJLMzU3 Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9QQ0lFMCwgMzQsIDEzKSwKPiArCVJLMzU3Nl9DUlVf UkVTRVRfT0ZGU0VUKFNSU1RfUENJRTBfUE9XRVJfVVAsIDM0LCAxNSksCj4gKwo+ICsJLyogU09G VFJTVF9DT04zNSAqLwo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX1VTQjNPVEcx LCAzNSwgMyksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0FfTU1VMCwgMzUsIDEx KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQV9TTFZfTU1VMCwgMzUsIDEzKSwK PiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQV9NTVUxLCAzNSwgMTQpLAo+ICsKPiAr CS8qIFNPRlRSU1RfQ09OMzYgKi8KPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQV9T TFZfTU1VMSwgMzYsIDApLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX1BDSUUx LCAzNiwgNyksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BDSUUxX1BPV0VSX1VQ LCAzNiwgOSksCj4gKwo+ICsJLyogU09GVFJTVF9DT04zNyAqLwo+ICsJUkszNTc2X0NSVV9SRVNF VF9PRkZTRVQoU1JTVF9SWE9PQjAsIDM3LCAwKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VU KFNSU1RfUlhPT0IxLCAzNywgMSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BN QUxJVkUwLCAzNywgMiksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BNQUxJVkUx LCAzNywgMyksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0FfU0FUQTAsIDM3LCA0 KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQV9TQVRBMSwgMzcsIDUpLAo+ICsJ UkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BU0lDMSwgMzcsIDYpLAo+ICsJUkszNTc2X0NS VV9SRVNFVF9PRkZTRVQoU1JTVF9BU0lDMCwgMzcsIDcpLAo+ICsKPiArCS8qIFNPRlRSU1RfQ09O NDAgKi8KPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9DU0lEUEhZMSwgNDAsIDIp LAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9TQ0FOX0NTSURQSFkxLCA0MCwgMyks Cj4gKwo+ICsJLyogU09GVFJTVF9DT040MiAqLwo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQo U1JTVF9QX1NER01BQ19HUkYsIDQyLCAzKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNS U1RfUF9TREdNQUNfQklVLCA0MiwgNCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNU X0FfU0RHTUFDX0JJVSwgNDIsIDUpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9I X1NER01BQ19CSVUsIDQyLCA2KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQV9H TUFDMCwgNDIsIDcpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX0dNQUMxLCA0 MiwgOCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfR01BQzAsIDQyLCA5KSwK PiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9HTUFDMSwgNDIsIDEwKSwKPiArCVJL MzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9TRElPLCA0MiwgMTIpLAo+ICsKPiArCS8qIFNP RlRSU1RfQ09ONDMgKi8KPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9TRE1NQzAs IDQzLCAyKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfU19GU1BJMSwgNDMsIDMp LAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9IX0ZTUEkxLCA0MywgNCksCj4gKwlS SzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0FfRFNNQ19CSVUsIDQzLCA2KSwKPiArCVJLMzU3 Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQV9EU01DLCA0MywgNyksCj4gKwlSSzM1NzZfQ1JVX1JF U0VUX09GRlNFVChTUlNUX1BfRFNNQywgNDMsIDgpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZT RVQoU1JTVF9IX0hTR1BJTywgNDMsIDEwKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNS U1RfSFNHUElPLCA0MywgMTEpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX0hT R1BJTywgNDMsIDEzKSwKPiArCj4gKwkvKiBTT0ZUUlNUX0NPTjQ1ICovCj4gKwlSSzM1NzZfQ1JV X1JFU0VUX09GRlNFVChTUlNUX0hfUktWREVDLCA0NSwgMyksCj4gKwlSSzM1NzZfQ1JVX1JFU0VU X09GRlNFVChTUlNUX0hfUktWREVDX0JJVSwgNDUsIDUpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9P RkZTRVQoU1JTVF9BX1JLVkRFQ19CSVUsIDQ1LCA2KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZG U0VUKFNSU1RfUktWREVDX0hFVkNfQ0EsIDQ1LCA4KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZG U0VUKFNSU1RfUktWREVDX0NPUkUsIDQ1LCA5KSwKPiArCj4gKwkvKiBTT0ZUUlNUX0NPTjQ3ICov Cj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0FfVVNCX0JJVSwgNDcsIDMpLAo+ICsJ UkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX1VTQlVGU19CSVUsIDQ3LCA0KSwKPiArCVJL MzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQV9VU0IzT1RHMCwgNDcsIDUpLAo+ICsJUkszNTc2 X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX1VGU19CSVUsIDQ3LCAxMCksCj4gKwlSSzM1NzZfQ1JV X1JFU0VUX09GRlNFVChTUlNUX0FfTU1VMiwgNDcsIDEyKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRf T0ZGU0VUKFNSU1RfQV9TTFZfTU1VMiwgNDcsIDEzKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZG U0VUKFNSU1RfQV9VRlNfU1lTLCA0NywgMTUpLAo+ICsKPiArCS8qIFNPRlRSU1RfQ09ONDggKi8K PiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQV9VRlMsIDQ4LCAwKSwKPiArCVJLMzU3 Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9VU0JVRlNfR1JGLCA0OCwgMSksCj4gKwlSSzM1NzZf Q1JVX1JFU0VUX09GRlNFVChTUlNUX1BfVUZTX0dSRiwgNDgsIDIpLAo+ICsKPiArCS8qIFNPRlRS U1RfQ09ONDkgKi8KPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9WUFVfQklVLCA0 OSwgNiksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0FfSlBFR19CSVUsIDQ5LCA3 KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQV9SR0FfQklVLCA0OSwgMTApLAo+ ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX1ZEUFBfQklVLCA0OSwgMTEpLAo+ICsJ UkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX0VCQ19CSVUsIDQ5LCAxMiksCj4gKwlSSzM1 NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0hfUkdBMkVfMCwgNDksIDEzKSwKPiArCVJLMzU3Nl9D UlVfUkVTRVRfT0ZGU0VUKFNSU1RfQV9SR0EyRV8wLCA0OSwgMTQpLAo+ICsJUkszNTc2X0NSVV9S RVNFVF9PRkZTRVQoU1JTVF9DT1JFX1JHQTJFXzAsIDQ5LCAxNSksCj4gKwo+ICsJLyogU09GVFJT VF9DT041MCAqLwo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX0pQRUcsIDUwLCAw KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9KUEVHLCA1MCwgMSksCj4gKwlS SzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0hfVkRQUCwgNTAsIDIpLAo+ICsJUkszNTc2X0NS VV9SRVNFVF9PRkZTRVQoU1JTVF9BX1ZEUFAsIDUwLCAzKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRf T0ZGU0VUKFNSU1RfQ09SRV9WRFBQLCA1MCwgNCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNF VChTUlNUX0hfUkdBMkVfMSwgNTAsIDUpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JT VF9BX1JHQTJFXzEsIDUwLCA2KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQ09S RV9SR0EyRV8xLCA1MCwgNyksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0hfRUJD LCA1MCwgMTApLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX0VCQywgNTAsIDEx KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfRF9FQkMsIDUwLCAxMiksCj4gKwo+ ICsJLyogU09GVFJTVF9DT041MSAqLwo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9I X1ZFUFUwX0JJVSwgNTEsIDIpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX1ZF UFUwX0JJVSwgNTEsIDMpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9IX1ZFUFUw LCA1MSwgNCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0FfVkVQVTAsIDUxLCA1 KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfVkVQVTBfQ09SRSwgNTEsIDYpLAo+ ICsKPiArCS8qIFNPRlRSU1RfQ09ONTMgKi8KPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNS U1RfQV9WSV9CSVUsIDUzLCAzKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9W SV9CSVUsIDUzLCA0KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9WSV9CSVUs IDUzLCA1KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfRF9WSUNBUCwgNTMsIDYp LAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX1ZJQ0FQLCA1MywgNyksCj4gKwlS SzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0hfVklDQVAsIDUzLCA4KSwKPiArCVJLMzU3Nl9D UlVfUkVTRVRfT0ZGU0VUKFNSU1RfSVNQMCwgNTMsIDEwKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRf T0ZGU0VUKFNSU1RfSVNQMF9WSUNBUCwgNTMsIDExKSwKPiArCj4gKwkvKiBTT0ZUUlNUX0NPTjU0 ICovCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0NPUkVfVlBTUywgNTQsIDEpLAo+ ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX0NTSV9IT1NUXzAsIDU0LCA0KSwKPiAr CVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9DU0lfSE9TVF8xLCA1NCwgNSksCj4gKwlS SzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfQ1NJX0hPU1RfMiwgNTQsIDYpLAo+ICsJUksz NTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX0NTSV9IT1NUXzMsIDU0LCA3KSwKPiArCVJLMzU3 Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9DU0lfSE9TVF80LCA1NCwgOCksCj4gKwo+ICsJLyog U09GVFJTVF9DT041OSAqLwo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9DSUZJTiwg NTksIDApLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9WSUNBUF9JMENMSywgNTks IDEpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9WSUNBUF9JMUNMSywgNTksIDIp LAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9WSUNBUF9JMkNMSywgNTksIDMpLAo+ ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9WSUNBUF9JM0NMSywgNTksIDQpLAo+ICsJ UkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9WSUNBUF9JNENMSywgNTksIDUpLAo+ICsKPiAr CS8qIFNPRlRSU1RfQ09ONjEgKi8KPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQV9W T1BfQklVLCA2MSwgNCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0FfVk9QMl9C SVUsIDYxLCA1KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9WT1BfQklVLCA2 MSwgNiksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfVk9QX0JJVSwgNjEsIDcp LAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9IX1ZPUCwgNjEsIDgpLAo+ICsJUksz NTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9BX1ZPUCwgNjEsIDkpLAo+ICsJUkszNTc2X0NSVV9S RVNFVF9PRkZTRVQoU1JTVF9EX1ZQMCwgNjEsIDEzKSwKPiArCj4gKwkvKiBTT0ZUUlNUX0NPTjYy ICovCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0RfVlAxLCA2MiwgMCksCj4gKwlS SzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0RfVlAyLCA2MiwgMSksCj4gKwlSSzM1NzZfQ1JV X1JFU0VUX09GRlNFVChTUlNUX1BfVk9QMl9CSVUsIDYyLCAyKSwKPiArCVJLMzU3Nl9DUlVfUkVT RVRfT0ZGU0VUKFNSU1RfUF9WT1BHUkYsIDYyLCAzKSwKPiArCj4gKwkvKiBTT0ZUUlNUX0NPTjYz ICovCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0hfVk8wX0JJVSwgNjMsIDUpLAo+ ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX1ZPMF9CSVUsIDYzLCA3KSwKPiArCVJL MzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQV9IRENQMF9CSVUsIDYzLCA5KSwKPiArCVJLMzU3 Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9WTzBfR1JGLCA2MywgMTApLAo+ICsJUkszNTc2X0NS VV9SRVNFVF9PRkZTRVQoU1JTVF9BX0hEQ1AwLCA2MywgMTIpLAo+ICsJUkszNTc2X0NSVV9SRVNF VF9PRkZTRVQoU1JTVF9IX0hEQ1AwLCA2MywgMTMpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZT RVQoU1JTVF9IRENQMCwgNjMsIDE0KSwKPiArCj4gKwkvKiBTT0ZUUlNUX0NPTjY0ICovCj4gKwlS SzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfRFNJSE9TVDAsIDY0LCA1KSwKPiArCVJLMzU3 Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfRFNJSE9TVDAsIDY0LCA2KSwKPiArCVJLMzU3Nl9DUlVf UkVTRVRfT0ZGU0VUKFNSU1RfUF9IRE1JVFgwLCA2NCwgNyksCj4gKwlSSzM1NzZfQ1JVX1JFU0VU X09GRlNFVChTUlNUX0hETUlUWDBfUkVGLCA2NCwgOSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09G RlNFVChTUlNUX1BfRURQMCwgNjQsIDEzKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNS U1RfRURQMF8yNE0sIDY0LCAxNCksCj4gKwo+ICsJLyogU09GVFJTVF9DT042NSAqLwo+ICsJUksz NTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9NX1NBSTVfOENILCA2NSwgNCksCj4gKwlSSzM1NzZf Q1JVX1JFU0VUX09GRlNFVChTUlNUX0hfU0FJNV84Q0gsIDY1LCA1KSwKPiArCVJLMzU3Nl9DUlVf UkVTRVRfT0ZGU0VUKFNSU1RfTV9TQUk2XzhDSCwgNjUsIDgpLAo+ICsJUkszNTc2X0NSVV9SRVNF VF9PRkZTRVQoU1JTVF9IX1NBSTZfOENILCA2NSwgOSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09G RlNFVChTUlNUX0hfU1BESUZfVFgyLCA2NSwgMTApLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZT RVQoU1JTVF9NX1NQRElGX1RYMiwgNjUsIDEzKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VU KFNSU1RfSF9TUERJRl9SWDIsIDY1LCAxNCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChT UlNUX01fU1BESUZfUlgyLCA2NSwgMTUpLAo+ICsKPiArCS8qIFNPRlRSU1RfQ09ONjYgKi8KPiAr CVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9TQUk4XzhDSCwgNjYsIDApLAo+ICsJUksz NTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9NX1NBSThfOENILCA2NiwgMiksCj4gKwo+ICsJLyog U09GVFJTVF9DT042NyAqLwo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9IX1ZPMV9C SVUsIDY3LCA1KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9WTzFfQklVLCA2 NywgNiksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX01fU0FJN184Q0gsIDY3LCA5 KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9TQUk3XzhDSCwgNjcsIDEwKSwK PiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9TUERJRl9UWDMsIDY3LCAxMSksCj4g KwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0hfU1BESUZfVFg0LCA2NywgMTIpLAo+ICsJ UkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9IX1NQRElGX1RYNSwgNjcsIDEzKSwKPiArCVJL MzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfTV9TUERJRl9UWDMsIDY3LCAxNCksCj4gKwo+ICsJ LyogU09GVFJTVF9DT042OCAqLwo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9EUDAs IDY4LCAwKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9WTzFfR1JGLCA2OCwg MiksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0FfSERDUDFfQklVLCA2OCwgMyks Cj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0FfSERDUDEsIDY4LCA0KSwKPiArCVJL MzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9IRENQMSwgNjgsIDUpLAo+ICsJUkszNTc2X0NS VV9SRVNFVF9PRkZTRVQoU1JTVF9IRENQMSwgNjgsIDYpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9P RkZTRVQoU1JTVF9IX1NBSTlfOENILCA2OCwgOSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNF VChTUlNUX01fU0FJOV84Q0gsIDY4LCAxMSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChT UlNUX01fU1BESUZfVFg0LCA2OCwgMTIpLAo+ICsJUkszNTc2X0NSVV9SRVNFVF9PRkZTRVQoU1JT VF9NX1NQRElGX1RYNSwgNjgsIDEzKSwKPiArCj4gKwkvKiBTT0ZUUlNUX0NPTjY5ICovCj4gKwlS SzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0dQVSwgNjksIDMpLAo+ICsJUkszNTc2X0NSVV9S RVNFVF9PRkZTRVQoU1JTVF9BX1NfR1BVX0JJVSwgNjksIDYpLAo+ICsJUkszNTc2X0NSVV9SRVNF VF9PRkZTRVQoU1JTVF9BX00wX0dQVV9CSVUsIDY5LCA3KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRf T0ZGU0VUKFNSU1RfUF9HUFVfQklVLCA2OSwgOSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNF VChTUlNUX1BfR1BVX0dSRiwgNjksIDEzKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNS U1RfR1BVX1BWVFBMTCwgNjksIDE0KSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1Rf UF9QVlRQTExfR1BVLCA2OSwgMTUpLAo+ICsKPiArCS8qIFNPRlRSU1RfQ09ONzIgKi8KPiArCVJL MzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQV9DRU5URVJfQklVLCA3MiwgNCksCj4gKwlSSzM1 NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0FfRE1BMkREUiwgNzIsIDUpLAo+ICsJUkszNTc2X0NS VV9SRVNFVF9PRkZTRVQoU1JTVF9BX0REUl9TSEFSRU1FTSwgNzIsIDYpLAo+ICsJUkszNTc2X0NS VV9SRVNFVF9PRkZTRVQoU1JTVF9BX0REUl9TSEFSRU1FTV9CSVUsIDcyLCA3KSwKPiArCVJLMzU3 Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9DRU5URVJfQklVLCA3MiwgOCksCj4gKwlSSzM1NzZf Q1JVX1JFU0VUX09GRlNFVChTUlNUX1BfQ0VOVEVSX0dSRiwgNzIsIDkpLAo+ICsJUkszNTc2X0NS VV9SRVNFVF9PRkZTRVQoU1JTVF9QX0RNQTJERFIsIDcyLCAxMCksCj4gKwlSSzM1NzZfQ1JVX1JF U0VUX09GRlNFVChTUlNUX1BfU0hBUkVNRU0sIDcyLCAxMSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VU X09GRlNFVChTUlNUX1BfQ0VOVEVSX0JJVSwgNzIsIDEyKSwKPiArCj4gKwkvKiBTT0ZUUlNUX0NP Tjc1ICovCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNFVChTUlNUX0xJTktTWU1fSERNSVRYUEhZ MCwgNzUsIDEpLAo+ICsKPiArCS8qIFNPRlRSU1RfQ09ONzggKi8KPiArCVJLMzU3Nl9DUlVfUkVT RVRfT0ZGU0VUKFNSU1RfRFAwX1BJWEVMQ0xLLCA3OCwgMSksCj4gKwlSSzM1NzZfQ1JVX1JFU0VU X09GRlNFVChTUlNUX1BIWV9EUDBfVFgsIDc4LCAyKSwKPiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZG U0VUKFNSU1RfRFAxX1BJWEVMQ0xLLCA3OCwgMyksCj4gKwlSSzM1NzZfQ1JVX1JFU0VUX09GRlNF VChTUlNUX0RQMl9QSVhFTENMSywgNzgsIDQpLAo+ICsKPiArCS8qIFNPRlRSU1RfQ09ONzkgKi8K PiArCVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9WRVBVMV9CSVUsIDc5LCAxKSwKPiAr CVJLMzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfQV9WRVBVMV9CSVUsIDc5LCAyKSwKPiArCVJL MzU3Nl9DUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9WRVBVMSwgNzksIDMpLAo+ICsJUkszNTc2X0NS VV9SRVNFVF9PRkZTRVQoU1JTVF9BX1ZFUFUxLCA3OSwgNCksCj4gKwlSSzM1NzZfQ1JVX1JFU0VU X09GRlNFVChTUlNUX1ZFUFUxX0NPUkUsIDc5LCA1KSwKPiArCj4gKwkvKiBQUExMX1NPRlRSU1Rf Q09OMDAgKi8KPiArCVJLMzU3Nl9QSFBDUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9QSFBQSFlfQ1JV LCAwLCAxKSwKPiArCVJLMzU3Nl9QSFBDUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9BUEIyQVNCX1NM Vl9DSElQX1RPUCwgMCwgMyksCj4gKwlSSzM1NzZfUEhQQ1JVX1JFU0VUX09GRlNFVChTUlNUX1Bf UENJRTJfQ09NQk9QSFkwLCAwLCA1KSwKPiArCVJLMzU3Nl9QSFBDUlVfUkVTRVRfT0ZGU0VUKFNS U1RfUF9QQ0lFMl9DT01CT1BIWTBfR1JGLCAwLCA2KSwKPiArCVJLMzU3Nl9QSFBDUlVfUkVTRVRf T0ZGU0VUKFNSU1RfUF9QQ0lFMl9DT01CT1BIWTEsIDAsIDcpLAo+ICsJUkszNTc2X1BIUENSVV9S RVNFVF9PRkZTRVQoU1JTVF9QX1BDSUUyX0NPTUJPUEhZMV9HUkYsIDAsIDgpLAo+ICsKPiArCS8q IFBQTExfU09GVFJTVF9DT04wMSAqLwo+ICsJUkszNTc2X1BIUENSVV9SRVNFVF9PRkZTRVQoU1JT VF9QQ0lFMF9QSVBFX1BIWSwgMSwgNSksCj4gKwlSSzM1NzZfUEhQQ1JVX1JFU0VUX09GRlNFVChT UlNUX1BDSUUxX1BJUEVfUEhZLCAxLCA4KSwKPiArCj4gKwkvKiBTRUNVUkVOU19TT0ZUUlNUX0NP TjAwICovCj4gKwlSSzM1NzZfU0VDVVJFTlNDUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9DUllQVE9f TlMsIDAsIDMpLAo+ICsJUkszNTc2X1NFQ1VSRU5TQ1JVX1JFU0VUX09GRlNFVChTUlNUX0hfVFJO R19OUywgMCwgNCksCj4gKwlSSzM1NzZfU0VDVVJFTlNDUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9P VFBDX05TLCAwLCA4KSwKPiArCVJLMzU3Nl9TRUNVUkVOU0NSVV9SRVNFVF9PRkZTRVQoU1JTVF9P VFBDX05TLCAwLCA5KSwKPiArCj4gKwkvKiBQTVUxX1NPRlRSU1RfQ09OMDAgKi8KPiArCVJLMzU3 Nl9QTVUxQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfSERQVFhfR1JGLCAwLCAwKSwKPiArCVJLMzU3 Nl9QTVUxQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfSERQVFhfQVBCLCAwLCAxKSwKPiArCVJLMzU3 Nl9QTVUxQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfTUlQSV9EQ1BIWSwgMCwgMiksCj4gKwlSSzM1 NzZfUE1VMUNSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX0RDUEhZX0dSRiwgMCwgMyksCj4gKwlSSzM1 NzZfUE1VMUNSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX0JPVDBfQVBCMkFTQiwgMCwgNCksCj4gKwlS SzM1NzZfUE1VMUNSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX0JPVDFfQVBCMkFTQiwgMCwgNSksCj4g KwlSSzM1NzZfUE1VMUNSVV9SRVNFVF9PRkZTRVQoU1JTVF9VU0IyREVCVUcsIDAsIDYpLAo+ICsJ UkszNTc2X1BNVTFDUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9DU0lQSFlfR1JGLCAwLCA3KSwKPiAr CVJLMzU3Nl9QTVUxQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfQ1NJUEhZLCAwLCA4KSwKPiArCVJL MzU3Nl9QTVUxQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfVVNCUEhZX0dSRl8wLCAwLCA5KSwKPiAr CVJLMzU3Nl9QTVUxQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfVVNCUEhZX0dSRl8xLCAwLCAxMCks Cj4gKwlSSzM1NzZfUE1VMUNSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX1VTQkRQX0dSRiwgMCwgMTEp LAo+ICsJUkszNTc2X1BNVTFDUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9VU0JEUFBIWSwgMCwgMTIp LAo+ICsJUkszNTc2X1BNVTFDUlVfUkVTRVRfT0ZGU0VUKFNSU1RfVVNCRFBfQ09NQk9fUEhZX0lO SVQsIDAsIDE1KSwKPiArCj4gKwkvKiBQTVUxX1NPRlRSU1RfQ09OMDEgKi8KPiArCVJLMzU3Nl9Q TVUxQ1JVX1JFU0VUX09GRlNFVChTUlNUX1VTQkRQX0NPTUJPX1BIWV9DTU4sIDEsIDApLAo+ICsJ UkszNTc2X1BNVTFDUlVfUkVTRVRfT0ZGU0VUKFNSU1RfVVNCRFBfQ09NQk9fUEhZX0xBTkUsIDEs IDEpLAo+ICsJUkszNTc2X1BNVTFDUlVfUkVTRVRfT0ZGU0VUKFNSU1RfVVNCRFBfQ09NQk9fUEhZ X1BDUywgMSwgMiksCj4gKwlSSzM1NzZfUE1VMUNSVV9SRVNFVF9PRkZTRVQoU1JTVF9NX01JUElf RENQSFksIDEsIDMpLAo+ICsJUkszNTc2X1BNVTFDUlVfUkVTRVRfT0ZGU0VUKFNSU1RfU19NSVBJ X0RDUEhZLCAxLCA0KSwKPiArCVJLMzU3Nl9QTVUxQ1JVX1JFU0VUX09GRlNFVChTUlNUX1NDQU5f Q1NJUEhZLCAxLCA1KSwKPiArCVJLMzU3Nl9QTVUxQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfVkND SU82X0lPQywgMSwgNiksCj4gKwlSSzM1NzZfUE1VMUNSVV9SRVNFVF9PRkZTRVQoU1JTVF9PVEdQ SFlfMCwgMSwgNyksCj4gKwlSSzM1NzZfUE1VMUNSVV9SRVNFVF9PRkZTRVQoU1JTVF9PVEdQSFlf MSwgMSwgOCksCj4gKwlSSzM1NzZfUE1VMUNSVV9SRVNFVF9PRkZTRVQoU1JTVF9IRFBUWF9JTklU LCAxLCA5KSwKPiArCVJLMzU3Nl9QTVUxQ1JVX1JFU0VUX09GRlNFVChTUlNUX0hEUFRYX0NNTiwg MSwgMTApLAo+ICsJUkszNTc2X1BNVTFDUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSERQVFhfTEFORSwg MSwgMTEpLAo+ICsJUkszNTc2X1BNVTFDUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSERNSVRYSFBELCAx LCAxMyksCj4gKwo+ICsJLyogUE1VMV9TT0ZUUlNUX0NPTjAyICovCj4gKwlSSzM1NzZfUE1VMUNS VV9SRVNFVF9PRkZTRVQoU1JTVF9NUEhZX0lOSVQsIDIsIDApLAo+ICsJUkszNTc2X1BNVTFDUlVf UkVTRVRfT0ZGU0VUKFNSU1RfUF9NUEhZX0dSRiwgMiwgMSksCj4gKwlSSzM1NzZfUE1VMUNSVV9S RVNFVF9PRkZTRVQoU1JTVF9QX1ZDQ0lPN19JT0MsIDIsIDMpLAo+ICsKPiArCS8qIFBNVTFfU09G VFJTVF9DT04wMyAqLwo+ICsJUkszNTc2X1BNVTFDUlVfUkVTRVRfT0ZGU0VUKFNSU1RfSF9QTVUx X0JJVSwgMywgOSksCj4gKwlSSzM1NzZfUE1VMUNSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX1BNVTFf TklVLCAzLCAxMCksCj4gKwlSSzM1NzZfUE1VMUNSVV9SRVNFVF9PRkZTRVQoU1JTVF9IX1BNVV9D TTBfQklVLCAzLCAxMSksCj4gKwlSSzM1NzZfUE1VMUNSVV9SRVNFVF9PRkZTRVQoU1JTVF9QTVVf Q00wX0NPUkUsIDMsIDEyKSwKPiArCVJLMzU3Nl9QTVUxQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BN VV9DTTBfSlRBRywgMywgMTMpLAo+ICsKPiArCS8qIFBNVTFfU09GVFJTVF9DT04wNCAqLwo+ICsJ UkszNTc2X1BNVTFDUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9DUlVfUE1VMSwgNCwgMSksCj4gKwlS SzM1NzZfUE1VMUNSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX1BNVTFfR1JGLCA0LCAzKSwKPiArCVJL MzU3Nl9QTVUxQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BfUE1VMV9JT0MsIDQsIDQpLAo+ICsJUksz NTc2X1BNVTFDUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9QTVUxV0RULCA0LCA1KSwKPiArCVJLMzU3 Nl9QTVUxQ1JVX1JFU0VUX09GRlNFVChTUlNUX1RfUE1VMVdEVCwgNCwgNiksCj4gKwlSSzM1NzZf UE1VMUNSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX1BNVVRJTUVSLCA0LCA3KSwKPiArCVJLMzU3Nl9Q TVUxQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BNVVRJTUVSMCwgNCwgOSksCj4gKwlSSzM1NzZfUE1V MUNSVV9SRVNFVF9PRkZTRVQoU1JTVF9QTVVUSU1FUjEsIDQsIDEwKSwKPiArCVJLMzU3Nl9QTVUx Q1JVX1JFU0VUX09GRlNFVChTUlNUX1BfUE1VMVBXTSwgNCwgMTEpLAo+ICsJUkszNTc2X1BNVTFD UlVfUkVTRVRfT0ZGU0VUKFNSU1RfUE1VMVBXTSwgNCwgMTIpLAo+ICsKPiArCS8qIFBNVTFfU09G VFJTVF9DT04wNSAqLwo+ICsJUkszNTc2X1BNVTFDUlVfUkVTRVRfT0ZGU0VUKFNSU1RfUF9JMkMw LCA1LCAxKSwKPiArCVJLMzU3Nl9QTVUxQ1JVX1JFU0VUX09GRlNFVChTUlNUX0kyQzAsIDUsIDIp LAo+ICsJUkszNTc2X1BNVTFDUlVfUkVTRVRfT0ZGU0VUKFNSU1RfU19VQVJUMSwgNSwgNSksCj4g KwlSSzM1NzZfUE1VMUNSVV9SRVNFVF9PRkZTRVQoU1JTVF9QX1VBUlQxLCA1LCA2KSwKPiArCVJL MzU3Nl9QTVUxQ1JVX1JFU0VUX09GRlNFVChTUlNUX1BETTAsIDUsIDEzKSwKPiArCVJLMzU3Nl9Q TVUxQ1JVX1JFU0VUX09GRlNFVChTUlNUX0hfUERNMCwgNSwgMTUpLAo+ICsKPiArCS8qIFBNVTFf U09GVFJTVF9DT04wNiAqLwo+ICsJUkszNTc2X1BNVTFDUlVfUkVTRVRfT0ZGU0VUKFNSU1RfTV9Q RE0wLCA2LCAwKSwKPiArCVJLMzU3Nl9QTVUxQ1JVX1JFU0VUX09GRlNFVChTUlNUX0hfVkFELCA2 LCAxKSwKPiArCj4gKwkvKiBQTVUxX1NPRlRSU1RfQ09OMDcgKi8KPiArCVJLMzU3Nl9QTVUxQ1JV X1JFU0VUX09GRlNFVChTUlNUX1BfUE1VMEdSRiwgNywgNCksCj4gKwlSSzM1NzZfUE1VMUNSVV9S RVNFVF9PRkZTRVQoU1JTVF9QX1BNVTBJT0MsIDcsIDUpLAo+ICsJUkszNTc2X1BNVTFDUlVfUkVT RVRfT0ZGU0VUKFNSU1RfUF9HUElPMCwgNywgNiksCj4gKwlSSzM1NzZfUE1VMUNSVV9SRVNFVF9P RkZTRVQoU1JTVF9EQl9HUElPMCwgNywgNyksCj4gK307Cj4gKwo+ICt2b2lkIHJrMzU3Nl9yc3Rf aW5pdChzdHJ1Y3QgZGV2aWNlX25vZGUgKm5wLCB2b2lkIF9faW9tZW0gKnJlZ19iYXNlKQo+ICt7 Cj4gKwlyb2NrY2hpcF9yZWdpc3Rlcl9zb2Z0cnN0X2x1dChucCwKPiArCQkJCSAgICAgIHJrMzU3 Nl9yZWdpc3Rlcl9vZmZzZXQsCj4gKwkJCQkgICAgICBBUlJBWV9TSVpFKHJrMzU3Nl9yZWdpc3Rl cl9vZmZzZXQpLAo+ICsJCQkJICAgICAgcmVnX2Jhc2UgKyBSSzM1NzZfU09GVFJTVF9DT04oMCks Cj4gKwkJCQkgICAgICBST0NLQ0hJUF9TT0ZUUlNUX0hJV09SRF9NQVNLKTsKPiArfQo+ICsKCl9f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkxpbnV4LXJvY2tj aGlwIG1haWxpbmcgbGlzdApMaW51eC1yb2NrY2hpcEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6 Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtcm9ja2NoaXAK