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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477632bda1asm27432985e9.3.2025.11.05.23.54.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 05 Nov 2025 23:54:07 -0800 (PST) Message-ID: Date: Thu, 6 Nov 2025 08:54:06 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 28/32] hw/arm/smmuv3-accel: Add property to specify OAS bits To: Jason Gunthorpe Cc: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org, peter.maydell@linaro.org, nicolinc@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org, zhenzhong.duan@intel.com, yi.l.liu@intel.com, kjaju@nvidia.com References: <20251031105005.24618-1-skolothumtho@nvidia.com> <20251031105005.24618-29-skolothumtho@nvidia.com> <49215c9d-feb1-4f72-bfe0-799572ecfac2@redhat.com> <20251104145041.GE1537560@nvidia.com> From: Eric Auger In-Reply-To: <20251104145041.GE1537560@nvidia.com> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: DmrBW6fdkHcIiq1DIJGMXyoExgSSwhAsZElkeJQ77C4_1762415648 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.517, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Hi Jason, On 11/4/25 3:50 PM, Jason Gunthorpe wrote: > On Tue, Nov 04, 2025 at 03:35:42PM +0100, Eric Auger wrote: >>> + /* >>> + * TODO: OAS is not something Linux kernel doc says meaningful for user. >>> + * But looks like OAS needs to be compatible for accelerator support. Please >>> + * check. >> would remove that comment. Either it is requested or not. >>> + */ >>> + if (FIELD_EX32(info->idr[5], IDR5, OAS) < >>> + FIELD_EX32(s->idr[5], IDR5, OAS)) { >>> + error_setg(errp, "Host SMMUv3 OAS(%d) bits not compatible", >>> + smmuv3_oas_bits(FIELD_EX32(info->idr[5], IDR5, OAS))); >> let's be more explicit then and say >> >> Host SMMUv3 OAS (%d bits) is less that OAS bits advertised by SMMU (%d) > It isn't OAS that is being checked here, this is now IPA. OAS is for > use by the hypervisor. > > When the guest looks at the vSMMU the "OAS" it sees is the IPS > supported by the HW. > > Aside from the raw HW limit, it also shouldn't exceed the configured > size of the S2 HWPT. > > So the above should refer to this detail because it is a bit subtle > that OAS and IPS are often the same. See "3.4 Address sizes" > > * IAS reflects the maximum usable IPA of an implementation that is > generated by stage 1 and input to stage 2: > > - This term is defined to illustrate the handling of intermediate > addresses in this section and is not a configurable parameter. > > - The maximum usable IPA size of an SMMU is defined in terms of other SMMU implementation choices, > as: > IAS = MAX(SMMU_IDR0.TTF[0]==1 ? 40 : 0), SMMU_IDR0.TTF[1]==1 ? OAS : 0)); > > - An IPA of 40 bits is required to support of AArch32 LPAE translations, and AArch64 limits the > maximum IPA size to the maximum PA size. Otherwise, when AArch32 LPAE is not implemented, the > IPA size equals OAS, the PA size, and might be smaller than 40 bits. > > - The purpose of definition of the IAS term is to abstract away from these implementation variables. Thank you for the clarification and pointer. I fully agree. maybe we can rephrase the error msg as: "Host SMMUv3 OAS (%d bits) is less that physical SMMU maximum usable IPA (%d)" which is more accurate despite in practice here we assimilate max IPA to OAS ( TTF[1]==1 case) Eric > > Jason >