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pr=C Message-ID: Date: Tue, 7 Nov 2023 12:23:02 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/2] xen/arm32: head: Introduce enable_{boot,secondary}_cpu_mm() Content-Language: en-US To: Ayan Kumar Halder , CC: , , , , , , Julien Grall References: <20231107110217.1827379-1-ayan.kumar.halder@amd.com> <20231107110217.1827379-2-ayan.kumar.halder@amd.com> From: Michal Orzel In-Reply-To: <20231107110217.1827379-2-ayan.kumar.halder@amd.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A1:EE_|MW4PR12MB6922:EE_ X-MS-Office365-Filtering-Correlation-Id: f7fde137-b1c6-4712-f33d-08dbdf83eef9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yeofc5IWU/ERHcueJr0W5tPvo6PXhksqhwWf0N/6IJcnqgNV4fhjjPz+VoPcUlJ3LvZqO0FV7nyJmbpv7ULKO7cNZAkZcyyJ0jKiE2JgYpxb+eEL95fsORNvK3N7sdaAjPbAE1BDfCpCwkmOcEacCwfPSs2+P4gmbBJKzgp9Zf1YUe6H3QA6x5SMsje7ZMJtlxKg/+1t3Cvbnuzwv6P30TBoob/NQ/o/cZt8sfrSRJezSm2qqJbyVF9gCk6IwNV+JJa1WJ73v9KNtJV8mUu5xb+/NRv+WroKFoV8J92huxhaSOSCt8go/qnFf9+NQr7A2KH3beZfst1M1EPJyVw6SG6vmPjndTUjyYXcQGAe3IAWhzy56PR2lLyLZxPXa63LREs03AYhm5jcgVuBF6xOgtiXk39OxeFyfhO+x6RUC2vZQU6vvxcoxvsQFJjRy++x75kpJTvBxEaYVac9yYFHkLZwLSO1mBprFHT7M/VarnQqwYm1S8H+ao7/1qcU0hL5P36Jn355WVxx8+GDwXJKGz3uijpc9sIe5dE3UFjJJgwoKZke+mOLQfci/Io2eGc1YJm1h/DcWlYpvfZNLFJ3YpcUkJ6U/+r9TKwUTwopwNR4c8bF1bXDHOzsSJ9NLvcmHLvvP7ykzsBAs9NRSQjkFX7RK8Z2yA7pAHOl1KMt7D4xpu+pJex/kt0Y3RHu3spFv/7RwLR5sPlIrHUa3EnjF3XnOBPQtiVH5x6OiPO+tjVGBY3rIIvEwGy5mEe4DGHOISqjQ3mvQVCnRMJ58SxDgY/cg/APTfbtK7HCdYd5qA/c3D+Xl2hJQGC1n0p1D+Q/OWCE62oMeMMFDvLyiPespw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(39860400002)(346002)(136003)(376002)(230922051799003)(1800799009)(64100799003)(451199024)(82310400011)(186009)(36840700001)(40470700004)(46966006)(40460700003)(40480700001)(478600001)(47076005)(83380400001)(426003)(336012)(26005)(2616005)(44832011)(36860700001)(8936002)(16576012)(2906002)(8676002)(316002)(4326008)(41300700001)(5660300002)(54906003)(110136005)(53546011)(70586007)(70206006)(36756003)(86362001)(31696002)(356005)(82740400003)(31686004)(81166007)(21314003)(43740500002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2023 11:23:14.5500 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f7fde137-b1c6-4712-f33d-08dbdf83eef9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6922 Hi Ayan, On 07/11/2023 12:02, Ayan Kumar Halder wrote: > All the MMU related functionality have been clubbed together in > enable_boot_cpu_mm() for booting primary cpu and enable_secondary_cpu_mm() for > booting secondary cpus. > This is done in preparation for moving the code related to MMU in MMU specific > file and in order to support non MMU cpus in future. > > This is based on d2f8df5b3ede ("xen/arm64: head.S: Introduce enable_{boot,secondary}_cpu_mm()"). > > Signed-off-by: Ayan Kumar Halder > Reviewed-by: Michal Orzel > Acked-by: Julien Grall > --- > > Changes from :- > > v1 - 1. Added a proper commit message. > 2. Some style and other fixes suggested in v1. > > v2 - 1. Updated the comment on top of enable_boot_cpu_mm() and > enable_secondary_cpu_mm() ie mentioned the input and output registers. > 2. Updated the comment inside enable_boot_cpu_mm(). > > xen/arch/arm/arm32/head.S | 102 ++++++++++++++++++++++++++++++-------- > 1 file changed, 80 insertions(+), 22 deletions(-) > > diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S > index 2d7e690bf5..2204ea6dce 100644 > --- a/xen/arch/arm/arm32/head.S > +++ b/xen/arch/arm/arm32/head.S > @@ -201,13 +201,11 @@ past_zImage: > > bl check_cpu_mode > bl cpu_init > - bl create_page_tables > > - /* Address in the runtime mapping to jump to after the MMU is enabled */ > mov_w lr, primary_switched > - b enable_mmu > + b enable_boot_cpu_mm > + > primary_switched: > - bl setup_fixmap > #ifdef CONFIG_EARLY_PRINTK > /* Use a virtual address to access the UART. */ > mov_w r11, EARLY_UART_VIRTUAL_ADDRESS > @@ -249,27 +247,11 @@ GLOBAL(init_secondary) > #endif > bl check_cpu_mode > bl cpu_init > - bl create_page_tables > > - /* Address in the runtime mapping to jump to after the MMU is enabled */ > mov_w lr, secondary_switched > - b enable_mmu > -secondary_switched: > - /* > - * Non-boot CPUs need to move on to the proper pagetables, which were > - * setup in prepare_secondary_mm. > - * > - * XXX: This is not compliant with the Arm Arm. > - */ > - mov_w r4, init_ttbr /* VA of HTTBR value stashed by CPU 0 */ > - ldrd r4, r5, [r4] /* Actual value */ > - dsb > - mcrr CP64(r4, r5, HTTBR) > - dsb > - isb > - flush_xen_tlb_local r0 > - pt_enforce_wxn r0 > + b enable_secondary_cpu_mm > > +secondary_switched: > #ifdef CONFIG_EARLY_PRINTK > /* Use a virtual address to access the UART. */ > mov_w r11, EARLY_UART_VIRTUAL_ADDRESS > @@ -692,6 +674,82 @@ ready_to_switch: > mov pc, lr > ENDPROC(switch_to_runtime_mapping) > > +/* > + * Enable mm (turn on the data cache and the MMU) for secondary CPUs. > + * The function will return to the virtual address provided in LR (e.g. the > + * runtime mapping). > + * > + * Inputs: > + * r9 : paddr(start) > + * r10: phys offset > + * lr : Virtual address to return to. > + * > + * Output: > + * r12: Was a temporary mapping created? > + * > + * Clobbers r0 - r6 > + */ > +enable_secondary_cpu_mm: > + mov r6, lr > + > + bl create_page_tables > + > + /* Address in the runtime mapping to jump to after the MMU is enabled */ > + mov_w lr, 1f > + b enable_mmu > +1: > + /* > + * Non-boot CPUs need to move on to the proper pagetables, which were > + * setup in prepare_secondary_mm. > + * > + * XXX: This is not compliant with the Arm Arm. > + */ > + mov_w r4, init_ttbr /* VA of HTTBR value stashed by CPU 0 */ > + ldrd r4, r5, [r4] /* Actual value */ > + dsb > + mcrr CP64(r4, r5, HTTBR) > + dsb > + isb > + flush_xen_tlb_local r0 > + pt_enforce_wxn r0 > + > + /* Return to the virtual address requested by the caller. */ > + mov pc, r6 > +ENDPROC(enable_secondary_cpu_mm) > + > +/* > + * Enable mm (turn on the data cache and the MMU) for the boot CPU. > + * The function will return to the virtual address provided in LR (e.g. the > + * runtime mapping). > + * > + * Inputs: > + * r9 : paddr(start) > + * r10: phys offset > + * lr : Virtual address to return to. > + * > + * Output: > + * r12: Was a temporary mapping created? > + * > + * Clobbers r0 - r6 > + */ > +enable_boot_cpu_mm: > + mov r6, lr > + > + bl create_page_tables > + > + /* Address in the runtime mapping to jump to after the MMU is enabled */ > + mov_w lr, 1f > + b enable_mmu > +1: > + /* > + * Prepare the fixmap. The function will return to the virtual address > + * requested by the caller. > + */ This comment should be above branch instruction and not here. ~Michal