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Content-Transfer-Encoding: base64 Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Ck9uIDI4LzAxLzIwMjAgMDg6NTksIEJlbiBEb29rcyB3cm90ZToKPiBPbiAyNy8wMS8yMDIwIDE5 OjIzLCBEbWl0cnkgT3NpcGVua28gd3JvdGU6Cj4+IDI3LjAxLjIwMjAgMjI6MjAsIERtaXRyeSBP c2lwZW5rbyDQv9C40YjQtdGCOgo+Pj4gMjQuMDEuMjAyMCAxOTo1MCwgSm9uIEh1bnRlciDQv9C4 0YjQtdGCOgo+Pj4+Cj4+Pj4gT24gMjMvMDEvMjAyMCAxOTozOCwgQmVuIERvb2tzIHdyb3RlOgo+ Pj4+PiBPbiAwNy8wMS8yMDIwIDAxOjM5LCBEbWl0cnkgT3NpcGVua28gd3JvdGU6Cj4+Pj4+PiAw Ni4wMS4yMDIwIDIyOjAwLCBCZW4gRG9va3Mg0L/QuNGI0LXRgjoKPj4+Pj4+PiBPbiAwNS8wMS8y MDIwIDEwOjUzLCBCZW4gRG9va3Mgd3JvdGU6Cj4+Pj4+Pj4+Cj4+Pj4+Pj4+Cj4+Pj4+Pj4+IE9u IDIwMjAtMDEtMDUgMDE6NDgsIERtaXRyeSBPc2lwZW5rbyB3cm90ZToKPj4+Pj4+Pj4+IDA1LjAx LjIwMjAgMDM6MDQsIEJlbiBEb29rcyDQv9C40YjQtdGCOgo+Pj4+Pj4+Pj4+IFtzbmlwXQo+Pj4+ Pj4+Pj4+Cj4+Pj4+Pj4+Pj4gSSd2ZSBqdXN0IGdvbmUgdGhyb3VnaCB0ZXN0aW5nLgo+Pj4+Pj4+ Pj4+Cj4+Pj4+Pj4+Pj4gU29tZSBzaW1wbGUgZGF0YSB0ZXN0cyBzaG93IDE2IGFuZCAzMi1iaXRz IHdvcmsuCj4+Pj4+Pj4+Pj4KPj4+Pj4+Pj4+PiBUaGUgMjQgYml0IGNhc2Ugc2VlbXMgdG8gYmUg d2VpcmQsIGl0IGxvb2tzIGxpa2UgdGhlIDI0LWJpdAo+Pj4+Pj4+Pj4+IGV4cGVjdHMKPj4+Pj4+ Pj4+PiAyNCBiaXQgc2FtcGxlcyBpbiAzMiBiaXQgd29yZHMuIEkgY2FuJ3Qgc2VlIGFueSBwYWNr aW5nCj4+Pj4+Pj4+Pj4gb3B0aW9ucyB0bwo+Pj4+Pj4+Pj4+IGRvIDI0IGJpdCBpbiAyNCBiaXQs IHNvIHdlIG1heSBoYXZlIHRvIHJlbW92ZSAyNCBiaXQgc2FtcGxlCj4+Pj4+Pj4+Pj4gc3VwcG9y dAo+Pj4+Pj4+Pj4+ICh3aGljaCBpcyBhIHNoYW1lKQo+Pj4+Pj4+Pj4+Cj4+Pj4+Pj4+Pj4gTXkg cHJlZmVyZW5jZSBpcyB0byByZW1vdmUgdGhlIDI0LWJpdCBzdXBwb3J0IGFuZCBrZWVwIHRoZSAz Mgo+Pj4+Pj4+Pj4+IGJpdCBpbi4KPj4+Pj4+Pj4+Pgo+Pj4+Pj4+Pj4KPj4+Pj4+Pj4+IEludGVy ZXN0aW5nLi4gSm9uLCBjb3VsZCB5b3UgcGxlYXNlIGNvbmZpcm0gdGhhdCAyNGJpdCBmb3JtYXQK Pj4+Pj4+Pj4+IGlzbid0Cj4+Pj4+Pj4+PiB1c2FibGUgb24gVDMwPwo+Pj4+Pj4+Pgo+Pj4+Pj4+ PiBJZiB0aGVyZSBpcyBhbiBvcHRpb24gb2YgMjQgcGFja2VkIGludG8gMzIsIHRoZW4gSSB0aGlu ayB0aGF0IHdvdWxkCj4+Pj4+Pj4+IHdvcmsuCj4+Pj4+Pj4+Cj4+Pj4+Pj4+IEkgY2FuIHRyeSB0 ZXN0aW5nIHRoYXQgd2l0aCByYXcgZGF0YSBvbiBNb25kYXkuCj4+Pj4+Pj4KPj4+Pj4+PiBJIG5l ZWQgdG8gY2hlY2sgc29tZSB0aGluZ3MsIEkgYXNzdW1lZCAyNCB3YXMgMjQgcGFja2VkIGJpdHMs IGl0Cj4+Pj4+Pj4gbG9va3MKPj4+Pj4+PiBsaWtlIHRoZSBkZWZhdWx0IGlzIDI0IGluIDMyIGJp dHMgc28gd2UgbWF5IGJlIG9rLiBIb3dldmVyIEkgbmVlZCB0bwo+Pj4+Pj4+IHJlLXdyaXRlIG15 IHRlc3QgY2FzZSB3aGljaCBhc3N1bWVkIGl0IHdhcyAyNGJpdHMgaW4gMyBieXRlcwo+Pj4+Pj4+ IChTMjRfM0xFKS4KPj4+Pj4+Pgo+Pj4+Pj4+IEknbGwgZm9sbG93IHVwIGxhdGVyLAo+Pj4+Pj4K Pj4+Pj4+IE9rYXksIHRoZSBTMjRfM0xFIGlzbid0IHN1cHBvcnRlZCBieSBSVDU2NDAgY29kZWMg aW4gbXkgY2FzZS4gSQo+Pj4+Pj4gYnJpZWZseQo+Pj4+Pj4gbG9va2VkIHRocm91Z2ggdGhlIFRS TSBkb2MgYW5kIGdvdCBpbXByZXNzaW9uIHRoYXQgQUhVQiBjb3VsZCByZS1wYWNrCj4+Pj4+PiBk YXRhIHN0cmVhbSBpbnRvIHNvbWV0aGluZyB0aGF0IGNvZGVjIHN1cHBvcnRzLCBidXQgbWF5YmUg aXQncyBhCj4+Pj4+PiB3cm9uZwo+Pj4+Pj4gaW1wcmVzc2lvbi4KPj4+Pj4+IF9fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fXwo+Pj4+Pgo+Pj4+PiBJIGRpZCBhIHF1aWNrIHRlc3Qgd2l0 aCB0aGUgZm9sbG93aW5nOgo+Pj4+Pgo+Pj4+PiDCoMKgc294IC1uIC1iIDE2IC1jIDIgLXIgNDQx MDAgL3RtcC90bXAud2F2wqAgc3ludGggc2luZSA1MDAgdm9sIDAuNQo+Pj4+PiDCoMKgc294IC1u IC1iIDI0IC1jIDIgLXIgNDQxMDAgL3RtcC90bXAud2F2wqAgc3ludGggc2luZSA1MDAgdm9sIDAu NQo+Pj4+PiDCoMKgc294IC1uIC1iIDMyIC1jIDIgLXIgNDQxMDAgL3RtcC90bXAud2F2wqAgc3lu dGggc2luZSA1MDAgdm9sIDAuNQo+Pj4+Pgo+Pj4+PiBUaGUgMTYgYW5kIDMyIHdvcmsgZmluZSwg dGhlIDI0IGlzIHNob3dpbmcgYSBwbGF5YmFjayBvdXRwdXQgZnJlcQo+Pj4+PiBvZiA0NDBIeiBp bnN0ZWFkIG9mIDUwMEh6Li4uIHRoaXMgc3VnZ2VzdHMgdGhlIGNsb2NrIGlzIG9mZiwgb3IgdGhl cmUKPj4+Pj4gaXMgc29tZXRoaW5nIGVsc2Ugd2VpcmQgZ29pbmcgb24uLi4KPj4+Pgo+Pj4+IEkg d2FzIGxvb2tpbmcgYXQgdXNpbmcgc294IHRvIGNyZWF0ZSBzdWNoIGFzIGZpbGUsIGJ1dCB0aGUg YWJvdmUKPj4+PiBjb21tYW5kCj4+Pj4gZ2VuZXJhdGVzIGEgUzI0XzNMRSBmaWxlIGFuZCBub3Qg UzI0X0xFIGZpbGUuIFRoZSBjb2RlYyBvbiBKZXRzb24tVEsxCj4+Pj4gc3VwcG9ydHMgUzI0X0xF IGJ1dCBkb2VzIG5vdCBzdXBwb3J0IFMyNF8zTEUgYW5kIHNvIEkgY2Fubm90IHRlc3QgdGhpcy4K Pj4+PiBBbnl3YXksIHdlIHJlYWxseSBuZWVkIHRvIHRlc3QgUzI0X0xFIGFuZCBub3QgUzI0XzNM RSBiZWNhdXNlIHRoaXMgaXMKPj4+PiB0aGUgcHJvYmxlbSB0aGF0IERtaXRyeSBpcyBoYXZpbmcu Cj4+Pj4KPj4+PiBCZW4gaXMgUzI0XzNMRSB3aGF0IHlvdSByZWFsbHkgbmVlZCB0byBzdXBwb3J0 Pwo+Pj4+Cj4+Pj4gRG1pdHJ5LCBkb2VzIHRoZSBmb2xsb3dpbmcgZml4IHlvdXIgcHJvYmxlbT8K Pj4+Pgo+Pj4+IGRpZmYgLS1naXQgYS9zb3VuZC9zb2MvdGVncmEvdGVncmEzMF9pMnMuYwo+Pj4+ IGIvc291bmQvc29jL3RlZ3JhL3RlZ3JhMzBfaTJzLmMKPj4+PiBpbmRleCBkYmVkM2M1NDA4ZTcu LjkyODQ1YzRiNjNmNCAxMDA2NDQKPj4+PiAtLS0gYS9zb3VuZC9zb2MvdGVncmEvdGVncmEzMF9p MnMuYwo+Pj4+ICsrKyBiL3NvdW5kL3NvYy90ZWdyYS90ZWdyYTMwX2kycy5jCj4+Pj4gQEAgLTE0 MCw3ICsxNDAsNyBAQCBzdGF0aWMgaW50IHRlZ3JhMzBfaTJzX2h3X3BhcmFtcyhzdHJ1Y3QKPj4+ PiBzbmRfcGNtX3N1YnN0cmVhbSAqc3Vic3RyZWFtLAo+Pj4+IMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgIGF1ZGlvX2JpdHMgPSBURUdSQTMwX0FVRElPQ0lGX0JJVFNfMTY7Cj4+Pj4g wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgc2FtcGxlX3NpemUgPSAxNjsKPj4+PiDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBicmVhazsKPj4+PiAtwqDCoMKgwqDCoMKg IGNhc2UgU05EUlZfUENNX0ZPUk1BVF9TMjRfTEU6Cj4+Pj4gK8KgwqDCoMKgwqDCoCBjYXNlIFNO RFJWX1BDTV9GT1JNQVRfUzI0XzNMRToKPj4+PiDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoCB2YWwgPSBURUdSQTMwX0kyU19DVFJMX0JJVF9TSVpFXzI0Owo+Pj4+IMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgIGF1ZGlvX2JpdHMgPSBURUdSQTMwX0FVRElPQ0lGX0JJVFNf MjQ7Cj4+Pj4gwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgc2FtcGxlX3NpemUgPSAy NDsKPj4+PiBAQCAtMzE4LDcgKzMxOCw3IEBAIHN0YXRpYyBjb25zdCBzdHJ1Y3Qgc25kX3NvY19k YWlfZHJpdmVyCj4+Pj4gdGVncmEzMF9pMnNfZGFpX3RlbXBsYXRlID0gewo+Pj4+IMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIC5jaGFubmVsc19tYXggPSAyLAo+Pj4+IMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIC5yYXRlcyA9IFNORFJWX1BDTV9SQVRFXzgwMDBfOTYw MDAsCj4+Pj4gwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgLmZvcm1hdHMgPSBTTkRS Vl9QQ01fRk1UQklUX1MzMl9MRSB8Cj4+Pj4gLcKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgIFNORFJWX1BDTV9GTVRCSVRfUzI0X0xFIHwKPj4+PiArwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgU05EUlZfUENN X0ZNVEJJVF9TMjRfM0xFIHwKPj4+PiDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqAgU05EUlZfUENNX0ZNVEJJVF9TMTZfTEUsCj4+Pj4gwqDCoMKg wqDCoMKgwqDCoCB9LAo+Pj4+IMKgwqDCoMKgwqDCoMKgwqAgLmNhcHR1cmUgPSB7Cj4+Pj4gQEAg LTMyNyw3ICszMjcsNyBAQCBzdGF0aWMgY29uc3Qgc3RydWN0IHNuZF9zb2NfZGFpX2RyaXZlcgo+ Pj4+IHRlZ3JhMzBfaTJzX2RhaV90ZW1wbGF0ZSA9IHsKPj4+PiDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoCAuY2hhbm5lbHNfbWF4ID0gMiwKPj4+PiDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoCAucmF0ZXMgPSBTTkRSVl9QQ01fUkFURV84MDAwXzk2MDAwLAo+Pj4+IMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIC5mb3JtYXRzID0gU05EUlZfUENNX0ZNVEJJ VF9TMzJfTEUgfAo+Pj4+IC3CoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoCBTTkRSVl9QQ01fRk1UQklUX1MyNF9MRSB8Cj4+Pj4gK8KgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIFNORFJWX1BDTV9GTVRCSVRfUzI0 XzNMRSB8Cj4+Pj4gwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgIFNORFJWX1BDTV9GTVRCSVRfUzE2X0xFLAo+Pj4+IMKgwqDCoMKgwqDCoMKgwqAg fSwKPj4+PiDCoMKgwqDCoMKgwqDCoMKgIC5vcHMgPSAmdGVncmEzMF9pMnNfZGFpX29wcywKPj4+ Pgo+Pj4+IEpvbgo+Pj4+Cj4+Pgo+Pj4gSXQgc2hvdWxkIHNvbHZlIHRoZSBwcm9ibGVtIGluIG15 IHBhcnRpY3VsYXIgY2FzZSwgYnV0IEknbSBub3Qgc3VyZSB0aGF0Cj4+PiB0aGUgc29sdXRpb24g aXMgY29ycmVjdC4KPj4+Cj4+PiBUaGUgdjUuNSBrZXJuZWwgaXMgcmVsZWFzZWQgbm93IHdpdGgg dGhlIGJyb2tlbiBhdWRpbyBhbmQgYXBwYXJlbnRseQo+Pj4gZ2V0dGluZyAyNGJpdCB0byB3b3Jr IHdvbid0IGJlIHRyaXZpYWwgKGlmIHBvc3NpYmxlIGF0IGFsbCkuIEJlbiwgY291bGQKPj4+IHlv dSBwbGVhc2Ugc2VuZCBhIHBhdGNoIHRvIGZpeCB2NS41IGJ5IHJlbW92aW5nIHRoZSBTMjQgc3Vw cG9ydAo+Pj4gYWR2ZXJ0aXNlbWVudCBmcm9tIHRoZSBkcml2ZXI/Cj4+Cj4+IEkgYWxzbyBzdXNw ZWN0IHRoYXQgczMyIG1heSBuZWVkIHNvbWUgZXh0cmEgcGF0Y2hlcyBhbmQgdGh1cyBjb3VsZCBi ZQo+PiB3b3J0aHdoaWxlIHRvIHN0b3AgYWR2ZXJ0aXNpbmcgaXQgYXMgd2VsbC4KPiAKPiBBcyBm YXIgYXMgSSBhbSBhd2FyZSB0aGF0IHdvcmtzIGFuZCB3ZSBjYW4gaGl0IHRoZSBhdWRpbyByYXRl cyBmb3IgaXQuCgpJIHJhbiBhIHRlc3Qgb24gVGVncmExMjQgSmV0c29uLVRLMSBhbmQgMjQtYml0 IHBsYXliYWNrIHNlZW1zIHRvIHdvcmsgYXMKQmVuIGhhcyBpbmRpY2F0ZWQuIFNvIEkgZG9uJ3Qg dGhpbmsgaXQgaXMgYnJva2VuLgoKQ2FuIHlvdSB0cnkgQmVuJ3MgdGVzdGNhc2Ugb24gVGVncmEz MCAoaWUuIGdlbmVyYXRlIGEgdG9uZSB1c2luZyBzb3ggYW5kCnVzZSBhcGxheSB0byBwbGF5KT8K CkpvbgoKLS0gCm52cHVibGljCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fCkFsc2EtZGV2ZWwgbWFpbGluZyBsaXN0CkFsc2EtZGV2ZWxAYWxzYS1wcm9qZWN0 Lm9yZwpodHRwczovL21haWxtYW4uYWxzYS1wcm9qZWN0Lm9yZy9tYWlsbWFuL2xpc3RpbmZvL2Fs c2EtZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jon Hunter Subject: Re: [alsa-devel] [Linux-kernel] [PATCH v5 2/7] ASoC: tegra: Allow 24bit and 32bit samples Date: Tue, 28 Jan 2020 13:19:17 +0000 Message-ID: References: <20191018154833.7560-1-ben.dooks@codethink.co.uk> <449bdc3c-bf82-7cc4-6704-440dd100ca3a@gmail.com> <5d3ae629-5d30-0930-5dd1-15161e64926e@codethink.co.uk> <9daeeb94-2b90-18b8-2e1e-daae5acf079d@gmail.com> <37beb96a-a525-c72f-a7e1-e9ef5d61f3b2@gmail.com> <29db3df4-6f51-7c0f-1eef-90171f1d233a@codethink.co.uk> <9a5447e2-155c-7e6e-b8f1-95523c6f42c6@gmail.com> <680e2dfd-6f4f-5c96-63b7-97520961dc82@gmail.com> <0e0cd260e39ad293edb881da1c565510@codethink.co.uk> <507dcd5a-672b-61ac-aa7f-af5ff01accff@codethink.co.uk> <28cafc56-095b-68c6-638d-270608a2983f@codethink.co.uk> <3d8544be-af20-f382-85fd-32183365267b@nvidia.com> <1b3c2af4-510e-306c-749a-efffc994b20a@gmail.com> <1aa6a4bf-10ea-001d-2d35-44494d9554f8@gmail.com> <62cea895-c1f1-a833-b63c-050642bb8a79@codethink.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <62cea895-c1f1-a833-b63c-050642bb8a79-4yDnlxn2s6sWdaTGBSpHTA@public.gmane.org> Content-Language: en-US Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Ben Dooks , Dmitry Osipenko Cc: linux-kernel-81qHHgoATdFT9dQujB1mzip2UmYkHbXO@public.gmane.org, alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org, Liam Girdwood , Takashi Iwai , Mark Brown , Thierry Reding , Edward Cragg , linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org On 28/01/2020 08:59, Ben Dooks wrote: > On 27/01/2020 19:23, Dmitry Osipenko wrote: >> 27.01.2020 22:20, Dmitry Osipenko =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >>> 24.01.2020 19:50, Jon Hunter =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >>>> >>>> On 23/01/2020 19:38, Ben Dooks wrote: >>>>> On 07/01/2020 01:39, Dmitry Osipenko wrote: >>>>>> 06.01.2020 22:00, Ben Dooks =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >>>>>>> On 05/01/2020 10:53, Ben Dooks wrote: >>>>>>>> >>>>>>>> >>>>>>>> On 2020-01-05 01:48, Dmitry Osipenko wrote: >>>>>>>>> 05.01.2020 03:04, Ben Dooks =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >>>>>>>>>> [snip] >>>>>>>>>> >>>>>>>>>> I've just gone through testing. >>>>>>>>>> >>>>>>>>>> Some simple data tests show 16 and 32-bits work. >>>>>>>>>> >>>>>>>>>> The 24 bit case seems to be weird, it looks like the 24-bit >>>>>>>>>> expects >>>>>>>>>> 24 bit samples in 32 bit words. I can't see any packing >>>>>>>>>> options to >>>>>>>>>> do 24 bit in 24 bit, so we may have to remove 24 bit sample >>>>>>>>>> support >>>>>>>>>> (which is a shame) >>>>>>>>>> >>>>>>>>>> My preference is to remove the 24-bit support and keep the 32 >>>>>>>>>> bit in. >>>>>>>>>> >>>>>>>>> >>>>>>>>> Interesting.. Jon, could you please confirm that 24bit format >>>>>>>>> isn't >>>>>>>>> usable on T30? >>>>>>>> >>>>>>>> If there is an option of 24 packed into 32, then I think that woul= d >>>>>>>> work. >>>>>>>> >>>>>>>> I can try testing that with raw data on Monday. >>>>>>> >>>>>>> I need to check some things, I assumed 24 was 24 packed bits, it >>>>>>> looks >>>>>>> like the default is 24 in 32 bits so we may be ok. However I need t= o >>>>>>> re-write my test case which assumed it was 24bits in 3 bytes >>>>>>> (S24_3LE). >>>>>>> >>>>>>> I'll follow up later, >>>>>> >>>>>> Okay, the S24_3LE isn't supported by RT5640 codec in my case. I >>>>>> briefly >>>>>> looked through the TRM doc and got impression that AHUB could re-pac= k >>>>>> data stream into something that codec supports, but maybe it's a >>>>>> wrong >>>>>> impression. >>>>>> _________________________________ >>>>> >>>>> I did a quick test with the following: >>>>> >>>>> =C2=A0=C2=A0sox -n -b 16 -c 2 -r 44100 /tmp/tmp.wav=C2=A0 synth sine = 500 vol 0.5 >>>>> =C2=A0=C2=A0sox -n -b 24 -c 2 -r 44100 /tmp/tmp.wav=C2=A0 synth sine = 500 vol 0.5 >>>>> =C2=A0=C2=A0sox -n -b 32 -c 2 -r 44100 /tmp/tmp.wav=C2=A0 synth sine = 500 vol 0.5 >>>>> >>>>> The 16 and 32 work fine, the 24 is showing a playback output freq >>>>> of 440Hz instead of 500Hz... this suggests the clock is off, or there >>>>> is something else weird going on... >>>> >>>> I was looking at using sox to create such as file, but the above >>>> command >>>> generates a S24_3LE file and not S24_LE file. The codec on Jetson-TK1 >>>> supports S24_LE but does not support S24_3LE and so I cannot test this= . >>>> Anyway, we really need to test S24_LE and not S24_3LE because this is >>>> the problem that Dmitry is having. >>>> >>>> Ben is S24_3LE what you really need to support? >>>> >>>> Dmitry, does the following fix your problem? >>>> >>>> diff --git a/sound/soc/tegra/tegra30_i2s.c >>>> b/sound/soc/tegra/tegra30_i2s.c >>>> index dbed3c5408e7..92845c4b63f4 100644 >>>> --- a/sound/soc/tegra/tegra30_i2s.c >>>> +++ b/sound/soc/tegra/tegra30_i2s.c >>>> @@ -140,7 +140,7 @@ static int tegra30_i2s_hw_params(struct >>>> snd_pcm_substream *substream, >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 audio_bits =3D TEGRA30_AUDIOCIF_BITS_16; >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 sample_size =3D 16; >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 break; >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case SNDRV_PCM_FORMAT_S24_LE: >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case SNDRV_PCM_FORMAT_S24_3LE: >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 val =3D TEGRA30_I2S_CTRL_BIT_SIZE_24; >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 audio_bits =3D TEGRA30_AUDIOCIF_BITS_24; >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 sample_size =3D 24; >>>> @@ -318,7 +318,7 @@ static const struct snd_soc_dai_driver >>>> tegra30_i2s_dai_template =3D { >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 .channels_max =3D 2, >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 .rates =3D SNDRV_PCM_RATE_8000_96000, >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 .formats =3D SNDRV_PCM_FMTBIT_S32_LE | >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 SNDRV_PCM_FMTBIT_S24_LE | >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 SNDRV_PCM_FMTBIT_S24_3LE | >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 SNDRV_PCM_FMTBIT_S16_LE, >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }, >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .capture =3D { >>>> @@ -327,7 +327,7 @@ static const struct snd_soc_dai_driver >>>> tegra30_i2s_dai_template =3D { >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 .channels_max =3D 2, >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 .rates =3D SNDRV_PCM_RATE_8000_96000, >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 .formats =3D SNDRV_PCM_FMTBIT_S32_LE | >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 SNDRV_PCM_FMTBIT_S24_LE | >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 SNDRV_PCM_FMTBIT_S24_3LE | >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 SNDRV_PCM_FMTBIT_S16_LE, >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }, >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .ops =3D &tegra30_i2s= _dai_ops, >>>> >>>> Jon >>>> >>> >>> It should solve the problem in my particular case, but I'm not sure tha= t >>> the solution is correct. >>> >>> The v5.5 kernel is released now with the broken audio and apparently >>> getting 24bit to work won't be trivial (if possible at all). Ben, could >>> you please send a patch to fix v5.5 by removing the S24 support >>> advertisement from the driver? >> >> I also suspect that s32 may need some extra patches and thus could be >> worthwhile to stop advertising it as well. >=20 > As far as I am aware that works and we can hit the audio rates for it. I ran a test on Tegra124 Jetson-TK1 and 24-bit playback seems to work as Ben has indicated. So I don't think it is broken. Can you try Ben's testcase on Tegra30 (ie. generate a tone using sox and use aplay to play)? Jon --=20 nvpublic