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([2a02:908:1256:79a0:224c:44a4:ecb8:82c2]) by smtp.gmail.com with ESMTPSA id dx24-20020a170906a85800b006fed93bf71fsm5931440ejb.18.2022.07.18.12.40.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 18 Jul 2022 12:40:21 -0700 (PDT) Message-ID: Date: Mon, 18 Jul 2022 21:40:20 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH] drm/amdgpu: fix scratch register access method in SRIOV Content-Language: en-US To: Gavin Wan , amd-gfx@lists.freedesktop.org References: <20220718193229.142120-1-Gavin.Wan@amd.com> From: =?UTF-8?Q?Christian_K=c3=b6nig?= In-Reply-To: <20220718193229.142120-1-Gavin.Wan@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Am 18.07.22 um 21:32 schrieb Gavin Wan: > The scratch register should be accessed through MMIO instead of RLCG > in SRIOV, since it being used in RLCG register access function. > > Fixes: 0e1314781b9c("drm/amdgpu: nuke dynamic gfx scratch reg allocation") > > Signed-off-by: Gavin Wan > Change-Id: I888cb3b96856583e764b35a098bcf8bff01ad90c Reviewed-by: Christian König > --- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index 5349ca4d19e3..c6e0f9313a7f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -987,23 +987,23 @@ static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, > static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) > { > struct amdgpu_device *adev = ring->adev; > + uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); > uint32_t tmp = 0; > unsigned i; > int r; > > - WREG32_SOC15(GC, 0, mmSCRATCH_REG0, 0xCAFEDEAD); > + WREG32(scratch, 0xCAFEDEAD); > r = amdgpu_ring_alloc(ring, 3); > if (r) > return r; > > amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); > - amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0) - > - PACKET3_SET_UCONFIG_REG_START); > + amdgpu_ring_write(ring, scratch - PACKET3_SET_UCONFIG_REG_START); > amdgpu_ring_write(ring, 0xDEADBEEF); > amdgpu_ring_commit(ring); > > for (i = 0; i < adev->usec_timeout; i++) { > - tmp = RREG32_SOC15(GC, 0, mmSCRATCH_REG0); > + tmp = RREG32(scratch); > if (tmp == 0xDEADBEEF) > break; > udelay(1);