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"p.zabel@pengutronix.de" , "matthias.bgg@gmail.com" , "chunkuang.hu@kernel.org" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" Cc: "linux-kernel@vger.kernel.org" , "linux-mediatek@lists.infradead.org" , =?UTF-8?B?U2luZ28gQ2hhbmcgKOW8teiIiOWciyk=?= , =?UTF-8?B?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= , "devicetree@vger.kernel.org" , =?UTF-8?B?TmFuY3kgTGluICjmnpfmrKPonqIp?= , Project_Global_Chrome_Upstream_Group , "linux-arm-kernel@lists.infradead.org" References: <20230614073125.17958-1-shawn.sung@mediatek.com> <20230614073125.17958-13-shawn.sung@mediatek.com> <4dca96de37b4e6e3321bc304df8bad678edfebc3.camel@mediatek.com> From: AngeloGioacchino Del Regno In-Reply-To: <4dca96de37b4e6e3321bc304df8bad678edfebc3.camel@mediatek.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230615_003738_585098_A04293E3 X-CRM114-Status: GOOD ( 18.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list 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rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH v2 12/15] soc: mediatek: Add MT8188 VDO1 reset bit map Content-Language: en-US To: =?UTF-8?B?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= , "p.zabel@pengutronix.de" , "matthias.bgg@gmail.com" , "chunkuang.hu@kernel.org" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" Cc: "linux-kernel@vger.kernel.org" , "linux-mediatek@lists.infradead.org" , =?UTF-8?B?U2luZ28gQ2hhbmcgKOW8teiIiOWciyk=?= , =?UTF-8?B?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= , "devicetree@vger.kernel.org" , =?UTF-8?B?TmFuY3kgTGluICjmnpfmrKPonqIp?= , Project_Global_Chrome_Upstream_Group , "linux-arm-kernel@lists.infradead.org" References: <20230614073125.17958-1-shawn.sung@mediatek.com> <20230614073125.17958-13-shawn.sung@mediatek.com> <4dca96de37b4e6e3321bc304df8bad678edfebc3.camel@mediatek.com> From: AngeloGioacchino Del Regno In-Reply-To: <4dca96de37b4e6e3321bc304df8bad678edfebc3.camel@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Il 15/06/23 08:01, Shawn Sung (宋孝謙) ha scritto: > Hi Angelo, > > Got it. Will fix this in the next version. > > Added a new define in mtk-mmsys.h: > #define MMSYS_RST_NR(bank, bit) ((bank * 32) + bit) > > And define the reset table as: > static const u8 mmsys_mt8188_vdo1_rst_tb[] = { > [MT8188_VDO1_RST_SMI_LARB2] = MMSYS_RST_NR(0, 0), > ... > [MT8188_VDO1_RST_VPP_MERGE2] = MMSYS_RST_NR(0, 11), > [MT8188_VDO1_RST_VPP_MERGE3] = MMSYS_RST_NR(1, 0), > ... > [MT8188_VDO1_RST_DISP_RSZ3] = MMSYS_RST_NR(1, 31), > [MT8188_VDO1_RST_HDR_VDO_FE0] = MMSYS_RST_NR(2, 0), > > ... > [MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] = MMSYS_RST_NR(2, 23), > }; > Okay, that's also good. Go on! Regards, Angelo > Thanks, > Hsiao Chien Sung > > On Wed, 2023-06-14 at 13:35 +0200, AngeloGioacchino Del Regno wrote: >> >> External email : Please do not click links or open attachments until >> you have verified the sender or the content. >> Il 14/06/23 09:31, Hsiao Chien Sung ha scritto: >>> Add MT8188 VDO1 reset bit map. >>> >>> Signed-off-by: Hsiao Chien Sung >>> --- >>> drivers/soc/mediatek/mt8188-mmsys.h | 57 >> +++++++++++++++++++++++++++++ >>> drivers/soc/mediatek/mtk-mmsys.c | 3 +- >>> 2 files changed, 59 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/soc/mediatek/mt8188-mmsys.h >> b/drivers/soc/mediatek/mt8188-mmsys.h >>> index c3e3c5cfe931..208d4dfedc1a 100644 >>> --- a/drivers/soc/mediatek/mt8188-mmsys.h >>> +++ b/drivers/soc/mediatek/mt8188-mmsys.h >>> @@ -144,6 +144,63 @@ static const u8 mmsys_mt8188_vdo0_rst_tb[] = { >>> [MT8188_VDO0_RST_DISP_RSZ0]= 31, >>> }; >>> >>> +static const u8 mmsys_mt8188_vdo1_rst_tb[] = { >>> +[MT8188_VDO1_RST_SMI_LARB2]= 0, >>> +[MT8188_VDO1_RST_SMI_LARB3]= 1, >>> +[MT8188_VDO1_RST_GALS]= 2, >>> +[MT8188_VDO1_RST_FAKE_ENG0]= 3, >>> +[MT8188_VDO1_RST_FAKE_ENG1]= 4, >>> +[MT8188_VDO1_RST_MDP_RDMA0]= 5, >>> +[MT8188_VDO1_RST_MDP_RDMA1]= 6, >>> +[MT8188_VDO1_RST_MDP_RDMA2]= 7, >>> +[MT8188_VDO1_RST_MDP_RDMA3]= 8, >>> +[MT8188_VDO1_RST_VPP_MERGE0]= 9, >>> +[MT8188_VDO1_RST_VPP_MERGE1]= 10, >>> +[MT8188_VDO1_RST_VPP_MERGE2]= 11, >>> +[MT8188_VDO1_RST_VPP_MERGE3]= 32 + 0, >> >> Works, but there's a better way. >> >> 32 + 0 means that you're using reset SW1 register, so you can do >> >> #define MT8188_MMSYS_RST_NR_PER_BANK32 >> #define MT8188_RST_SW1_OFFSETMT8188_MMSYS_RST_NR_PER_BANK >> #define MT8188_RST_SW2_OFFSETMT8188_MMSYS_RST_NR_PER_BANK * 2 >> >> [MT8188_VDO1_RST_VPP_MERGE3] = MT8188_RST_SW1_OFFSET + 0 >> [MT8188_VDO1_RST_VPP_MERGE4] = MT8188_RST_SW1_OFFSET + 0 >> ....... >> [MT8188_VDO1_RST_HDR_VDO_FE0] = MT8188_RST_SW2_OFFSET + 0 >> ...etc >> >> Reading this will make it clear that a certain reset bit is in a >> different >> (sequential or not) register. >> >> P.S.: If the RST_NR_PER_BANK is *not* MT8188 specific (as in, all >> reset registers >> for all SoCs are always 32 bits, which I believe is true), you could >> move that >> definition to mtk-mmsys.h as >> #define MMSYS_RST_NR_PER_BANK32 >> and then define the offsets in mt8188-mmsys.h as >> #define MT8188_RST_SW1_OFFSET MMSYS_RST_NR_PER_BANK >> .... etc >> >> Thanks, >> Angelo >> >>