Re: [Qemu-devel] [PATCH] sun4u: implement power device

[Marcel Apfelbaum <marcel@redhat.com>]

On 16/01/2018 22:05, Mark Cave-Ayland wrote:
> On 16/01/18 14:23, Marcel Apfelbaum wrote:
> 
>> Hi Philippe,
>>
>> On 16/01/2018 2:54, Philippe Mathieu-Daudé wrote:
>>> CC'ing PCI maintainers.
>>>
>>> Hi Mark,
>>>
>>> On 01/15/2018 05:58 PM, Mark Cave-Ayland wrote:
>>>> This inbuilt device contains a single 4-byte register, of which bit 24 is used
>>>> to power down the machine on a real Ultra 5.
>>>>
>>>> The power device exists at offset 0x724000 on a real machine, but due to the
>>>> current configuration of the BARs in QEMU it must be located lower in PCI IO
>>>> space.
>>> Is is some issue in pci_bar_address()?
>>>
>>
>> The QEMU IO layout:
>>
>>      /*
>>       * QEMU I/O address space usage:
>>       *   0000 - 0fff    legacy isa, pci config, pci root bus, ...
>>       *   1000 - 9fff    free
>>       *   a000 - afff    hotplug (cpu, pci via acpi, i440fx/piix only)
>>       *   b000 - bfff    power management (PORT_ACPI_PM_BASE)
>>       *                  [ qemu 1.4+ implements pci config registers
>>       *                    properly so guests can place the registers
>>       *                    where they want, on older versions its fixed ]
>>       *   c000 - ffff    free, traditionally used for pci io
>>       */
>>
>> As you can see we don't have IO address space over ffff.
> 
> Well that's not actually quite true - we use a separate ebus address space for the onboard devices (and that does have 
> 32-bit PCI IO accesses enabled), but the issue here is one of the sun4u PCI host/onboard device configuration rather 
> than anything to do with QEMU.
> 

Got it, thanks (the above is probably true only for x86 machines)
Marcel

> 
> ATB,
> 
> Mark.