Re: [PATCH v9 5/6] target/riscv: Update address modify functions to take into account pointer masking

[LIU Zhiwei <zhiwei_liu@linux.alibaba.com>]

On 2024/5/11 18:10, Alexey Baturo wrote:
> From: Alexey Baturo <baturo.alexey@gmail.com>
>
> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>   target/riscv/translate.c     | 22 ++++++++++++++++------
>   target/riscv/vector_helper.c | 13 +++++++++++++
>   2 files changed, 29 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 3f578d6dd8..da46e636f8 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -580,8 +580,10 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
>       TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
>   
>       tcg_gen_addi_tl(addr, src1, imm);
> -    if (get_address_xl(ctx) == MXL_RV32) {
> -        tcg_gen_ext32u_tl(addr, addr);
> +    if (ctx->addr_signed) {
> +        tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_width);
> +    } else {
> +        tcg_gen_extract_tl(addr, addr, 0, ctx->addr_width);
>       }
>   
>       return addr;
> @@ -594,8 +596,10 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
>       TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
>   
>       tcg_gen_add_tl(addr, src1, offs);
> -    if (get_xl(ctx) == MXL_RV32) {
> -        tcg_gen_ext32u_tl(addr, addr);
> +    if (ctx->addr_signed) {
> +        tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_width);
> +    } else {
> +        tcg_gen_extract_tl(addr, addr, 0, ctx->addr_width);
>       }
>       return addr;
>   }
> @@ -1188,8 +1192,14 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>       ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
>       ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
>       ctx->cs = cs;
> -    ctx->addr_width = 0;
> -    ctx->addr_signed = false;
> +    if (get_xl(ctx) == MXL_RV32) {
Maybe ctx->address_xl?
> +        ctx->addr_width = 32;
> +        ctx->addr_signed = false;
In tcg inline code, we have considered the XL. But
> +    } else {
> +        int pm_pmm = FIELD_EX32(tb_flags, TB_FLAGS, PM_PMM);
> +        ctx->addr_width = 64 - riscv_pm_get_pmlen(pm_pmm);
> +        ctx->addr_signed = FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND);
> +    }
>       ctx->ztso = cpu->cfg.ext_ztso;
>       ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
>       ctx->zero = tcg_constant_tl(0);
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 39ba2a09dd..28861cc509 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -104,6 +104,19 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz)
>   
>   static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
>   {

here, we don't process the MXL_RV32. We should process it explicitly here.

Zhiwei

> +    RISCVPmPmm pmm = riscv_pm_get_pmm(env);
> +    if (pmm == PMM_FIELD_DISABLED) {
> +        return addr;
> +    }
> +    int pmlen = riscv_pm_get_pmlen(pmm);
> +    bool signext = riscv_cpu_virt_mem_enabled(env);
> +    addr = addr << pmlen;
> +    /* sign/zero extend masked address by N-1 bit */
> +    if (signext) {
> +        addr = (target_long)addr >> pmlen;
> +    } else {
> +        addr = addr >> pmlen;
> +    }
>       return addr;
>   }
>