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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4255d8f4ab0sm3412107f8f.52.2025.10.02.05.31.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Oct 2025 05:31:15 -0700 (PDT) Message-ID: Date: Thu, 2 Oct 2025 14:31:14 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 07/27] hw/arm/smmuv3: Implement get_viommu_cap() callback To: Shameer Kolothum , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" Cc: "peter.maydell@linaro.org" , Jason Gunthorpe , Nicolin Chen , "ddutile@redhat.com" , "berrange@redhat.com" , Nathan Chen , Matt Ochs , "smostafa@google.com" , "wangzhou1@hisilicon.com" , "jiangkunkun@huawei.com" , "jonathan.cameron@huawei.com" , "zhangfei.gao@linaro.org" , "zhenzhong.duan@intel.com" , "yi.l.liu@intel.com" , "shameerkolothum@gmail.com" References: <20250929133643.38961-1-skolothumtho@nvidia.com> <20250929133643.38961-8-skolothumtho@nvidia.com> <55de40c2-7d33-4806-8eb0-e4dde8d0c84f@redhat.com> From: Eric Auger In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: jbE26rYB9QSnqsHugkZDulttzJb8QXLDxEdtGk9Syww_1759408277 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.451, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On 10/2/25 11:38 AM, Shameer Kolothum wrote: > >> -----Original Message----- >> From: Eric Auger >> Sent: 01 October 2025 18:37 >> To: Shameer Kolothum ; qemu- >> arm@nongnu.org; qemu-devel@nongnu.org >> Cc: peter.maydell@linaro.org; Jason Gunthorpe ; Nicolin >> Chen ; ddutile@redhat.com; berrange@redhat.com; >> Nathan Chen ; Matt Ochs ; >> smostafa@google.com; wangzhou1@hisilicon.com; >> jiangkunkun@huawei.com; jonathan.cameron@huawei.com; >> zhangfei.gao@linaro.org; zhenzhong.duan@intel.com; yi.l.liu@intel.com; >> shameerkolothum@gmail.com >> Subject: Re: [PATCH v4 07/27] hw/arm/smmuv3: Implement >> get_viommu_cap() callback >> >> External email: Use caution opening links or attachments >> >> >> Hi Shameer, >> >> On 9/29/25 3:36 PM, Shameer Kolothum wrote: >>> For accelerated SMMUv3, we need nested parent domain creation. Add the >>> callback support so that VFIO can create a nested parent. >>> >>> In the accelerated SMMUv3 case, the host SMMUv3 is configured in nested >>> mode (S1 + S2), and the guest owns the Stage-1 page table. Therefore, we >>> expose only Stage-1 to the guest to ensure it uses the correct page-table >>> format. >>> >>> Reviewed-by: Nicolin Chen >>> Signed-off-by: Shameer Kolothum >> >>> Signed-off-by: Shameer Kolothum >> Wonder if you shall keep both. I don't know the usage though but worth >> to check. > Hmm.. I don't know either for sure. What I followed here(I will double check) > is all the patches I had previously(v3) I kept all the S-by tags. That seems to be > a right thing to do and IIRC I have seen that previously as well. > >>> --- >>> hw/arm/smmuv3-accel.c | 13 +++++++++++++ >>> hw/arm/virt.c | 13 +++++++++++++ >>> 2 files changed, 26 insertions(+) >>> >>> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c >>> index 44410cfb2a..6b0e512d86 100644 >>> --- a/hw/arm/smmuv3-accel.c >>> +++ b/hw/arm/smmuv3-accel.c >>> @@ -10,6 +10,7 @@ >>> #include "qemu/error-report.h" >>> >>> #include "hw/arm/smmuv3.h" >>> +#include "hw/iommu.h" >>> #include "hw/pci/pci_bridge.h" >>> #include "hw/pci-host/gpex.h" >>> #include "hw/vfio/pci.h" >>> @@ -106,8 +107,20 @@ static AddressSpace >> *smmuv3_accel_find_add_as(PCIBus *bus, void *opaque, >>> } >>> } >>> >>> +static uint64_t smmuv3_accel_get_viommu_flags(void *opaque) >>> +{ >>> + /* >>> + * We return VIOMMU_FLAG_WANT_NESTING_PARENT to inform VFIO >> core to create a >>> + * nesting parent which is required for accelerated SMMUv3 support. >>> + * The real HW nested support should be reported from host SMMUv3 >> and if >>> + * it doesn't, the nesting parent allocation will fail anyway in VFIO core. >>> + */ >>> + return VIOMMU_FLAG_WANT_NESTING_PARENT; >>> +} >>> + >>> static const PCIIOMMUOps smmuv3_accel_ops = { >>> .get_address_space = smmuv3_accel_find_add_as, >>> + .get_viommu_flags = smmuv3_accel_get_viommu_flags, >>> }; >>> >>> void smmuv3_accel_init(SMMUv3State *s) >>> diff --git a/hw/arm/virt.c b/hw/arm/virt.c >>> index 02209fadcf..b533b0556e 100644 >>> --- a/hw/arm/virt.c >>> +++ b/hw/arm/virt.c >>> @@ -3073,6 +3073,19 @@ static void >> virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, >>> return; >>> } >>> >>> + if (object_property_get_bool(OBJECT(dev), "accel", &error_abort)) { >> This looks unrelated to the get_viommu_flags() addition and to me this >> shall be put in a separate patch of squashed in the patch that exposes >> the accel prop Thanks Eric > But my thought process was, without this we can't say the vIOMMU will support > the nesting parent. But then the flag seems to be indicating that vIOMMU "want" > nesting parent. So I guess we can move it for later. Yes that's my understanding too Eric > > Thanks, > Shameer