All of lore.kernel.org
 help / color / mirror / Atom feed
From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
To: Cezary Rojewski <cezary.rojewski@intel.com>,
	alsa-devel@alsa-project.org,  broonie@kernel.org
Cc: upstream@semihalf.com, harshapriya.n@intel.com, rad@semihalf.com,
	tiwai@suse.com, hdegoede@redhat.com,
	amadeuszx.slawinski@linux.intel.com, cujomalainey@chromium.org,
	lma@semihalf.com
Subject: Re: [PATCH 12/14] ASoC: Intel: avs: Power management
Date: Tue, 26 Apr 2022 17:18:31 -0500	[thread overview]
Message-ID: <da55736f-61a8-dbbc-7253-7e3da70931d1@linux.intel.com> (raw)
In-Reply-To: <20220426172346.3508411-13-cezary.rojewski@intel.com>



On 4/26/22 12:23, Cezary Rojewski wrote:
> To preserve power during sleep operations, handle suspend (S3),
> hibernation (S4) and runtime (RTD3) transitions. As flow for all of
> is shared, define common handlers to reduce code size.
> 
> Signed-off-by: Amadeusz Sławiński <amadeuszx.slawinski@linux.intel.com>
> Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
> ---
>  sound/soc/intel/avs/core.c | 125 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 125 insertions(+)
> 
> diff --git a/sound/soc/intel/avs/core.c b/sound/soc/intel/avs/core.c
> index 93180c22032d..c2f8fb87cfc2 100644
> --- a/sound/soc/intel/avs/core.c
> +++ b/sound/soc/intel/avs/core.c
> @@ -536,6 +536,128 @@ static void avs_pci_remove(struct pci_dev *pci)
>  	pm_runtime_get_noresume(&pci->dev);
>  }
>  
> +static int __maybe_unused avs_suspend_common(struct avs_dev *adev, bool low_power)

low_power is not used so....

> +{
> +	struct hdac_bus *bus = &adev->base.core;
> +	int ret;
> +
> +	flush_work(&adev->probe_work);
> +
> +	snd_hdac_ext_bus_link_power_down_all(bus);
> +
> +	ret = avs_ipc_set_dx(adev, AVS_MAIN_CORE_MASK, false);
> +	/*
> +	 * pm_runtime is blocked on DSP failure but system-wide suspend is not.
> +	 * Do not block entire system from suspending if that's the case.
> +	 */
> +	if (ret && ret != -EPERM) {
> +		dev_err(adev->dev, "set dx failed: %d\n", ret);
> +		return AVS_IPC_RET(ret);
> +	}
> +
> +	avs_dsp_op(adev, int_control, false);
> +	snd_hdac_ext_bus_ppcap_int_enable(bus, false);
> +
> +	ret = avs_dsp_core_disable(adev, AVS_MAIN_CORE_MASK);
> +	if (ret < 0) {
> +		dev_err(adev->dev, "core_mask %ld disable failed: %d\n", AVS_MAIN_CORE_MASK, ret);
> +		return ret;
> +	}
> +
> +	snd_hdac_ext_bus_ppcap_enable(bus, false);
> +	/* disable LP SRAM retention */
> +	avs_hda_power_gating_enable(adev, false);
> +	snd_hdac_bus_stop_chip(bus);
> +	/* disable CG when putting controller to reset */
> +	avs_hdac_clock_gating_enable(bus, false);
> +	snd_hdac_bus_enter_link_reset(bus);
> +	avs_hdac_clock_gating_enable(bus, true);
> +
> +	snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
> +
> +	return 0;
> +}
> +
> +static int __maybe_unused avs_resume_common(struct avs_dev *adev, bool low_power, bool purge)
> +{
> +	struct hdac_bus *bus = &adev->base.core;
> +	struct hdac_ext_link *hlink;
> +	int ret;
> +
> +	snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true);
> +	avs_hdac_bus_init_chip(bus, true);
> +
> +	snd_hdac_ext_bus_ppcap_enable(bus, true);
> +	snd_hdac_ext_bus_ppcap_int_enable(bus, true);
> +
> +	ret = avs_dsp_boot_firmware(adev, purge);
> +	if (ret < 0) {
> +		dev_err(adev->dev, "firmware boot failed: %d\n", ret);
> +		return ret;
> +	}
> +
> +	/* turn off the links that were off before suspend */
> +	list_for_each_entry(hlink, &bus->hlink_list, list) {
> +		if (!hlink->ref_count)
> +			snd_hdac_ext_bus_link_power_down(hlink);
> +	}
> +
> +	/* check dma status and clean up CORB/RIRB buffers */
> +	if (!bus->cmd_dma_state)
> +		snd_hdac_bus_stop_cmd_io(bus);
> +
> +	return 0;
> +}
> +
> +static int __maybe_unused avs_suspend(struct device *dev)
> +{
> +	return avs_suspend_common(to_avs_dev(dev), true);
> +}
> +
> +static int __maybe_unused avs_resume(struct device *dev)
> +{
> +	return avs_resume_common(to_avs_dev(dev), true, true);
> +}
> +
> +static int __maybe_unused avs_runtime_suspend(struct device *dev)
> +{
> +	return avs_suspend_common(to_avs_dev(dev), true);
> +}
> +
> +static int __maybe_unused avs_runtime_resume(struct device *dev)
> +{
> +	return avs_resume_common(to_avs_dev(dev), true, false);
> +}
> +
> +static int __maybe_unused avs_freeze(struct device *dev)
> +{
> +	return avs_suspend_common(to_avs_dev(dev), false);
> +}
> +static int __maybe_unused avs_thaw(struct device *dev)
> +{
> +	return avs_resume_common(to_avs_dev(dev), false, true);
> +}
> +
> +static int __maybe_unused avs_poweroff(struct device *dev)
> +{
> +	return avs_suspend_common(to_avs_dev(dev), false);
> +}
> +
> +static int __maybe_unused avs_restore(struct device *dev)
> +{
> +	return avs_resume_common(to_avs_dev(dev), false, true);
> +}
> +
> +static const struct dev_pm_ops avs_dev_pm = {
> +	.suspend = avs_suspend,
> +	.resume = avs_resume,

... all the 4 functions below seem unnecessary?

> +	.freeze = avs_freeze,
> +	.thaw = avs_thaw,
> +	.poweroff = avs_poweroff,
> +	.restore = avs_restore,

we've historically never used those, what drives this new usage?

on the SOF side, we've used prepare and complete, along with idle...


> +	SET_RUNTIME_PM_OPS(avs_runtime_suspend, avs_runtime_resume, NULL)
> +};
> +
>  static const struct pci_device_id avs_ids[] = {
>  	{ 0 }
>  };
> @@ -546,6 +668,9 @@ static struct pci_driver avs_pci_driver = {
>  	.id_table = avs_ids,
>  	.probe = avs_pci_probe,
>  	.remove = avs_pci_remove,
> +	.driver = {
> +		.pm = &avs_dev_pm,
> +	},
>  };
>  module_pci_driver(avs_pci_driver);
>  

  reply	other threads:[~2022-04-26 22:26 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-26 17:23 [PATCH 00/14] ASoC: Intel: avs: Driver core and PCM operations Cezary Rojewski
2022-04-26 17:23 ` [PATCH 01/14] ASoC: Intel: avs: Account for libraries when booting basefw Cezary Rojewski
2022-04-26 21:21   ` Pierre-Louis Bossart
2022-05-01  9:45     ` Cezary Rojewski
2022-05-06 15:25       ` Piotr Maziarz
2022-05-06 15:47         ` Pierre-Louis Bossart
2022-04-26 17:23 ` [PATCH 02/14] ASoC: Intel: avs: Generic soc component driver Cezary Rojewski
2022-04-26 21:33   ` Pierre-Louis Bossart
2022-05-01 10:45     ` Cezary Rojewski
2022-04-26 17:23 ` [PATCH 03/14] ASoC: Intel: avs: Generic PCM FE operations Cezary Rojewski
2022-04-26 17:23 ` [PATCH 04/14] ASoC: Intel: avs: non-HDA PCM BE operations Cezary Rojewski
2022-04-26 21:40   ` Pierre-Louis Bossart
2022-05-01 10:48     ` Cezary Rojewski
2022-04-26 17:23 ` [PATCH 05/14] ASoC: Intel: avs: HDA " Cezary Rojewski
2022-04-26 21:45   ` Pierre-Louis Bossart
2022-05-01 10:55     ` Cezary Rojewski
2022-04-26 17:23 ` [PATCH 06/14] ASoC: Intel: avs: Coredump and recovery flow Cezary Rojewski
2022-04-26 21:53   ` Pierre-Louis Bossart
2022-05-01 15:32     ` Cezary Rojewski
2022-05-02 13:53       ` Pierre-Louis Bossart
2022-04-26 17:23 ` [PATCH 07/14] ASoC: Intel: avs: Prepare for firmware tracing Cezary Rojewski
2022-04-26 17:23 ` [PATCH 08/14] ASoC: Intel: avs: D0ix power state support Cezary Rojewski
2022-04-26 21:58   ` Pierre-Louis Bossart
2022-04-29 14:19     ` Cezary Rojewski
2022-04-29 14:33       ` Cezary Rojewski
2022-04-26 17:23 ` [PATCH 09/14] ASoC: Intel: avs: Event tracing Cezary Rojewski
2022-04-26 17:23 ` [PATCH 10/14] ASoC: Intel: avs: Machine board registration Cezary Rojewski
2022-04-26 22:12   ` Pierre-Louis Bossart
2022-04-29 14:01     ` Cezary Rojewski
2022-05-04  9:41       ` Amadeusz Sławiński
2022-05-04 11:12         ` Cezary Rojewski
2022-05-04 11:26         ` Péter Ujfalusi
2022-05-04 12:33           ` Cezary Rojewski
2022-04-26 17:23 ` [PATCH 11/14] ASoC: Intel: avs: PCI driver implementation Cezary Rojewski
2022-04-26 17:23 ` [PATCH 12/14] ASoC: Intel: avs: Power management Cezary Rojewski
2022-04-26 22:18   ` Pierre-Louis Bossart [this message]
2022-04-29 13:44     ` Cezary Rojewski
2022-04-26 17:23 ` [PATCH 13/14] ASoC: Intel: avs: SKL-based platforms support Cezary Rojewski
2022-04-26 17:23 ` [PATCH 14/14] ASoC: Intel: avs: APL-based " Cezary Rojewski
2022-04-27  8:15 ` [PATCH 00/14] ASoC: Intel: avs: Driver core and PCM operations Cezary Rojewski

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=da55736f-61a8-dbbc-7253-7e3da70931d1@linux.intel.com \
    --to=pierre-louis.bossart@linux.intel.com \
    --cc=alsa-devel@alsa-project.org \
    --cc=amadeuszx.slawinski@linux.intel.com \
    --cc=broonie@kernel.org \
    --cc=cezary.rojewski@intel.com \
    --cc=cujomalainey@chromium.org \
    --cc=harshapriya.n@intel.com \
    --cc=hdegoede@redhat.com \
    --cc=lma@semihalf.com \
    --cc=rad@semihalf.com \
    --cc=tiwai@suse.com \
    --cc=upstream@semihalf.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.