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From: Segher Boessenkool <segher@kernel.crashing.org>
Subject: Re: [RFC/PATCH] powerpc: MPC7450 L2 HW cache flush feature utilization
Date: Thu, 14 Jun 2007 15:56:20 +0200
To: Vladislav Buzov <vbuzov@ru.mvista.com>
Cc: linuxppc-dev list <linuxppc-dev@ozlabs.org>
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> I read the MPC7450 reference manual and it describes a method to flush
> the cache using L2 hardware flushing feature. The cache flushing
> procedure consist of several steps and some of them are dictated by
> MPC7448 errata (www.freescale.com/files/32bit/doc/errata/MPC7448CE.pdf,
> Erratum no.3).

Are these errata 7448-only?  If not, I wonder what is
done on PowerMacs?

> First, I'm looking for a help and advice why the current _set_L2CR()
> implementation may not work for MPC7450 (namely 7448 with 1Mb L2 cache
> installed). Is it a bug in _set_L2CR()  or a hardware problem.

I think that if anyone here could answer this straight
away, the source code would have been fixed already ;-)

> I've
> mentioned above about MPC7450 hardware bug in L2 hardware flushing
> mechanism. May it be applicable to common cache flushing procedure 
> based
> on sequence of lwz/dcbf instructions?

Dunno, too lazy to download that PDF, perhaps you can
quote the relevant part?

> Second, Is this patch acceptable?

Looks reasonable enough to me...  if it works (on all
things considered "7450" by the kernel).

>  	/* TODO: use HW flush assist when available */

You want to get rid of this old comment though -- and
perhaps branch over the non-hardware-assisted cache
flushing code.


Segher