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[217.95.100.236]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e25828e3bsm5868372f8f.31.2026.10.21.07.51.09 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Oct 2026 07:51:09 -0700 (PDT) Message-ID: Date: Wed, 21 Oct 2026 16:51:07 +0200 X-Archived-By: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/9] hw/intc/arm_gicv5: Ignore low bits in IRS_IST_BASER.ADDR To: qemu-devel@nongnu.org References: <20260914160020.327787-1-peter.maydell@linaro.org> <20260914160020.327787-2-peter.maydell@linaro.org> From: Richard Henderson Content-Language: en-US In-Reply-To: <20260914160020.327787-2-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-17.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On 9/14/26 18:00, Peter Maydell wrote: > The IRS_IST_BASER.ADDR documentation says: > > For IRS_IST_CFGR.STRUCTURE = 0: > Bits[N:0] of the resulting address are 0 where N depends on the ISTSZ > and LPI_ID_BITS fields in IRS_IST_CFGR as follows: > N = Max(5, (ISTSZ + 1) + LPI_ID_BITS) > For IRS_IST_CFGR.STRUCTURE = 1: > > Bits[N:0] of the resulting address are 0 where N depends on L2SZ, > ISTSZ, and LPI_ID_BITS in IRS_IST_CFGR as follows: > N = Max(5, LPI_ID_BITS - ((10 - ISTSZ) + (2 * L2SZ)) + 2) > > This enforces that the IST is aligned to the size of the IST table, > or to a 64-byte boundary if the table is smaller than 64 bytes, even > if the guest programs the low bits in the ADDR field to specify an > insufficiently aligned address. > > We were missing this check, and instead trusted the guest-provided > address to be sufficiently aligned already; add the alignment > enforcement. > > The GICv5 spec defines the masking to be used with the expressions > quoted above, which work with the raw field values from the > IRS_IST_CFGR register; these simplify down to some straightforward > expressions based on the sanitized values we've already extracted > form those fields. You can get to the expressions we use here either > by working through the simplification of the GIC spec expressions, or > from first principles (the number of bits needed for the size of the > table in bytes is the number of bits that index it plus the number of > bits specifying the size of an individual table entry). > > Signed-off-by: Peter Maydell > --- > hw/intc/arm_gicv5.c | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) Reviewed-by: Richard Henderson r~