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Mon, 06 May 2024 04:32:33 -0700 (PDT) Message-ID: Date: Mon, 6 May 2024 13:32:32 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [XEN PATCH v2 5/5] x86/MCE: optional build of AMD/Intel MCE code Content-Language: en-US To: Sergiy Kibrik Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <47d32ecff7b915bd23b6d13b76cedf4b39db71a2.1714640459.git.Sergiy_Kibrik@epam.com> From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <47d32ecff7b915bd23b6d13b76cedf4b39db71a2.1714640459.git.Sergiy_Kibrik@epam.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 02.05.2024 11:21, Sergiy Kibrik wrote: > Separate Intel/AMD-specific MCE code using CONFIG_{INTEL,AMD} config options. > Now we can avoid build of mcheck code if support for specific platform is > intentionally disabled by configuration. > > Add default return value to init_nonfatal_mce_checker() routine -- in case > of a build with both AMD and INTEL options are off (e.g. randconfig). I'm afraid that, as before, I can't accept this as a justification for the addition. The addition likely is wanted, but perhaps in a separate up-front patch and explaining what's wrong when that's missing. > Also global Intel-specific variables lmce_support & cmci_support have to be > redefined if !INTEL, as they get checked in common code. Them being checked in common code may have different resolution strategies. The justification here imo is that, right now, both variables are only ever written by mce_intel.c. As mentioned for vmce_has_lmce(), there's nothing fundamentally preventing MCG_CAP from having respective bits set on a non- Intel CPU. > --- a/xen/arch/x86/cpu/mcheck/mce.h > +++ b/xen/arch/x86/cpu/mcheck/mce.h > @@ -40,7 +40,11 @@ enum mcheck_type { > }; > > extern uint8_t cmci_apic_vector; > +#ifdef CONFIG_INTEL > extern bool lmce_support; > +#else > +#define lmce_support (false) Nit: Neither here nor ... > @@ -120,7 +124,11 @@ DECLARE_PER_CPU(struct mca_banks *, poll_bankmask); > DECLARE_PER_CPU(struct mca_banks *, no_cmci_banks); > DECLARE_PER_CPU(struct mca_banks *, mce_clear_banks); > > +#ifdef CONFIG_INTEL > extern bool cmci_support; > +#else > +#define cmci_support (false) ... here parentheses are really needed. > --- a/xen/arch/x86/cpu/mcheck/non-fatal.c > +++ b/xen/arch/x86/cpu/mcheck/non-fatal.c > @@ -24,14 +24,20 @@ static int __init cf_check init_nonfatal_mce_checker(void) > * Check for non-fatal errors every MCE_RATE s > */ > switch (c->x86_vendor) { > +#ifdef CONFIG_AMD > case X86_VENDOR_AMD: > case X86_VENDOR_HYGON: > /* Assume we are on K8 or newer AMD or Hygon CPU here */ > amd_nonfatal_mcheck_init(c); > break; > +#endif > +#ifdef CONFIG_INTEL > case X86_VENDOR_INTEL: > intel_nonfatal_mcheck_init(c); > break; > +#endif > + default: > + return -ENODEV; > } > printk(KERN_INFO "mcheck_poll: Machine check polling timer started.\n"); > return 0; Along the lines of remarks on earlier patches, it would be a good opportunity here to add missing blank lines between non-fall-through case blocks. Jan