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Tue, 7 Jul 2026 08:40:48 +0000 Message-ID: Date: Tue, 7 Jul 2026 16:40:41 +0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 06/13] drm/amdgpu: add amdgpu_vm_update_leaves() To: christian.koenig@amd.com Cc: amd-gfx@lists.freedesktop.org, natalie.vock@gmx.de, Alexander.Deucher@amd.com, Felix.Kuehling@amd.com, Philip.Yang@amd.com, timur.kristof@gmail.com, Huang Rui , honghuan@amd.com References: <20260529114031.3714-1-christian.koenig@amd.com> <20260529114031.3714-7-christian.koenig@amd.com> Content-Language: en-US From: "Huang, Honglei" In-Reply-To: <20260529114031.3714-7-christian.koenig@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SI2PR02CA0014.apcprd02.prod.outlook.com (2603:1096:4:194::19) To CY8PR12MB7170.namprd12.prod.outlook.com (2603:10b6:930:5a::18) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY8PR12MB7170:EE_|SA1PR12MB999086:EE_ X-MS-Office365-Filtering-Correlation-Id: 2792e6a1-ad13-4d66-de42-08dedc0371ba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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> + struct amdgpu_vm_update_params params; > + bool is_compute_context; > struct amdgpu_bo *root; > uint64_t value, flags; > struct amdgpu_vm *vm; > + unsigned int idx; > int r; > > vm = amdgpu_vm_lock_by_pasid(adev, &root, pasid); > @@ -3029,24 +3031,46 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, > value = adev->dummy_page_addr; > flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE | > AMDGPU_PTE_WRITEABLE; > - > + /* On +gfx9 we can use the PRT functionality instead */ > + if (!adev->gmc.gmc_funcs->set_prt) { > + flags &= ~AMDGPU_PTE_VALID; > + flags |= AMDGPU_PTE_PRT; > + } > } else { > /* Let the hw retry silently on the PTE */ > value = 0; > } > > + if (!drm_dev_enter(adev_to_drm(adev), &idx)) { > + r = -ENODEV; > + goto error_unlock; > + } > + > + amdgpu_vm_eviction_lock(vm); > + if (vm->evicting) { > + r = -EBUSY; > + goto error_dev_exit; > + } > + > + memset(¶ms, 0, sizeof(params)); > + params.adev = adev; > + params.vm = vm; > + params.immediate = true; > + params.pages_addr = NULL; > + > r = dma_resv_reserve_fences(root->tbo.base.resv, 1); > if (r) { > pr_debug("failed %d to reserve fence slot\n", r); > - goto error_unlock; > + goto error_eviction_lock; > } > > - r = amdgpu_vm_update_range(adev, vm, true, false, false, false, > - NULL, addr, addr, flags, value, 0, NULL, NULL, NULL); > - if (r) > - goto error_unlock; > + amdgpu_vm_update_leaves(¶ms, addr, addr, value, flags); Maybe need add prepare and commit flow? see diff: @@ -3118,6 +3118,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, params.vm = vm; params.immediate = true; params.pages_addr = NULL; + INIT_LIST_HEAD(¶ms.tlb_flush_waitlist); r = amdgpu_vm_begin_critical(¶ms); if (r) @@ -3129,9 +3130,16 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, goto error_end_critical; } + r = vm->update_funcs->prepare(¶ms, NULL, + AMDGPU_KERNEL_JOB_ID_VM_UPDATE); + if (r) + goto error_end_critical; + /* update_leaves uses exclusive end; we want a single PTE at @addr */ amdgpu_vm_update_leaves(¶ms, addr, addr + 1, value, flags); + r = vm->update_funcs->commit(¶ms, NULL); + Regards, Honglei > > - r = amdgpu_vm_update_pdes(adev, vm, true); > +error_eviction_lock: > + amdgpu_vm_eviction_unlock(vm); > + > +error_dev_exit: > + drm_dev_exit(idx); > > error_unlock: > amdgpu_bo_unreserve(root); > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > index cc096c005e34..04b32accfa3f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > @@ -613,6 +613,9 @@ int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params, > int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, > uint64_t start, uint64_t end, > uint64_t dst, uint64_t flags); > +void amdgpu_vm_update_leaves(struct amdgpu_vm_update_params *params, > + uint64_t start, uint64_t end, > + int64_t dst, uint64_t flags); > void amdgpu_vm_pt_free_work(struct work_struct *work); > void amdgpu_vm_pt_free_list(struct amdgpu_device *adev, > struct amdgpu_vm_update_params *params); > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c > index e43a60d09808..9766b6b9aecc 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c > @@ -790,6 +790,8 @@ int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, > uint64_t dst, uint64_t flags) > { > struct amdgpu_device *adev = params->adev; > + struct amdgpu_vm *vm = params->vm; > + pid_t tgid = vm->task_info ? vm->task_info->tgid : 0; > struct amdgpu_vm_pt_cursor cursor; > uint64_t frag_start = start, frag_end; > unsigned int frag; > @@ -881,7 +883,6 @@ int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, > entry_end = min(entry_end, end); > > do { > - struct amdgpu_vm *vm = params->vm; > uint64_t upd_end = min(entry_end, frag_end); > unsigned int nptes = (upd_end - frag_start) >> shift; > uint64_t upd_flags = flags | AMDGPU_PTE_FRAG(frag); > @@ -893,8 +894,7 @@ int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, > > trace_amdgpu_vm_update_ptes(params, frag_start, upd_end, > min(nptes, 32u), dst, incr, > - upd_flags, > - vm->task_info ? vm->task_info->tgid : 0, > + upd_flags, tgid, > vm->immediate.fence_context); > amdgpu_vm_pte_update_flags(params, to_amdgpu_bo_vm(pt), > cursor.level, pe_start, dst, > @@ -938,6 +938,71 @@ int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, > return 0; > } > > +/** > + * amdgpu_vm_update_leaves - update leave PDEs/PTEs > + * > + * @params: see amdgpu_vm_update_params definition > + * @start: start of GPU address range > + * @end: end of GPU address range > + * @dst: destination address to insert into the leave PDEs/PTEs > + * @flags: mapping flags > + * > + * Update the leave PDEs/PTEs in the range @start - @end without allocating or > + * freeing page tables. > + * > + * Returns: > + * 0 for success, negative error code for failure. > + */ > +void amdgpu_vm_update_leaves(struct amdgpu_vm_update_params *params, > + uint64_t start, uint64_t end, > + int64_t dst, uint64_t flags) > +{ > + struct amdgpu_device *adev = params->adev; > + struct amdgpu_vm *vm = params->vm; > + pid_t tgid = vm->task_info ? vm->task_info->tgid : 0; > + struct amdgpu_vm_pt_cursor cursor; > + > + amdgpu_vm_pt_start(adev, params->vm, start, &cursor); > + while (cursor.pfn < end) { > + unsigned int shift, mask; > + uint64_t entry_end, pe_start; > + struct amdgpu_bo *pt; > + unsigned int nptes; > + > + /* Walk to the leave entries */ > + if (amdgpu_vm_pt_descendant(adev, &cursor)) > + continue; > + > + pt = cursor.parent->bo; > + shift = amdgpu_vm_pt_level_shift(adev, cursor.level - 1); > + mask = amdgpu_vm_pt_entries_mask(adev, cursor.level - 1); > + > + /* Looks good so far, calculate parameters for the update */ > + pe_start = ((cursor.pfn >> shift) & mask) * 8; > + > + entry_end = ((uint64_t)mask + 1) << shift; > + entry_end += cursor.pfn & ~(entry_end - 1); > + entry_end = min(entry_end, end); > + > + nptes = (entry_end - cursor.pfn) >> shift; > + /* > + * This can happen when we set higher level PDEs to unmap and/or > + * silent to stop fault floods. > + */ > + nptes = max(nptes, 1u); > + > + trace_amdgpu_vm_update_ptes(params, cursor.pfn, entry_end, > + min(nptes, 32u), dst, 0, flags, > + tgid, > + vm->immediate.fence_context); > + amdgpu_vm_pte_update_flags(params, to_amdgpu_bo_vm(pt), > + cursor.level - 1, pe_start, dst, > + nptes, 0, flags); > + > + amdgpu_vm_pt_next(adev, &cursor); > + } > +} > + > /** > * amdgpu_vm_pt_map_tables - have bo of root PD cpu accessible > * @adev: amdgpu device structure