From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp4.osuosl.org (smtp4.osuosl.org [140.211.166.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0EF6AC369D9 for ; Tue, 29 Apr 2025 03:37:06 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp4.osuosl.org (Postfix) with ESMTP id 8A8B5403EC; Tue, 29 Apr 2025 03:37:06 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp4.osuosl.org ([127.0.0.1]) by localhost (smtp4.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id gBJFByoL-VVf; Tue, 29 Apr 2025 03:37:05 +0000 (UTC) X-Comment: SPF check N/A for local connections - client-ip=140.211.166.142; helo=lists1.osuosl.org; envelope-from=intel-wired-lan-bounces@osuosl.org; receiver= DKIM-Filter: OpenDKIM Filter v2.11.0 smtp4.osuosl.org 2B070403BD DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=osuosl.org; s=default; t=1745897825; bh=8/vIV67PmACAkGn6XKFeocjiUfJ9TpwART6PyHAiWmA=; h=Date:To:Cc:References:From:In-Reply-To:Subject:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=bwixnokikJ34MgImzqreFel8KF55W7fFjNsdl0NVhB5MR/3to9AHv+vPoFrZhkBkx Gl6cJ2Zv0K4zlU2+Y2ofDvslYaX/fKhuaZbYKQNDfQu40/vrq78451RSUXgDCsPLpo VMJiLOh6lRGUQ/mUHVat5tURmPvNc025bCtbVVQPj6f0O4hllvd4eTHIpBQqGXOHfO FXK5mBz3ivXAYqy32BWbfnZWB9pqaSAq2EQ1xzHL1RfRJJgWIkDCC1GRW8SEwkgVUU ut7f3q3u6aHg9h6upy16qBF1ZCSmB17QYcXuTCMNyNgkDd9NzL5QKzJo9WfuWl0wIS S21E3SmlBVqwQ== Received: from lists1.osuosl.org (lists1.osuosl.org [140.211.166.142]) by smtp4.osuosl.org (Postfix) with ESMTP id 2B070403BD; Tue, 29 Apr 2025 03:37:05 +0000 (UTC) Received: from smtp2.osuosl.org (smtp2.osuosl.org [IPv6:2605:bc80:3010::133]) by lists1.osuosl.org (Postfix) with ESMTP id A92A11E3 for ; Tue, 29 Apr 2025 03:37:04 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp2.osuosl.org (Postfix) with ESMTP id 8FD5540198 for ; Tue, 29 Apr 2025 03:37:04 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp2.osuosl.org ([127.0.0.1]) by localhost (smtp2.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id QrUYzCavofZN for ; Tue, 29 Apr 2025 03:37:04 +0000 (UTC) Received-SPF: None (mailfrom) identity=mailfrom; client-ip=198.175.65.16; helo=mgamail.intel.com; envelope-from=faizal.abdul.rahim@linux.intel.com; receiver= DMARC-Filter: OpenDMARC Filter v1.4.2 smtp2.osuosl.org 93421400C1 DKIM-Filter: OpenDKIM Filter v2.11.0 smtp2.osuosl.org 93421400C1 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by smtp2.osuosl.org (Postfix) with ESMTPS id 93421400C1 for ; Tue, 29 Apr 2025 03:37:03 +0000 (UTC) X-CSE-ConnectionGUID: QV12eqQjSnOAsaOdL6fEpw== X-CSE-MsgGUID: nYybN2o2Tb2l491C+f98GA== X-IronPort-AV: E=McAfee;i="6700,10204,11417"; a="47598867" X-IronPort-AV: E=Sophos;i="6.15,248,1739865600"; d="scan'208";a="47598867" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2025 20:37:02 -0700 X-CSE-ConnectionGUID: 0qgXs45zTyKuUWwhvF7+ug== X-CSE-MsgGUID: 5bB2k/8qQU22LGzgpyvGdw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,248,1739865600"; d="scan'208";a="156932012" Received: from mohdfai2-mobl.gar.corp.intel.com (HELO [10.247.22.166]) ([10.247.22.166]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2025 20:37:00 -0700 Message-ID: Date: Tue, 29 Apr 2025 11:36:43 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird To: "Ruinskiy, Dima" , Tony Nguyen , Przemek Kitszel , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Chwee-Lin Choong References: <20250428060225.1306986-1-faizal.abdul.rahim@linux.intel.com> <20250428060225.1306986-2-faizal.abdul.rahim@linux.intel.com> Content-Language: en-US From: "Abdul Rahim, Faizal" In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1745897824; x=1777433824; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=J8ow/rnNH8xEu4UhfA9BOL3uvWtte0jR7ktfsoarV38=; b=Xs/2bTbedEA6iJ9Lgj2j/wNTy/F/BtWeO0BT7fFvSHojoqhzTsYVxkMI T+cKF68XD7ZVxT2LyGhGjjMMJphAzTJr4N48iKLuJrOZ8N1xNGkMxsg7y HLc8V2vGNjM1KEceEHuXseYaO2zm2f7klSyYsJxEoA5gc9b0Ml8ZZi0QR gLykejDJynwnVARny+I1//F3fQKdbWu+JbvXYsAhKby+wbijipjan3vTY xvMDflWcAAssPtqA/UWXROGss2uzV6Uzkn9BNBFodOdI7XMZFyPslcrF3 FS8z7kWuMJUEyEdyyLii0/tWfvbZtTtKNEr4r8VlyAUUg1cf6LpxQeps5 Q==; X-Mailman-Original-Authentication-Results: smtp2.osuosl.org; dmarc=none (p=none dis=none) header.from=linux.intel.com X-Mailman-Original-Authentication-Results: smtp2.osuosl.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Xs/2bTbe Subject: Re: [Intel-wired-lan] [PATCH iwl-next v1 1/8] igc: move IGC_TXDCTL_QUEUE_ENABLE and IGC_TXDCTL_SWFLUSH X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" On 28/4/2025 3:01 pm, Ruinskiy, Dima wrote: > On 28/04/2025 9:02, Faizal Rahim wrote: >> Consolidate TXDCTL-related macros for better organization and readability. >> >> Signed-off-by: Faizal Rahim >> --- >>   drivers/net/ethernet/intel/igc/igc.h      | 6 ++++++ >>   drivers/net/ethernet/intel/igc/igc_base.h | 4 ---- >>   2 files changed, 6 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/ >> intel/igc/igc.h >> index 859a15e4ccba..e9d180eac015 100644 >> --- a/drivers/net/ethernet/intel/igc/igc.h >> +++ b/drivers/net/ethernet/intel/igc/igc.h >> @@ -492,6 +492,12 @@ static inline u32 igc_rss_type(const union >> igc_adv_rx_desc *rx_desc) >>   #define IGC_RX_WTHRESH            4 >>   #define IGC_TX_WTHRESH            16 >> +/* Additional Transmit Descriptor Control definitions */ >> +/* Ena specific Tx Queue */ >> +#define IGC_TXDCTL_QUEUE_ENABLE    0x02000000 >> +/* Transmit Software Flush */ >> +#define IGC_TXDCTL_SWFLUSH    0x04000000 >> + >>   #define IGC_RX_DMA_ATTR \ >>       (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) >> diff --git a/drivers/net/ethernet/intel/igc/igc_base.h b/drivers/net/ >> ethernet/intel/igc/igc_base.h >> index 6320eabb72fe..4a56c634977b 100644 >> --- a/drivers/net/ethernet/intel/igc/igc_base.h >> +++ b/drivers/net/ethernet/intel/igc/igc_base.h >> @@ -86,10 +86,6 @@ union igc_adv_rx_desc { >>       } wb;  /* writeback */ >>   }; >> -/* Additional Transmit Descriptor Control definitions */ >> -#define IGC_TXDCTL_QUEUE_ENABLE    0x02000000 /* Ena specific Tx Queue */ >> -#define IGC_TXDCTL_SWFLUSH    0x04000000 /* Transmit Software Flush */ >> - >>   /* Additional Receive Descriptor Control definitions */ >>   #define IGC_RXDCTL_QUEUE_ENABLE    0x02000000 /* Ena specific Rx Queue */ >>   #define IGC_RXDCTL_SWFLUSH        0x04000000 /* Receive Software Flush */ > > Is there an intrinsic value for moving these definitions from one H file to > another? And if so, why move the Tx defs and leave the Rx defs where they are? Hi Dima, I moved and refactored the TXDCTL macros because this patch series modifies the TXDCTL register, specifically setting new bitfields. Consolidating `IGC_TXDCTL_QUEUE_ENABLE` and `IGC_TXDCTL_SWFLUSH` alongside the existing TXDCTL macros improves readability and makes it easier to cross-reference the TXDCTL bitfield mapping, as documented in Section 8.11.16 of the i226 Software User Manual. The grouping now matches that layout directly: #define IGC_TXDCTL_PTHRESH_MASK GENMASK(4, 0) #define IGC_TXDCTL_HTHRESH_MASK GENMASK(12, 8) #define IGC_TXDCTL_WTHRESH_MASK GENMASK(20, 16) #define IGC_TXDCTL_QUEUE_ENABLE_MASK GENMASK(25, 25) #define IGC_TXDCTL_SWFLUSH_MASK GENMASK(26, 26) #define IGC_TXDCTL_PRIORITY_MASK GENMASK(27, 27) Since RXDCTL is a separate register with its own bitfield mapping section in the i226 Software User Manual, and this patch series does not modify it, I left the RXDCTL macros untouched. They are used independently in separate functions within the driver. That said, I can move the RXDCTL macros as well for consistency.