Re: [PATCH v2 1/3] clk: ingenic: Poll JZ4780 CPU1 power status atomically

[Florian Fainelli <f.fainelli@gmail.com>]

On 11/11/26 10:41, Brian Masney wrote:
> Hi Florian,
> 
>> The CPU1 clock enable callback runs under the clock framework's spinlock
>> with interrupts disabled. Its readl_poll_timeout() can sleep between
>> reads, which is invalid in this context when SMP powers up CPU1.
>>
>> Use readl_poll_timeout_atomic() with the existing interval and timeout.
>> This is a prerequisite for the JZ4780 SMP bring-up path. The original
>> CPU1 clock implementation by Zhou Yanjie is already upstream.
>>
>> Cross-built for CI20; the subsequent SMP-enabled image brought up both
>> CPU cores. Development and validation used Codex assistance.
>>
>> Fixes: 6673db4f3f26 ("clk: JZ4780: Add function for enable the second core.")
>> Link: https://lkml.kernel.org/r/1582215889-113034-3-git-send-email-zhouyanjie@wanyeetech.com
> 
> Cc: stable

OK, I will add that, thanks!

> 
>> Reviewed-by: Paul Cercueil <paul@crapouillou.net>
>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
>> ---
>>   drivers/clk/ingenic/jz4780-cgu.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
>> index 1e88aef7ac0f..f5983033583a 100644
>> --- a/drivers/clk/ingenic/jz4780-cgu.c
>> +++ b/drivers/clk/ingenic/jz4780-cgu.c
>> @@ -242,7 +242,7 @@ static int jz4780_core1_enable(struct clk_hw *hw)
>>   	spin_unlock_irqrestore(&cgu->lock, flags);
>>   
>>   	/* wait for the CPU to be powered up */
>> -	retval = readl_poll_timeout(cgu->base + CGU_REG_LCR, lcr,
>> +	retval = readl_poll_timeout_atomic(cgu->base + CGU_REG_LCR, lcr,
>>   				 !(lcr & LCR_SCPUS), 10, timeout);
> 
> Since you are making changes here, please fix the alignment of the
> next line with (.

Certainly, will submit a newer version shortly.
-- 
Florian