Re: [PATCH net-next 2/2] net: phy: dp83867: Always program R/SGMII enable bits

[Sean Anderson <sean.anderson@linux.dev>]

Hi Russell,

On 1/29/26 12:22, Russell King (Oracle) wrote:
> On Thu, Jan 29, 2026 at 12:12:05PM -0500, Sean Anderson wrote:
>> If the board designers have neglected to populate the appropriate
>> resistors on the strapping pins then the phy may default to the wrong
>> interface mode. Enable/disable the RGMII/SGMII enable bits as necessary
>> to select the correct interface.
>> 
>> The dp83867 strapping pins have four levels and typically configure two
>> features at once. LED_0 controls both port mirroring and whether SGMII
>> is enabled. If it is pulled to VDDIO, both port mirroring and SGMII
>> will be enabled. For variants of the dp83867 that do not support SGMII,
>> this will prevent data from being transferred. As we now explicitly set
>> the SGMII and RGMII enable bits, we do not need to detect whether SGMII
>> has been inadvertently enabled.
>> 
>> Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
> 
> Something to consider:
> 
> You have separate enable bits for SGMII and RGMII. The code you're
> submitting sets the SGMII enable before clearing the RGMII enable.
> Is it permitted to have both set?

Section 7.4.1 of SNLS504F says:

| The SGMII enable has higher priority than the RGMII enable. Table 7-1 is
| the configuration table for the MAC interfaces:
| 
| Table 7-1. Configuration Table for the MAC Interfaces
| SGMII ENABLE              RGMII ENABLE             DEVICE FUNCTIONAL MODE
| (REGISTER 0x0010, BIT 11) (REGISTER 0x0032, BIT 7)
| ========================= ======================== ======================
|                       0x1                      0x1 SGMII
|                       0x1                      0x0 SGMII
|                       0x0                      0x1 RGMII

So I don't think we will have any problems.

--Sean