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action=none header.from=amd.com; Received: from SA0PR12MB7091.namprd12.prod.outlook.com (2603:10b6:806:2d5::17) by BY1PR12MB8446.namprd12.prod.outlook.com (2603:10b6:a03:52d::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.546.14; Thu, 22 Oct 2026 14:08:01 +0000 Received: from SA0PR12MB7091.namprd12.prod.outlook.com ([fe80::ec33:1213:cfd8:63bc]) by SA0PR12MB7091.namprd12.prod.outlook.com ([fe80::ec33:1213:cfd8:63bc%6]) with mapi id 15.21.0522.017; Thu, 22 Oct 2026 14:07:58 +0000 Message-ID: Date: Thu, 22 Oct 2026 19:37:51 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] drm/amd/pm: Report SMU 15.0.8 XGMI bandwidth To: Asad Kamal , amd-gfx@lists.freedesktop.org Cc: hawking.zhang@amd.com, le.ma@amd.com, shiwu.zhang@amd.com, alexander.deucher@amd.com, Kevin.Wang@amd.com References: <20261022123200.2222192-1-asad.kamal@amd.com> Content-Language: en-US From: "Lazar, Lijo" In-Reply-To: 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Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-17.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On 22-Oct-26 6:02 PM, Asad Kamal wrote: > SMU 15.0.8 firmware reports accumulated XGMI read and write bandwidth. > The driver publishes those counters as transferred data, in KB. > > Publish them as xgmi_read_bandwidth_acc and xgmi_write_bandwidth_acc, > with unit GB/s. > > Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Thanks, Lijo > --- > drivers/gpu/drm/amd/include/kgd_pp_interface.h | 2 ++ > drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 6 ++++-- > drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h | 8 ++++---- > 3 files changed, 10 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h > index f92bccb8cb41..17f76071b514 100644 > --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h > +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h > @@ -685,6 +685,8 @@ enum amdgpu_metrics_attr_id { > AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR, > AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_IBC_HSC, > AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_IBC, > + AMDGPU_METRICS_ATTR_ID_XGMI_READ_BANDWIDTH_ACC, > + AMDGPU_METRICS_ATTR_ID_XGMI_WRITE_BANDWIDTH_ACC, > AMDGPU_METRICS_ATTR_ID_MAX, > }; > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c > index 2254c2d414d2..bacdc1a2dd38 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c > @@ -2041,8 +2041,10 @@ static ssize_t smu_v15_0_8_get_gpu_metrics(struct smu_context *smu, void **table > gpu_metrics->xgmi_link_status[j] = ret; > } > > - gpu_metrics->xgmi_read_data_acc = SMUQ10_ROUND(metrics->XgmiReadBandwidthAcc); > - gpu_metrics->xgmi_write_data_acc = SMUQ10_ROUND(metrics->XgmiWriteBandwidthAcc); > + gpu_metrics->xgmi_read_bandwidth_acc = > + SMUQ10_ROUND(metrics->XgmiReadBandwidthAcc); > + gpu_metrics->xgmi_write_bandwidth_acc = > + SMUQ10_ROUND(metrics->XgmiWriteBandwidthAcc); > > for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); ++i) { > inst = GET_INST(GC, i); > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h > index c3835c81d313..8c7e808aa8eb 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h > @@ -146,10 +146,10 @@ typedef struct { > SMU_ARRAY(SMU_MATTR(XGMI_LINK_STATUS), SMU_MUNIT(NONE), \ > SMU_MTYPE(U16), xgmi_link_status, \ > SMU_15_0_8_NUM_XGMI_LINKS); \ > - SMU_SCALAR(SMU_MATTR(XGMI_READ_DATA_ACC), SMU_MUNIT(DATA_1), \ > - SMU_MTYPE(U64), xgmi_read_data_acc); \ > - SMU_SCALAR(SMU_MATTR(XGMI_WRITE_DATA_ACC), SMU_MUNIT(DATA_1), \ > - SMU_MTYPE(U64), xgmi_write_data_acc); \ > + SMU_SCALAR(SMU_MATTR(XGMI_READ_BANDWIDTH_ACC), SMU_MUNIT(BW_1), \ > + SMU_MTYPE(U64), xgmi_read_bandwidth_acc); \ > + SMU_SCALAR(SMU_MATTR(XGMI_WRITE_BANDWIDTH_ACC), SMU_MUNIT(BW_1), \ > + SMU_MTYPE(U64), xgmi_write_bandwidth_acc); \ > SMU_SCALAR(SMU_MATTR(FIRMWARE_TIMESTAMP), SMU_MUNIT(TIME_2), \ > SMU_MTYPE(U64), firmware_timestamp); \ > SMU_ARRAY(SMU_MATTR(CURRENT_GFXCLK), SMU_MUNIT(CLOCK_1), \