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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4904561a160sm462805075e9.9.2026.05.27.08.30.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 May 2026 08:30:38 -0700 (PDT) Message-ID: Date: Wed, 27 May 2026 17:30:36 +0200 Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Reply-To: eric.auger@redhat.com Subject: Re: [PATCH v5 11/18] arm/kvm: Initialize all writable ID registers from host To: Khushit Shah Cc: "eric.auger.pro@gmail.com" , "qemu-devel@nongnu.org" , "qemu-arm@nongnu.org" , "kvmarm@lists.linux.dev" , "peter.maydell@linaro.org" , Shaju Abraham , "yangjinqian1@huawei.com" , "cohuck@redhat.com" , "richard.henderson@linaro.org" , "sebott@redhat.com" , "skolothumtho@nvidia.com" , "philmd@linaro.org" , "maz@kernel.org" , "oliver.upton@linux.dev" , "pbonzini@redhat.com" , "armbru@redhat.com" , "berrange@redhat.com" , "abologna@redhat.com" , "jdenemar@redhat.com" References: <20260519132905.145643-1-eric.auger@redhat.com> <20260519132905.145643-12-eric.auger@redhat.com> <7CF06975-A0CB-43CD-9B3D-FF74DBF55AB9@nutanix.com> From: Eric Auger In-Reply-To: <7CF06975-A0CB-43CD-9B3D-FF74DBF55AB9@nutanix.com> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: p6d4-hraRZcbg2IqHVy6RM0f8EKCPfySBkm1MTJOG-g_1779895840 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 5/27/26 5:02 PM, Khushit Shah wrote: > >> On 19 May 2026, at 6:57 PM, Eric Auger wrote: >> >> !-------------------------------------------------------------------| >> CAUTION: External Email >> >> |-------------------------------------------------------------------! >> >> We want to allow overwriting writable fields of some ID registers. >> However currently some of them are never touched, neither read nor >> w. Examples are CLIDR_EL1, CTR_EL0, REVIDR_EL1, MIDR_EL1. >> >> We want to initialize them from the host value, allow overwrite >> and write back for kvm afterwards. This patch implements the >> initialization. >> >> Introduce a new get_host_cpu_idregs() helper that gets the host >> values for all writable ID regs and store them in isar.idregs[]. >> >> Signed-off-by: Eric Auger >> Signed-off-by: Cornelia Huck >> >> --- >> --- >> target/arm/kvm.c | 72 +++++++++++++++++++++++++++++++++++++++-- >> target/arm/trace-events | 1 + >> 2 files changed, 71 insertions(+), 2 deletions(-) >> >> diff --git a/target/arm/kvm.c b/target/arm/kvm.c >> index 4adfd20050..92219ee62e 100644 >> --- a/target/arm/kvm.c >> +++ b/target/arm/kvm.c >> @@ -42,6 +42,7 @@ >> #include "hw/acpi/ghes.h" >> #include "target/arm/gtimer.h" >> #include "migration/blocker.h" >> +#include "cpu-idregs.h" >> >> const KVMCapabilityInfo kvm_arch_required_capabilities[] = { >> KVM_CAP_INFO(DEVICE_CTRL), >> @@ -273,7 +274,62 @@ static uint32_t kvm_arm_sve_get_vls(int fd) >> return vls[0] & MAKE_64BIT_MASK(0, ARM_MAX_VQ); >> } >> >> -static void kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) >> +static int idregs_idx_to_kvm_feature_idx(ARMIDRegisterIdx idx) >> +{ >> + ARMSysRegs sysreg = id_register_sysreg[idx]; >> + >> + return KVM_ARM_FEATURE_ID_RANGE_IDX((sysreg & CP_REG_ARM64_SYSREG_OP0_MASK) >> + >> CP_REG_ARM64_SYSREG_OP0_SHIFT, >> + (sysreg & CP_REG_ARM64_SYSREG_OP1_MASK) >> + >> CP_REG_ARM64_SYSREG_OP1_SHIFT, >> + (sysreg & CP_REG_ARM64_SYSREG_CRN_MASK) >> + >> CP_REG_ARM64_SYSREG_CRN_SHIFT, >> + (sysreg & CP_REG_ARM64_SYSREG_CRM_MASK) >> + >> CP_REG_ARM64_SYSREG_CRM_SHIFT, >> + (sysreg & CP_REG_ARM64_SYSREG_OP2_MASK) >> + >> CP_REG_ARM64_SYSREG_OP2_SHIFT); >> +} >> + >> +/* >> + * get_host_cpu_idregs: Read all the writable ID reg host values >> + * >> + * Need to be called once the writable mask has been populated >> + * Note we may want to read all the known id regs but some of them are not >> + * writable and return an error, hence the choice of reading only those which >> + * are writable. Those are also readable! >> + */ >> +static int get_host_cpu_idregs(ARMCPU *cpu, int fd, ARMHostCPUFeatures *ahcf) >> +{ >> + int err = 0; >> + int i; >> + >> + for (i = 0; i < NUM_ID_IDX; i++) { >> + ARM64SysReg *sysregdesc = &arm64_id_regs[i]; >> + ARMSysRegs sysreg = id_register_sysreg[i]; >> + uint64_t writable_mask = >> + cpu->writable_map[idregs_idx_to_kvm_feature_idx(i)]; >> + uint64_t *reg; >> + int ret; >> + >> + if (!writable_mask) { >> + continue; >> + } >> + >> + reg = &ahcf->isar.idregs[i]; >> + ret = read_sys_reg64(fd, reg, idregs_sysreg_to_kvm_reg(sysreg)); >> + trace_get_host_cpu_idregs(sysregdesc->name, *reg); >> + if (ret) { >> + error_report("%s error reading value of host %s register (%m)", >> + __func__, sysregdesc->name); >> + >> + err = ret; >> + } >> + } >> + return err; >> +} >> + >> +static void >> +kvm_arm_get_host_cpu_features(ARMCPU *cpu, ARMHostCPUFeatures *ahcf) >> { >> /* Identify the feature bits corresponding to the host CPU, and >> * fill out the ARMHostCPUClass fields accordingly. To do this >> @@ -359,6 +415,18 @@ static void kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) >> SET_IDREG(&ahcf->isar, ID_AA64PFR0, 0x00000011); /* EL1&0, AArch64 only */ >> err = 0; >> } else { >> + /* Make sure all writable ID reg values are initialized */ >> + if (cpu->writable_map) { >> + err |= get_host_cpu_idregs(cpu, fd, ahcf); >> + } > Again, I do not like writable_map being in ARMCPU. > > Why should kvm_arm_get_host_cpu_features care if writable > map is populated or not? > >> + /* >> + * temporarily override the CLIDR_EL1 value since some host values >> + * trigger "Unified type is not implemented at level n" error in >> + * fdt_add_cpu_nodes() >> + */ >> + SET_IDREG(&ahcf->isar, CLIDR, 0x0); >> + > This is because by default KVM exposes a 1 level unified, 1 way 1 set simple > cache, to efficiently handle set/way based cache operations. I sent a separate question to the contributor in https://lore.kernel.org/all/0fc08e52-d62c-4c40-9221-9f4e659c2aa5@redhat.com/. You can also reply in the separate thread This looks we need a separate fix for that, no? Thanks Eric > > TBH this is slightly ugly. Should make the virt machine code to not expose > cache fdt nodes if using KVM. > > For our v2 (WIP), we have handled this by a new property ‘expose-cache’ for > named cpu models which is used to set CLIDR and CCSIDR banks based > on values provided by the model and only creating fdt nodes if those > values are provided. > >> err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX); >> err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR2_EL1_IDX); >> err |= get_host_cpu_reg(fd, ahcf, ID_AA64SMFR0_EL1_IDX); >> @@ -485,7 +553,7 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) >> CPUARMState *env = &cpu->env; >> >> if (!arm_host_cpu_features.dtb_compatible) { >> - kvm_arm_get_host_cpu_features(&arm_host_cpu_features); >> + kvm_arm_get_host_cpu_features(cpu, &arm_host_cpu_features); >> } >> >> cpu->kvm_target = arm_host_cpu_features.target; >> diff --git a/target/arm/trace-events b/target/arm/trace-events >> index 8502fb3265..8c7faf57c7 100644 >> --- a/target/arm/trace-events >> +++ b/target/arm/trace-events >> @@ -13,6 +13,7 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d" >> >> # kvm.c >> kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova = 0x%"PRIx64" is translated into 0x%"PRIx64 >> +get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu host value for %s is 0x%"PRIx64 >> >> # cpu.c >> arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 >> -- >> 2.53.0 >> > > Warm Regards, > Khushit >