Re: [Intel-gfx] [PATCH v3 1/5] drm/i915/panelreplay: dpcd register definition for panelreplay

["Manna, Animesh" <animesh.manna@intel.com>]

> -----Original Message-----
> From: Souza, Jose <jose.souza@intel.com>
> Sent: Wednesday, November 24, 2021 1:07 AM
> To: dri-devel@lists.freedesktop.org; Manna, Animesh
> <animesh.manna@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Kahola, Mika <mika.kahola@intel.com>; Navare,
> Manasi D <manasi.d.navare@intel.com>
> Subject: Re: [PATCH v3 1/5] drm/i915/panelreplay: dpcd register definition for
> panelreplay
> 
> On Sun, 2021-10-10 at 17:40 +0530, Animesh Manna wrote:
> > DPCD register definition added to check and enable panel replay
> > capability of the sink.
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  include/drm/drm_dp_helper.h | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index b52df4db3e8f..8a2b929c3f88 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -541,6 +541,9 @@ struct drm_panel;
> >  /* DFP Capability Extension */
> >  #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT	0x0a3	/* 2.0 */
> >
> > +#define DP_PANEL_REPLAY_CAP                 0x0b0
> > +# define PANEL_REPLAY_SUPPORT               (1 << 0)
> 
> Missing bit 1, that is very important when panel do not support selective update
> panel replay needs to act like PSR1 when it is sets it needs to act like PSR2.
> 
> > +
> >  /* Link Configuration */
> >  #define	DP_LINK_BW_SET		            0x100
> >  # define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */
> > @@ -709,6 +712,9 @@ struct drm_panel;
> >  #define DP_BRANCH_DEVICE_CTRL		    0x1a1
> >  # define DP_BRANCH_DEVICE_IRQ_HPD	    (1 << 0)
> >
> > +#define PANEL_REPLAY_CONFIG                 0x1b0
> > +# define PANEL_REPLAY_ENABLE                (1 << 0)
> 
> All other bits are also important, for the errors ones we have PSR counter parts
> and your are missing the error status register.

Thanks for review.
Added the suggested changes in current version.
 
Regards,
Animesh
> 
> > +
> >  #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
> >  #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1  #define
> > DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2