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Fri, 30 Jan 2026 08:04:32 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN3PEPF0000B370.mail.protection.outlook.com (10.167.243.167) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9587.0 via Frontend Transport; Fri, 30 Jan 2026 08:04:36 +0000 Received: from [10.136.44.172] (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 30 Jan 2026 02:04:33 -0600 Message-ID: Date: Fri, 30 Jan 2026 13:34:30 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] amd_iommu: Use switch case to determine mmio register name Content-Language: en-US To: CLEMENT MATHIEU--DRIF , "qemu-devel@nongnu.org" CC: "alejandro.j.jimenez@oracle.com" , "pbonzini@redhat.com" , "richard.henderson@linaro.org" , "eduardo@habkost.net" , "mst@redhat.com" , "marcel.apfelbaum@gmail.com" , "vasant.hegde@amd.com" References: <20260129102814.4488-1-sarunkod@amd.com> <20260129102814.4488-2-sarunkod@amd.com> <85c7506f677e3a9145eb8be2212ee62c0b92169e.camel@eviden.com> From: Sairaj Kodilkar In-Reply-To: <85c7506f677e3a9145eb8be2212ee62c0b92169e.camel@eviden.com> Content-Type: text/plain; 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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B370.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4108 Received-SPF: permerror client-ip=40.93.201.2; envelope-from=Sairaj.ArunKodilkar@amd.com; helo=CY3PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/30/2026 1:09 PM, CLEMENT MATHIEU--DRIF wrote: > > On Thu, 2026-01-29 at 15:58 +0530, Sairaj Kodilkar wrote: >> This makes it easier to add new MMIO registers for tracing and removes >> the unnecessary complexity introduced by amdvi_mmio_(low/high) array. >> >> Signed-off-by: Sairaj Kodilkar <[sarunkod@amd.com](mailto:sarunkod@amd.com)> >> Reviewed-by: Vasant Hegde <[vasant.hegde@amd.com](mailto:vasant.hegde@amd.com)> >> --- >>  hw/i386/amd_iommu.c | 65 +++++++++++++++++++-------------------------- >>  1 file changed, 27 insertions(+), 38 deletions(-) >> >> diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c >> index 789e09d6f2bc..62175cc366ac 100644 >> --- a/hw/i386/amd_iommu.c >> +++ b/hw/i386/amd_iommu.c >> @@ -35,28 +35,7 @@ >>  #include "kvm/kvm_i386.h" >>  #include "qemu/iova-tree.h" >> >> -/* used AMD-Vi MMIO registers */ >> -const char *amdvi_mmio_low[] = { >> -    "AMDVI_MMIO_DEVTAB_BASE", >> -    "AMDVI_MMIO_CMDBUF_BASE", >> -    "AMDVI_MMIO_EVTLOG_BASE", >> -    "AMDVI_MMIO_CONTROL", >> -    "AMDVI_MMIO_EXCL_BASE", >> -    "AMDVI_MMIO_EXCL_LIMIT", >> -    "AMDVI_MMIO_EXT_FEATURES", >> -    "AMDVI_MMIO_PPR_BASE", >> -    "UNHANDLED" >> -}; >> -const char *amdvi_mmio_high[] = { >> -    "AMDVI_MMIO_COMMAND_HEAD", >> -    "AMDVI_MMIO_COMMAND_TAIL", >> -    "AMDVI_MMIO_EVTLOG_HEAD", >> -    "AMDVI_MMIO_EVTLOG_TAIL", >> -    "AMDVI_MMIO_STATUS", >> -    "AMDVI_MMIO_PPR_HEAD", >> -    "AMDVI_MMIO_PPR_TAIL", >> -    "UNHANDLED" >> -}; >> +#define MMIO_REG_TO_STRING(mmio_reg) case mmio_reg: return #mmio_reg > Hi Sairaj, > > Shouldn't we define this inside the mmio_get_name function and undef it after the return statement? > I think it would be cleanup to make the scope of this a bit smaller as it is specifically written for this function. Hi I think this is probably okay as its unlikely to cause any issues in future. Thanks -Sairaj > >> >>  struct AMDVIAddressSpace { >>      PCIBus *bus;                /* PCIBus (for bus number)              */ >> @@ -1484,31 +1463,41 @@ static void amdvi_cmdbuf_run(AMDVIState *s) >>      } >>  } >> >> -static inline uint8_t amdvi_mmio_get_index(hwaddr addr) >> -{ >> -    uint8_t index = (addr & ~0x2000) / 8; >> - >> -    if ((addr & 0x2000)) { >> -        /* high table */ >> -        index = index >= AMDVI_MMIO_REGS_HIGH ? AMDVI_MMIO_REGS_HIGH : index; >> -    } else { >> -        index = index >= AMDVI_MMIO_REGS_LOW ? AMDVI_MMIO_REGS_LOW : index; >> +static inline >> +const char *amdvi_mmio_get_name(hwaddr addr) >> +{ >> +    /* Return MMIO names as string literals */ >> +    switch (addr) { >> +    MMIO_REG_TO_STRING(AMDVI_MMIO_DEVICE_TABLE); >> +    MMIO_REG_TO_STRING(AMDVI_MMIO_COMMAND_BASE); >> +    MMIO_REG_TO_STRING(AMDVI_MMIO_EVENT_BASE); >> +    MMIO_REG_TO_STRING(AMDVI_MMIO_CONTROL); >> +    MMIO_REG_TO_STRING(AMDVI_MMIO_EXCL_BASE); >> +    MMIO_REG_TO_STRING(AMDVI_MMIO_EXCL_LIMIT); >> +    MMIO_REG_TO_STRING(AMDVI_MMIO_EXT_FEATURES); >> +    MMIO_REG_TO_STRING(AMDVI_MMIO_COMMAND_HEAD); >> +    MMIO_REG_TO_STRING(AMDVI_MMIO_COMMAND_TAIL); >> +    MMIO_REG_TO_STRING(AMDVI_MMIO_EVENT_HEAD); >> +    MMIO_REG_TO_STRING(AMDVI_MMIO_EVENT_TAIL); >> +    MMIO_REG_TO_STRING(AMDVI_MMIO_STATUS); >> +    MMIO_REG_TO_STRING(AMDVI_MMIO_PPR_BASE); >> +    MMIO_REG_TO_STRING(AMDVI_MMIO_PPR_HEAD); >> +    MMIO_REG_TO_STRING(AMDVI_MMIO_PPR_TAIL); >> +    default: >> +        return "UNHANDLED"; >>      } >> - >> -    return index; >>  } >> >>  static void amdvi_mmio_trace_read(hwaddr addr, unsigned size) >>  { >> -    uint8_t index = amdvi_mmio_get_index(addr); >> -    trace_amdvi_mmio_read(amdvi_mmio_low[index], addr, size, addr & ~0x07); >> +    const char *mmio_name = amdvi_mmio_get_name(addr); >> +    trace_amdvi_mmio_read(mmio_name, addr, size, addr & ~0x07); >>  } >> >>  static void amdvi_mmio_trace_write(hwaddr addr, unsigned size, uint64_t val) >>  { >> -    uint8_t index = amdvi_mmio_get_index(addr); >> -    trace_amdvi_mmio_write(amdvi_mmio_low[index], addr, size, val, >> -                           addr & ~0x07); >> +    const char *mmio_name = amdvi_mmio_get_name(addr); >> +    trace_amdvi_mmio_write(mmio_name, addr, size, val, addr & ~0x07); >>  } >> >>  static uint64_t amdvi_mmio_read(void *opaque, hwaddr addr, unsigned size)