From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com
Subject: Re: [PATCH RESEND v7 12/12] target/riscv: forbid write_misa() for static CPUs
Date: Fri, 21 Apr 2023 08:36:17 -0300 [thread overview]
Message-ID: <dfaad783-bddb-64a1-72c7-da4b7ab71349@ventanamicro.com> (raw)
In-Reply-To: <CAKmqyKPX4ThJkWfyoTmVoCtcwGdPYONYqdMLAXUGzOb+9T=ggw@mail.gmail.com>
On 4/20/23 20:48, Alistair Francis wrote:
> On Thu, Apr 20, 2023 at 7:22 PM Daniel Henrique Barboza
> <dbarboza@ventanamicro.com> wrote:
>>
>> Static CPUs don't want their extensions changed by user interaction. We
>> can prevent it during init by not exposing user facing properties, but
>> write_misa() is also capable of disabling/enabling extension during
>> runtime.
>>
>> We have a way of telling whether a CPU is static or not by checking for
>> TYPE_RISCV_DYNAMIC_CPU. Use it to make write_misa() a no-op for these
>> CPUs.
>>
>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> ---
>> target/riscv/cpu.c | 5 +++++
>> target/riscv/cpu.h | 2 ++
>> target/riscv/csr.c | 5 +++++
>> 3 files changed, 12 insertions(+)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 4fa720a39d..3cbcf6d320 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -1452,6 +1452,11 @@ static void riscv_cpu_init(Object *obj)
>> #endif /* CONFIG_USER_ONLY */
>> }
>>
>> +bool riscv_cpu_is_static(RISCVCPU *cpu)
>> +{
>> + return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_DYNAMIC_CPU) == NULL;
>> +}
>> +
>> typedef struct RISCVCPUMisaExtConfig {
>> const char *name;
>> const char *description;
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 1f39edc687..1913ab9d8d 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -587,6 +587,8 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env,
>> target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
>> void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
>>
>> +bool riscv_cpu_is_static(RISCVCPU *cpu);
>> +
>> #include "exec/cpu-all.h"
>>
>> FIELD(TB_FLAGS, MEM_IDX, 0, 3)
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index d449da2657..929c5477dd 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -1391,6 +1391,11 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
>> uint32_t orig_misa_ext = env->misa_ext;
>> Error *local_err = NULL;
>>
>> + if (riscv_cpu_is_static(cpu)) {
>> + /* never write MISA for static CPUs */
>> + return RISCV_EXCP_NONE;
>> + }
>
> Do we actually need this? We already check misa_w which would be
> disabled. What's the harm in allowing someone to manually enable
> misa_w and then change the MISA?
>
> Also, it's possible that static CPUs actually support changing the
> MISA value at run time.
That's all valid points. I believe it's ok to drop this patch to allow
for static CPUs to have more flexibility in the future. We're still have
misa_w.
Thanks,
Daniel
>
> Alistair
>
>> +
>> if (!riscv_cpu_cfg(env)->misa_w) {
>> /* drop write to misa */
>> return RISCV_EXCP_NONE;
>> --
>> 2.40.0
>>
>>
prev parent reply other threads:[~2023-04-21 11:36 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-20 9:20 [PATCH RESEND v7 00/12] target/riscv: rework CPU extensions validation Daniel Henrique Barboza
2023-04-20 9:20 ` [PATCH RESEND v7 01/12] target/riscv/cpu.c: add riscv_cpu_validate_v() Daniel Henrique Barboza
2023-04-20 9:20 ` [PATCH RESEND v7 02/12] target/riscv/cpu.c: remove set_vext_version() Daniel Henrique Barboza
2023-04-20 9:20 ` [PATCH RESEND v7 03/12] target/riscv/cpu.c: remove set_priv_version() Daniel Henrique Barboza
2023-04-20 9:20 ` [PATCH RESEND v7 04/12] target/riscv: add PRIV_VERSION_LATEST Daniel Henrique Barboza
2023-04-20 9:20 ` [PATCH RESEND v7 05/12] target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version Daniel Henrique Barboza
2023-04-20 23:00 ` Alistair Francis
2023-04-20 9:20 ` [PATCH RESEND v7 06/12] target/riscv: Update check for Zca/Zcf/Zcd Daniel Henrique Barboza
2023-04-20 9:20 ` [PATCH RESEND v7 07/12] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers Daniel Henrique Barboza
2023-04-20 9:20 ` [PATCH RESEND v7 08/12] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() Daniel Henrique Barboza
2023-04-20 9:20 ` [PATCH RESEND v7 09/12] target/riscv/cpu.c: validate extensions before riscv_timer_init() Daniel Henrique Barboza
2023-04-20 9:20 ` [PATCH RESEND v7 10/12] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() Daniel Henrique Barboza
2023-04-20 9:20 ` [PATCH RESEND v7 11/12] target/riscv: rework write_misa() Daniel Henrique Barboza
2023-04-20 23:45 ` Alistair Francis
2023-04-21 11:34 ` Daniel Henrique Barboza
2023-04-21 13:06 ` Daniel Henrique Barboza
2023-04-21 13:14 ` Daniel Henrique Barboza
2023-04-20 9:21 ` [PATCH RESEND v7 12/12] target/riscv: forbid write_misa() for static CPUs Daniel Henrique Barboza
2023-04-20 23:48 ` Alistair Francis
2023-04-21 11:36 ` Daniel Henrique Barboza [this message]
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