diff for duplicates of <dfd57ef4-08bd-53cf-1f0a-86edc5bc0a67@intel.com>

diff --git a/a/1.txt b/N1/1.txt
index a960e45..22e3de5 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -6,7 +6,7 @@ On 6/24/2019 18:06, Kai-Heng Feng wrote:
 >>> at 19:08, Kai-Heng Feng <kai.heng.feng@canonical.com> wrote:
 >>>> Hi Jeffrey,
 >>>>
->>>> There are several platforms that uses e1000e can?t enter 
+>>>> There are several platforms that uses e1000e can’t enter 
 >>>> Opportunistic S0ix (PC10) when the ethernet has a link partner.
 >>>>
 >>>> This behavior also exits in out-of-tree e1000e driver 3.4.2.1, but 
@@ -15,37 +15,37 @@ On 6/24/2019 18:06, Kai-Heng Feng wrote:
 >>>> A quick diff between the two versions shows that this code section 
 >>>> may be our solution:
 >>>>
->>>> ??????? /* Read from EXTCNF_CTRL in e1000_acquire_swflag_ich8lan 
+>>>>         /* Read from EXTCNF_CTRL in e1000_acquire_swflag_ich8lan 
 >>>> function
->>>> ???????? * may occur during global reset and cause system hang.
->>>> ???????? * Configuration space access creates the needed delay.
->>>> ???????? * Write to E1000_STRAP RO register 
+>>>>          * may occur during global reset and cause system hang.
+>>>>          * Configuration space access creates the needed delay.
+>>>>          * Write to E1000_STRAP RO register 
 >>>> E1000_PCI_VENDOR_ID_REGISTER value
->>>> ???????? * insures configuration space read is done before global 
+>>>>          * insures configuration space read is done before global 
 >>>> reset.
->>>> ???????? */
->>>> ??????? pci_read_config_word(hw->adapter->pdev, 
+>>>>          */
+>>>>         pci_read_config_word(hw->adapter->pdev, 
 >>>> E1000_PCI_VENDOR_ID_REGISTER,
->>>> ???????????????????????????? &pci_cfg);
->>>> ??????? ew32(STRAP, pci_cfg);
->>>> ??????? e_dbg("Issuing a global reset to ich8lan\n");
->>>> ??????? ew32(CTRL, (ctrl | E1000_CTRL_RST));
->>>> ??????? /* cannot issue a flush here because it hangs the hardware */
->>>> ??????? msleep(20);
+>>>>                              &pci_cfg);
+>>>>         ew32(STRAP, pci_cfg);
+>>>>         e_dbg("Issuing a global reset to ich8lan\n");
+>>>>         ew32(CTRL, (ctrl | E1000_CTRL_RST));
+>>>>         /* cannot issue a flush here because it hangs the hardware */
+>>>>         msleep(20);
 >>>>
->>>> ??????? /* Configuration space access improve HW level time sync 
+>>>>         /* Configuration space access improve HW level time sync 
 >>>> mechanism.
->>>> ???????? * Write to E1000_STRAP RO register 
+>>>>          * Write to E1000_STRAP RO register 
 >>>> E1000_PCI_VENDOR_ID_REGISTER
->>>> ???????? * value to insure configuration space read is done
->>>> ???????? * before any access to mac register.
->>>> ???????? */
->>>> ??????? pci_read_config_word(hw->adapter->pdev, 
+>>>>          * value to insure configuration space read is done
+>>>>          * before any access to mac register.
+>>>>          */
+>>>>         pci_read_config_word(hw->adapter->pdev, 
 >>>> E1000_PCI_VENDOR_ID_REGISTER,
->>>> ???????????????????????????? &pci_cfg);
->>>> ??????? ew32(STRAP, pci_cfg);
->>> Turns out the "extra sauce? is not this part, it?s called ?Dynamic 
->>> LTR support?.
+>>>>                              &pci_cfg);
+>>>>         ew32(STRAP, pci_cfg);
+>>> Turns out the "extra sauce” is not this part, it’s called “Dynamic 
+>>> LTR support”.
 >>> >>
 >>>> Is there any plan to support this in the upstream kernel?
 >>> Is there any plan to support Dynamic LTR in upstream e1000e?
@@ -53,7 +53,7 @@ On 6/24/2019 18:06, Kai-Heng Feng wrote:
 >> to upstream. I hope we will be able to fix this in HW for a future 
 >> projects.
 > 
-> Does this mean current generation hardware won?t get the fix?
+> Does this mean current generation hardware won’t get the fix?
 Current HW have a limitation. Please, try follow workaround on your 
 platform: echo 3 > /sys/kernel/debug/pmc_core/ltr_ignore
 > >> S0ix support is under discussion with our architecture. We will try
@@ -70,7 +70,7 @@ will work as properly.
 >>>> Kai-Heng
 >>> _______________________________________________
 >>> Intel-wired-lan mailing list
->>> Intel-wired-lan at osuosl.org
+>>> Intel-wired-lan@osuosl.org
 >>> https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
 >>
 >> Thanks
diff --git a/a/content_digest b/N1/content_digest
index 17fcad2..f975c83 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -3,9 +3,13 @@
  "ref\095f88f45-fd6c-52e4-de8c-2db1b4c6c04e@intel.com\0"
  "ref\0E8C45269-819C-41E0-A3D3-AA98710DBA4C@canonical.com\0"
  "From\0Neftin, Sasha <sasha.neftin@intel.com>\0"
- "Subject\0[Intel-wired-lan] Opportunistic S0ix blocked by e1000e when ethernet is in use\0"
+ "Subject\0Re: [Intel-wired-lan] Opportunistic S0ix blocked by e1000e when ethernet is in use\0"
  "Date\0Tue, 25 Jun 2019 13:25:00 +0300\0"
- "To\0intel-wired-lan@osuosl.org\0"
+ "To\0Kai-Heng Feng <kai.heng.feng@canonical.com>\0"
+ "Cc\0jeffrey.t.kirsher@intel.com"
+  intel-wired-lan@lists.osuosl.org
+  Anthony Wong <anthony.wong@canonical.com>
+ " linux-kernel <linux-kernel@vger.kernel.org>\0"
  "\00:1\0"
  "b\0"
  "On 6/24/2019 18:06, Kai-Heng Feng wrote:\n"
@@ -16,7 +20,7 @@
  ">>> at 19:08, Kai-Heng Feng <kai.heng.feng@canonical.com> wrote:\n"
  ">>>> Hi Jeffrey,\n"
  ">>>>\n"
- ">>>> There are several platforms that uses e1000e can?t enter \n"
+ ">>>> There are several platforms that uses e1000e can\342\200\231t enter \n"
  ">>>> Opportunistic S0ix (PC10) when the ethernet has a link partner.\n"
  ">>>>\n"
  ">>>> This behavior also exits in out-of-tree e1000e driver 3.4.2.1, but \n"
@@ -25,37 +29,37 @@
  ">>>> A quick diff between the two versions shows that this code section \n"
  ">>>> may be our solution:\n"
  ">>>>\n"
- ">>>> ??????? /* Read from EXTCNF_CTRL in e1000_acquire_swflag_ich8lan \n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240 /* Read from EXTCNF_CTRL in e1000_acquire_swflag_ich8lan \n"
  ">>>> function\n"
- ">>>> ???????? * may occur during global reset and cause system hang.\n"
- ">>>> ???????? * Configuration space access creates the needed delay.\n"
- ">>>> ???????? * Write to E1000_STRAP RO register \n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * may occur during global reset and cause system hang.\n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * Configuration space access creates the needed delay.\n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * Write to E1000_STRAP RO register \n"
  ">>>> E1000_PCI_VENDOR_ID_REGISTER value\n"
- ">>>> ???????? * insures configuration space read is done before global \n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * insures configuration space read is done before global \n"
  ">>>> reset.\n"
- ">>>> ???????? */\n"
- ">>>> ??????? pci_read_config_word(hw->adapter->pdev, \n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 */\n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240 pci_read_config_word(hw->adapter->pdev, \n"
  ">>>> E1000_PCI_VENDOR_ID_REGISTER,\n"
- ">>>> ???????????????????????????? &pci_cfg);\n"
- ">>>> ??????? ew32(STRAP, pci_cfg);\n"
- ">>>> ??????? e_dbg(\"Issuing a global reset to ich8lan\\n\");\n"
- ">>>> ??????? ew32(CTRL, (ctrl | E1000_CTRL_RST));\n"
- ">>>> ??????? /* cannot issue a flush here because it hangs the hardware */\n"
- ">>>> ??????? msleep(20);\n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 &pci_cfg);\n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240 ew32(STRAP, pci_cfg);\n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240 e_dbg(\"Issuing a global reset to ich8lan\\n\");\n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240 ew32(CTRL, (ctrl | E1000_CTRL_RST));\n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240 /* cannot issue a flush here because it hangs the hardware */\n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240 msleep(20);\n"
  ">>>>\n"
- ">>>> ??????? /* Configuration space access improve HW level time sync \n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240 /* Configuration space access improve HW level time sync \n"
  ">>>> mechanism.\n"
- ">>>> ???????? * Write to E1000_STRAP RO register \n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * Write to E1000_STRAP RO register \n"
  ">>>> E1000_PCI_VENDOR_ID_REGISTER\n"
- ">>>> ???????? * value to insure configuration space read is done\n"
- ">>>> ???????? * before any access to mac register.\n"
- ">>>> ???????? */\n"
- ">>>> ??????? pci_read_config_word(hw->adapter->pdev, \n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * value to insure configuration space read is done\n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * before any access to mac register.\n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 */\n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240 pci_read_config_word(hw->adapter->pdev, \n"
  ">>>> E1000_PCI_VENDOR_ID_REGISTER,\n"
- ">>>> ???????????????????????????? &pci_cfg);\n"
- ">>>> ??????? ew32(STRAP, pci_cfg);\n"
- ">>> Turns out the \"extra sauce? is not this part, it?s called ?Dynamic \n"
- ">>> LTR support?.\n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 &pci_cfg);\n"
+ ">>>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240 ew32(STRAP, pci_cfg);\n"
+ ">>> Turns out the \"extra sauce\342\200\235 is not this part, it\342\200\231s called \342\200\234Dynamic \n"
+ ">>> LTR support\342\200\235.\n"
  ">>> >>\n"
  ">>>> Is there any plan to support this in the upstream kernel?\n"
  ">>> Is there any plan to support Dynamic LTR in upstream e1000e?\n"
@@ -63,7 +67,7 @@
  ">> to upstream. I hope we will be able to fix this in HW for a future \n"
  ">> projects.\n"
  "> \n"
- "> Does this mean current generation hardware won?t get the fix?\n"
+ "> Does this mean current generation hardware won\342\200\231t get the fix?\n"
  "Current HW have a limitation. Please, try follow workaround on your \n"
  "platform: echo 3 > /sys/kernel/debug/pmc_core/ltr_ignore\n"
  "> >> S0ix support is under discussion with our architecture. We will try\n"
@@ -80,7 +84,7 @@
  ">>>> Kai-Heng\n"
  ">>> _______________________________________________\n"
  ">>> Intel-wired-lan mailing list\n"
- ">>> Intel-wired-lan at osuosl.org\n"
+ ">>> Intel-wired-lan@osuosl.org\n"
  ">>> https://lists.osuosl.org/mailman/listinfo/intel-wired-lan\n"
  ">>\n"
  ">> Thanks\n"
@@ -88,4 +92,4 @@
  "> \n"
  >
 
-bfcc8b64a56e520942c363880d858200a50a42b2a5d0b4bd1b019ed102869753
+720444ed81473d07fb8a33e8a9e54bbc0b5c63ca09448ff64496efd28802bf46
