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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39e1b69c756sm2159085a91.3.2026.09.15.21.26.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Sep 2026 21:26:12 -0700 (PDT) Message-ID: Date: Wed, 16 Sep 2026 12:26:10 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 2/2] pwm: Add Nuvoton MA35D1 PWM controller support To: sashiko-reviews@lists.linux.dev Cc: conor+dt@kernel.org, robh@kernel.org, devicetree@vger.kernel.org, =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= , cwweng@nuvoton.com References: <20260914110739.203479-1-cwweng.linux@gmail.com> <20260914110739.203479-3-cwweng.linux@gmail.com> <20260914111742.85BF01F000FF@smtp.kernel.org> Content-Language: en-US From: Chi-Wen Weng In-Reply-To: <20260914111742.85BF01F000FF@smtp.kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit sashiko-bot@kernel.org 於 2026/9/14 下午 07:17 寫道: > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [Medium] The driver relies on the bootloader-configured CLKPSC (prescaler) register but does not cache its value, which will cause incorrect period calculations after a system suspend/resume cycle. > -- > > commit b9ac3c051c5908fe946a0ef1c7b809030aa32933 > Author: Chi-Wen Weng > > pwm: Add Nuvoton MA35D1 PWM controller support > > This commit adds a generic PWM framework driver for the Nuvoton MA35D1 PWM > controller. The initial driver supports 6 channels in up-counting, > auto-reload, independent output, and period loading modes. > >> diff --git a/drivers/pwm/pwm-ma35d1.c b/drivers/pwm/pwm-ma35d1.c >> new file mode 100644 >> --- /dev/null >> +++ b/drivers/pwm/pwm-ma35d1.c > [ ... ] >> +static u32 nuvoton_pwm_get_prescale(struct nuvoton_pwm *nvtpwm, >> + unsigned int ch) >> +{ >> + return nuvoton_pwm_readl(nvtpwm, MA35D1_REG_PWM_CLKPSC(ch)) & >> + MA35D1_PWM_CLKPSC_MASK; >> +} > > [Severity: Medium] > Does reading the hardware register directly here make the driver vulnerable > to hardware state loss during system suspend? > > If the controller loses power during suspend, the clock prescaler register > might reset to its default value. When the system resumes and a consumer > subsequently calls into the apply callback, this function will return the > reset value instead of the bootloader-configured value. This could result > in drastically altered PWM output frequencies. > > Would it be safer to cache the prescaler value during probe? > > [ ... ] >> +static struct platform_driver nuvoton_pwm_driver = { >> + .probe = nuvoton_pwm_probe, >> + .driver = { >> + .name = "nuvoton-pwm", >> + .of_match_table = nuvoton_pwm_of_match, >> + }, >> +}; > > [Severity: Medium] > Should this driver include PM callbacks to handle saving and restoring the > hardware state? > > Currently, there are no suspend/resume hooks provided. If the platform > powers down the PWM domain during system suspend, the controller state > will be lost upon resume and might not be appropriately reconfigured before > the next state application. > Hi, Thanks for the review. On MA35D1, the EPWM register context is retained across system suspend. This includes CLKPSC as well as the other EPWM configuration registers used by the driver. Therefore, after resume, nuvoton_pwm_get_prescale() still reads the same CLKPSC value that was present before suspend. The firmware-provided prescaler value is not lost, so caching CLKPSC during probe would be redundant. For the same reason, suspend/resume callbacks are not required to save and restore the EPWM register state on MA35D1. So I don't think either of these issues requires a driver change. Best regards, Chi-Wen