From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF2DAC32789 for ; Tue, 6 Nov 2018 06:08:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 69A8120827 for ; Tue, 6 Nov 2018 06:08:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="n17ZoVV5" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 69A8120827 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-pci-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729605AbeKFPcB (ORCPT ); Tue, 6 Nov 2018 10:32:01 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:37706 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729342AbeKFPcB (ORCPT ); Tue, 6 Nov 2018 10:32:01 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id wA667Ghh050877; Tue, 6 Nov 2018 00:07:16 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1541484436; bh=oV2xEQML1iU4xFL/ov6+uu3i0JmRIX7v1/Io36rwBSs=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=n17ZoVV5ZlWRHhwAw5SOcZhlY93M7Lv298AXnS7YCuztswjt2f9dA0EPsYjyCcYm7 I1EJFBX8ufizWM12meFygjqwtsC1lJFfcns1YVKfjJsRD0zhkRdGNW6E8nkQllMlDN ndcYdh0OuCwqZp8TkoSlkR/K0Q5ZOMF1T0cY12T4= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wA667Guq003139 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 6 Nov 2018 00:07:16 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 6 Nov 2018 00:07:16 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 6 Nov 2018 00:07:16 -0600 Received: from [172.24.190.233] (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id wA667A0e013958; Tue, 6 Nov 2018 00:07:11 -0600 Subject: Re: [PATCH 5/6] pci: layerscape: Add the EP mode support. To: Xiaowei Bao , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "arnd@arndb.de" , "gregkh@linuxfoundation.org" , "M.h. Lian" , Mingkai Hu , Roy Zang , "kstewart@linuxfoundation.org" , "cyrille.pitchen@free-electrons.com" , "pombredanne@nexb.com" , "shawn.lin@rock-chips.com" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linuxppc-dev@lists.ozlabs.org" CC: Jiafei Pan References: <20181025110901.5680-1-xiaowei.bao@nxp.com> <20181025110901.5680-5-xiaowei.bao@nxp.com> <8ec7f502-e058-2c28-9140-5d125e4af6ff@ti.com> From: Kishon Vijay Abraham I Message-ID: Date: Tue, 6 Nov 2018 11:36:42 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org (Removed Niklas as mails to him is bouncing) Hi, Please fix your email client. Refer Documentation/process/email-clients.rst On 05/11/18 2:45 PM, Xiaowei Bao wrote: > > > -----Original Message----- > From: Kishon Vijay Abraham I > Sent: 2018年11月5日 16:57 > To: Xiaowei Bao ; bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com; shawnguo@kernel.org; Leo Li ; lorenzo.pieralisi@arm.com; arnd@arndb.de; gregkh@linuxfoundation.org; M.h. Lian ; Mingkai Hu ; Roy Zang ; kstewart@linuxfoundation.org; cyrille.pitchen@free-electrons.com; pombredanne@nexb.com; shawn.lin@rock-chips.com; niklas.cassel@axis.com; linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linuxppc-dev@lists.ozlabs.org > Cc: Jiafei Pan > Subject: Re: [PATCH 5/6] pci: layerscape: Add the EP mode support. > > Hi, > > On 31/10/18 4:08 PM, Xiaowei Bao wrote: >> >> >> -----Original Message----- >> From: Kishon Vijay Abraham I >> Sent: 2018年10月31日 12:15 >> To: Xiaowei Bao ; bhelgaas@google.com; >> robh+dt@kernel.org; mark.rutland@arm.com; shawnguo@kernel.org; Leo Li >> ; lorenzo.pieralisi@arm.com; arnd@arndb.de; >> gregkh@linuxfoundation.org; M.h. Lian ; Mingkai >> Hu ; Roy Zang ; >> kstewart@linuxfoundation.org; cyrille.pitchen@free-electrons.com; >> pombredanne@nexb.com; shawn.lin@rock-chips.com; >> niklas.cassel@axis.com; linux-pci@vger.kernel.org; >> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; >> linux-arm-kernel@lists.infradead.org; linuxppc-dev@lists.ozlabs.org >> Cc: Jiafei Pan >> Subject: Re: [PATCH 5/6] pci: layerscape: Add the EP mode support. >> >> Hi, >> >> On 31/10/18 8:03 AM, Xiaowei Bao wrote: >>> >>> >>> -----Original Message----- >>> From: Xiaowei Bao >>> Sent: 2018年10月26日 17:19 >>> To: 'Kishon Vijay Abraham I' ; bhelgaas@google.com; >>> robh+dt@kernel.org; mark.rutland@arm.com; shawnguo@kernel.org; Leo Li >>> ; lorenzo.pieralisi@arm.com; arnd@arndb.de; >>> gregkh@linuxfoundation.org; M.h. Lian ; >>> Mingkai Hu ; Roy Zang ; >>> kstewart@linuxfoundation.org; cyrille.pitchen@free-electrons.com; >>> pombredanne@nexb.com; shawn.lin@rock-chips.com; >>> niklas.cassel@axis.com; linux-pci@vger.kernel.org; >>> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; >>> linux-arm-kernel@lists.infradead.org; linuxppc-dev@lists.ozlabs.org >>> Cc: Jiafei Pan >>> Subject: RE: [PATCH 5/6] pci: layerscape: Add the EP mode support. >>> >>> >>> >>> -----Original Message----- >>> From: Kishon Vijay Abraham I >>> Sent: 2018年10月26日 13:29 >>> To: Xiaowei Bao ; bhelgaas@google.com; >>> robh+dt@kernel.org; mark.rutland@arm.com; shawnguo@kernel.org; Leo Li >>> ; lorenzo.pieralisi@arm.com; arnd@arndb.de; >>> gregkh@linuxfoundation.org; M.h. Lian ; >>> Mingkai Hu ; Roy Zang ; >>> kstewart@linuxfoundation.org; cyrille.pitchen@free-electrons.com; >>> pombredanne@nexb.com; shawn.lin@rock-chips.com; >>> niklas.cassel@axis.com; linux-pci@vger.kernel.org; >>> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; >>> linux-arm-kernel@lists.infradead.org; linuxppc-dev@lists.ozlabs.org >>> Subject: Re: [PATCH 5/6] pci: layerscape: Add the EP mode support. >>> >>> Hi, >>> >>> On Thursday 25 October 2018 04:39 PM, Xiaowei Bao wrote: >>>> Add the PCIe EP mode support for layerscape platform. >>>> >>>> Signed-off-by: Xiaowei Bao >>>> --- >>>> drivers/pci/controller/dwc/Makefile | 2 +- >>>> drivers/pci/controller/dwc/pci-layerscape-ep.c | 161 >>>> ++++++++++++++++++++++++ >>>> 2 files changed, 162 insertions(+), 1 deletions(-) create mode >>>> 100644 drivers/pci/controller/dwc/pci-layerscape-ep.c >>>> >>>> diff --git a/drivers/pci/controller/dwc/Makefile >>>> b/drivers/pci/controller/dwc/Makefile >>>> index 5d2ce72..b26d617 100644 >>>> --- a/drivers/pci/controller/dwc/Makefile >>>> +++ b/drivers/pci/controller/dwc/Makefile >>>> @@ -8,7 +8,7 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o >>>> obj-$(CONFIG_PCI_IMX6) += pci-imx6.o >>>> obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o >>>> obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o >>>> -obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o >>>> +obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o >>>> +pci-layerscape-ep.o >>>> obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o >>>> obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o >>>> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o diff --git >>>> a/drivers/pci/controller/dwc/pci-layerscape-ep.c >>>> b/drivers/pci/controller/dwc/pci-layerscape-ep.c >>>> new file mode 100644 >>>> index 0000000..3b33bbc >>>> --- /dev/null >>>> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c >>>> @@ -0,0 +1,161 @@ >>>> +// SPDX-License-Identifier: GPL-2.0 >>>> +/* >>>> + * PCIe controller EP driver for Freescale Layerscape SoCs >>>> + * >>>> + * Copyright (C) 2018 NXP Semiconductor. >>>> + * >>>> + * Author: Xiaowei Bao */ >>>> + >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> + >>>> +#include "pcie-designware.h" >>>> + >>>> +#define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/ >>> >>> The base address should come from dt. >>>> + >>>> +struct ls_pcie_ep { >>>> + struct dw_pcie *pci; >>>> +}; >>>> + >>>> +#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev) >>>> + >>>> +static bool ls_pcie_is_bridge(struct ls_pcie_ep *pcie) { >>>> + struct dw_pcie *pci = pcie->pci; >>>> + u32 header_type; >>>> + >>>> + header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE); >>>> + header_type &= 0x7f; >>>> + >>>> + return header_type == PCI_HEADER_TYPE_BRIDGE; } >>>> + >>>> +static int ls_pcie_establish_link(struct dw_pcie *pci) { >>>> + return 0; >>>> +} >>> >>> There should be some way by which EP should tell RC that it is not configured yet. Are there no bits to control LTSSM state initialization or Configuration retry status enabling? >>> [Xiaowei Bao] There have not bits to control LTSSM state to tell the RC it is configured. The start link is auto completed. >>> [Xiaowei Bao] Hi Kishon, is there any advice? >> >> If there is no HW support, I don't think anything could be done here. This could result in RC reading configuration space even before EP is fully initialized. >> [Xiaowei Bao] The bootloader have initialized the EP device and set the config ready bit, and the kernel don't need to do anything. > > What does bootloader initalize? The EP driver here will reinitialize everything right? > [Xiaowei Bao] The bootloader initialize BAR size, outbound window, inbound window and set the config ready bit. How will bootloader know the BAR size? The BAR size is based on the function driver. How does bootloader configure the OB window? The OB window is configured based on the size and address given by the host dynamically at runtime. Thanks Kishon From mboxrd@z Thu Jan 1 00:00:00 1970 From: kishon@ti.com (Kishon Vijay Abraham I) Date: Tue, 6 Nov 2018 11:36:42 +0530 Subject: [PATCH 5/6] pci: layerscape: Add the EP mode support. In-Reply-To: References: <20181025110901.5680-1-xiaowei.bao@nxp.com> <20181025110901.5680-5-xiaowei.bao@nxp.com> <8ec7f502-e058-2c28-9140-5d125e4af6ff@ti.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org (Removed Niklas as mails to him is bouncing) Hi, Please fix your email client. Refer Documentation/process/email-clients.rst On 05/11/18 2:45 PM, Xiaowei Bao wrote: > > > -----Original Message----- > From: Kishon Vijay Abraham I > Sent: 2018?11?5? 16:57 > To: Xiaowei Bao ; bhelgaas at google.com; robh+dt at kernel.org; mark.rutland at arm.com; shawnguo at kernel.org; Leo Li ; lorenzo.pieralisi at arm.com; arnd at arndb.de; gregkh at linuxfoundation.org; M.h. Lian ; Mingkai Hu ; Roy Zang ; kstewart at linuxfoundation.org; cyrille.pitchen at free-electrons.com; pombredanne at nexb.com; shawn.lin at rock-chips.com; niklas.cassel at axis.com; linux-pci at vger.kernel.org; devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linuxppc-dev at lists.ozlabs.org > Cc: Jiafei Pan > Subject: Re: [PATCH 5/6] pci: layerscape: Add the EP mode support. > > Hi, > > On 31/10/18 4:08 PM, Xiaowei Bao wrote: >> >> >> -----Original Message----- >> From: Kishon Vijay Abraham I >> Sent: 2018?10?31? 12:15 >> To: Xiaowei Bao ; bhelgaas at google.com; >> robh+dt at kernel.org; mark.rutland at arm.com; shawnguo at kernel.org; Leo Li >> ; lorenzo.pieralisi at arm.com; arnd at arndb.de; >> gregkh at linuxfoundation.org; M.h. Lian ; Mingkai >> Hu ; Roy Zang ; >> kstewart at linuxfoundation.org; cyrille.pitchen at free-electrons.com; >> pombredanne at nexb.com; shawn.lin at rock-chips.com; >> niklas.cassel at axis.com; linux-pci at vger.kernel.org; >> devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; >> linux-arm-kernel at lists.infradead.org; linuxppc-dev at lists.ozlabs.org >> Cc: Jiafei Pan >> Subject: Re: [PATCH 5/6] pci: layerscape: Add the EP mode support. >> >> Hi, >> >> On 31/10/18 8:03 AM, Xiaowei Bao wrote: >>> >>> >>> -----Original Message----- >>> From: Xiaowei Bao >>> Sent: 2018?10?26? 17:19 >>> To: 'Kishon Vijay Abraham I' ; bhelgaas at google.com; >>> robh+dt at kernel.org; mark.rutland at arm.com; shawnguo at kernel.org; Leo Li >>> ; lorenzo.pieralisi at arm.com; arnd at arndb.de; >>> gregkh at linuxfoundation.org; M.h. Lian ; >>> Mingkai Hu ; Roy Zang ; >>> kstewart at linuxfoundation.org; cyrille.pitchen at free-electrons.com; >>> pombredanne at nexb.com; shawn.lin at rock-chips.com; >>> niklas.cassel at axis.com; linux-pci at vger.kernel.org; >>> devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; >>> linux-arm-kernel at lists.infradead.org; linuxppc-dev at lists.ozlabs.org >>> Cc: Jiafei Pan >>> Subject: RE: [PATCH 5/6] pci: layerscape: Add the EP mode support. >>> >>> >>> >>> -----Original Message----- >>> From: Kishon Vijay Abraham I >>> Sent: 2018?10?26? 13:29 >>> To: Xiaowei Bao ; bhelgaas at google.com; >>> robh+dt at kernel.org; mark.rutland at arm.com; shawnguo at kernel.org; Leo Li >>> ; lorenzo.pieralisi at arm.com; arnd at arndb.de; >>> gregkh at linuxfoundation.org; M.h. Lian ; >>> Mingkai Hu ; Roy Zang ; >>> kstewart at linuxfoundation.org; cyrille.pitchen at free-electrons.com; >>> pombredanne at nexb.com; shawn.lin at rock-chips.com; >>> niklas.cassel at axis.com; linux-pci at vger.kernel.org; >>> devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; >>> linux-arm-kernel at lists.infradead.org; linuxppc-dev at lists.ozlabs.org >>> Subject: Re: [PATCH 5/6] pci: layerscape: Add the EP mode support. >>> >>> Hi, >>> >>> On Thursday 25 October 2018 04:39 PM, Xiaowei Bao wrote: >>>> Add the PCIe EP mode support for layerscape platform. >>>> >>>> Signed-off-by: Xiaowei Bao >>>> --- >>>> drivers/pci/controller/dwc/Makefile | 2 +- >>>> drivers/pci/controller/dwc/pci-layerscape-ep.c | 161 >>>> ++++++++++++++++++++++++ >>>> 2 files changed, 162 insertions(+), 1 deletions(-) create mode >>>> 100644 drivers/pci/controller/dwc/pci-layerscape-ep.c >>>> >>>> diff --git a/drivers/pci/controller/dwc/Makefile >>>> b/drivers/pci/controller/dwc/Makefile >>>> index 5d2ce72..b26d617 100644 >>>> --- a/drivers/pci/controller/dwc/Makefile >>>> +++ b/drivers/pci/controller/dwc/Makefile >>>> @@ -8,7 +8,7 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o >>>> obj-$(CONFIG_PCI_IMX6) += pci-imx6.o >>>> obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o >>>> obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o >>>> -obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o >>>> +obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o >>>> +pci-layerscape-ep.o >>>> obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o >>>> obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o >>>> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o diff --git >>>> a/drivers/pci/controller/dwc/pci-layerscape-ep.c >>>> b/drivers/pci/controller/dwc/pci-layerscape-ep.c >>>> new file mode 100644 >>>> index 0000000..3b33bbc >>>> --- /dev/null >>>> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c >>>> @@ -0,0 +1,161 @@ >>>> +// SPDX-License-Identifier: GPL-2.0 >>>> +/* >>>> + * PCIe controller EP driver for Freescale Layerscape SoCs >>>> + * >>>> + * Copyright (C) 2018 NXP Semiconductor. >>>> + * >>>> + * Author: Xiaowei Bao */ >>>> + >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> + >>>> +#include "pcie-designware.h" >>>> + >>>> +#define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/ >>> >>> The base address should come from dt. >>>> + >>>> +struct ls_pcie_ep { >>>> + struct dw_pcie *pci; >>>> +}; >>>> + >>>> +#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev) >>>> + >>>> +static bool ls_pcie_is_bridge(struct ls_pcie_ep *pcie) { >>>> + struct dw_pcie *pci = pcie->pci; >>>> + u32 header_type; >>>> + >>>> + header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE); >>>> + header_type &= 0x7f; >>>> + >>>> + return header_type == PCI_HEADER_TYPE_BRIDGE; } >>>> + >>>> +static int ls_pcie_establish_link(struct dw_pcie *pci) { >>>> + return 0; >>>> +} >>> >>> There should be some way by which EP should tell RC that it is not configured yet. Are there no bits to control LTSSM state initialization or Configuration retry status enabling? >>> [Xiaowei Bao] There have not bits to control LTSSM state to tell the RC it is configured. The start link is auto completed. >>> [Xiaowei Bao] Hi Kishon, is there any advice? >> >> If there is no HW support, I don't think anything could be done here. This could result in RC reading configuration space even before EP is fully initialized. >> [Xiaowei Bao] The bootloader have initialized the EP device and set the config ready bit, and the kernel don't need to do anything. > > What does bootloader initalize? The EP driver here will reinitialize everything right? > [Xiaowei Bao] The bootloader initialize BAR size, outbound window, inbound window and set the config ready bit. How will bootloader know the BAR size? The BAR size is based on the function driver. How does bootloader configure the OB window? The OB window is configured based on the size and address given by the host dynamically at runtime. Thanks Kishon From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kishon Vijay Abraham I Subject: Re: [PATCH 5/6] pci: layerscape: Add the EP mode support. Date: Tue, 6 Nov 2018 11:36:42 +0530 Message-ID: References: <20181025110901.5680-1-xiaowei.bao@nxp.com> <20181025110901.5680-5-xiaowei.bao@nxp.com> <8ec7f502-e058-2c28-9140-5d125e4af6ff@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Xiaowei Bao , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "arnd@arndb.de" , "gregkh@linuxfoundation.org" , "M.h. Lian" , Mingkai Hu , Roy Zang , "kstewart@linuxfoundation.org" , "cyrille.pitchen@free-electrons.com" , "pombredanne@nexb.com" , "shawn.lin@rock-chips.com" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" "linux-kernel@vger.kernel.org"
  • Cc: Jiafei Pan List-Id: devicetree@vger.kernel.org KFJlbW92ZWQgTmlrbGFzIGFzIG1haWxzIHRvIGhpbSBpcyBib3VuY2luZykKCkhpLAoKUGxlYXNl IGZpeCB5b3VyIGVtYWlsIGNsaWVudC4gUmVmZXIgRG9jdW1lbnRhdGlvbi9wcm9jZXNzL2VtYWls LWNsaWVudHMucnN0CgpPbiAwNS8xMS8xOCAyOjQ1IFBNLCBYaWFvd2VpIEJhbyB3cm90ZToKPiAK PiAKPiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQo+IEZyb206IEtpc2hvbiBWaWpheSBBYnJh aGFtIEkgPGtpc2hvbkB0aS5jb20+IAo+IFNlbnQ6IDIwMTjlubQxMeaciDXml6UgMTY6NTcKPiBU bzogWGlhb3dlaSBCYW8gPHhpYW93ZWkuYmFvQG54cC5jb20+OyBiaGVsZ2Fhc0Bnb29nbGUuY29t OyByb2JoK2R0QGtlcm5lbC5vcmc7IG1hcmsucnV0bGFuZEBhcm0uY29tOyBzaGF3bmd1b0BrZXJu ZWwub3JnOyBMZW8gTGkgPGxlb3lhbmcubGlAbnhwLmNvbT47IGxvcmVuem8ucGllcmFsaXNpQGFy bS5jb207IGFybmRAYXJuZGIuZGU7IGdyZWdraEBsaW51eGZvdW5kYXRpb24ub3JnOyBNLmguIExp YW4gPG1pbmdodWFuLmxpYW5AbnhwLmNvbT47IE1pbmdrYWkgSHUgPG1pbmdrYWkuaHVAbnhwLmNv bT47IFJveSBaYW5nIDxyb3kuemFuZ0BueHAuY29tPjsga3N0ZXdhcnRAbGludXhmb3VuZGF0aW9u Lm9yZzsgY3lyaWxsZS5waXRjaGVuQGZyZWUtZWxlY3Ryb25zLmNvbTsgcG9tYnJlZGFubmVAbmV4 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