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[127.0.0.1]) by director3.derp.mail-out.ovh.net (inspect_sender_mail_agent) with SMTP for ; Tue, 1 Sep 2026 06:59:59 +0000 (UTC) Received: from mta11.priv.ovhmail-u2.ea.mail.ovh.net (unknown [10.110.58.197]) by director3.derp.mail-out.ovh.net (Postfix) with ESMTPS id 4hYxZ70CB8z1xrd; Tue, 1 Sep 2026 06:59:59 +0000 (UTC) Received: from kaod.org (unknown [10.1.6.4]) (Authenticated sender: clg@kaod.org) by mta11.priv.ovhmail-u2.ea.mail.ovh.net (Postfix) with ESMTPSA id 9D91A2403FDA; Tue, 1 Sep 2026 06:59:56 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-99G003a9514f60-3c75-43cb-9300-e752095463b6, 60FF1D1BA71F1148B3CBA6CDBAED02576558214C) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 Message-ID: Date: Tue, 1 Sep 2026 08:59:55 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 10/25] tests/qtest: tmp105: cover one-shot and fault-queue write immunity To: Emmanuel Blot , qemu-devel@nongnu.org Cc: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Steven Lee , Jamin Lin , Kane Chen , Andrew Jeffery , Joel Stanley , qemu-arm@nongnu.org, Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Thomas Huth , =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= , Emmanuel Blot References: <20260731-sanmiguel-bmc-locator-v2-0-1266926ba769@free.fr> <20260731-sanmiguel-bmc-locator-v2-10-1266926ba769@free.fr> From: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= Content-Language: en-US, fr Autocrypt: addr=clg@kaod.org; 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v=1; b=o9LVf4yPCegSgXs1yqzsXUiw/wq25bvzA3Jpaf+EywAIGXxNDYX1JF5MfI+c51tYm2GcI6Ir E5aTOdWcd45ermiXIA8khxzY/F1BnaOf7cE3lECJ7ovdGBhz4FSovsEUCo8EGyPEmnKEZD0avK7 jasfNQ2AyIlgiChokRiCk/VL6i8Z2jZB5U7WIFVgtmS7MtPJVLExD+WRLLRBbyrya1JvxI0cQ6N DDaTrpwuuPTempxoot6YKyBnyg67po3T/UNf+jEktpaU/JFoPZL4d5y6TgLgEm5ZMbw84U9ALgM v2ymUjtoFLLCyR5HvZy+h62QiuV+3PbUudCe7mpuyMuqg== Received-SPF: pass client-ip=51.210.91.14; envelope-from=clg@kaod.org; helo=smtpout5.mo536.mail-out.ovh.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On 7/31/26 12:45, Emmanuel Blot wrote: > Verify that the one-shot (OS) bit triggers a conversion only in shutdown > mode and is ignored in continuous mode, and that > configuration/limit-register writes never advance the fault queue — only > real conversions do. > > Signed-off-by: Emmanuel Blot > --- > tests/qtest/tmp105-test.c | 102 ++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 102 insertions(+) > > diff --git a/tests/qtest/tmp105-test.c b/tests/qtest/tmp105-test.c > index ea6803715a..e586a634d8 100644 > --- a/tests/qtest/tmp105-test.c > +++ b/tests/qtest/tmp105-test.c > @@ -33,6 +33,8 @@ > #define TMP105_CONFIG_FQ_1 (0 << 3) /* fault queue: 1 consecutive fault */ > #define TMP105_CONFIG_FQ_4 (2 << 3) /* fault queue: 4 consecutive faults */ > #define TMP105_CONFIG_FQ(f) ((f) << 3) /* raw F1:F0 fault-queue field value */ > +#define TMP105_CONFIG_SD (1 << 0) /* shutdown mode */ > +#define TMP105_CONFIG_OS (1 << 7) /* one-shot conversion */ > > static int qmp_tmp105_get_temperature(const char *id) > { > @@ -200,6 +202,102 @@ static void check_fault_queue(QI2CDevice *i2cdev, const char *id, > g_assert_true(get_irq(0)); > } > > +/* > + * The one-shot (OS) bit starts a conversion only in shutdown mode. In > + * continuous mode it is ignored, so writing it must not advance the fault > + * queue; in shutdown each OS write performs one conversion that does. > + */ > +static void test_one_shot(void *obj, void *data, QGuestAllocator *alloc) > +{ > + QI2CDevice *i2cdev = (QI2CDevice *)obj; > + int i; > + > + qtest_irq_intercept_out(global_qtest, TMP105_TEST_PATH); > + > + i2c_set8(i2cdev, TMP105_REG_CONFIG, TMP105_CONFIG_POL | TMP105_CONFIG_FQ_4); > + qmp_tmp105_set_temperature(TMP105_TEST_ID, 85000); > + g_assert_false(get_irq(0)); > + > + for (i = 0; i < 8; i++) { > + i2c_set8(i2cdev, TMP105_REG_CONFIG, > + TMP105_CONFIG_POL | TMP105_CONFIG_FQ_4 | TMP105_CONFIG_OS); > + g_assert_false(get_irq(0)); > + } > + > + i2c_set8(i2cdev, TMP105_REG_CONFIG, > + TMP105_CONFIG_POL | TMP105_CONFIG_FQ_4 | TMP105_CONFIG_SD); > + for (i = 0; i < 2; i++) { > + i2c_set8(i2cdev, TMP105_REG_CONFIG, TMP105_CONFIG_POL | > + TMP105_CONFIG_FQ_4 | TMP105_CONFIG_SD | TMP105_CONFIG_OS); > + g_assert_false(get_irq(0)); > + } > + i2c_set8(i2cdev, TMP105_REG_CONFIG, TMP105_CONFIG_POL | > + TMP105_CONFIG_FQ_4 | TMP105_CONFIG_SD | TMP105_CONFIG_OS); > + g_assert_true(get_irq(0)); > +} > + > +/* > + * Configuration and limit-register writes are not conversions and must not > + * advance the fault queue. > + */ > +static void test_fault_queue_ignores_writes(void *obj, void *data, > + QGuestAllocator *alloc) > +{ > + QI2CDevice *i2cdev = (QI2CDevice *)obj; > + int i; > + > + qtest_irq_intercept_out(global_qtest, TMP105_TEST_PATH); > + > + i2c_set8(i2cdev, TMP105_REG_CONFIG, TMP105_CONFIG_POL | TMP105_CONFIG_FQ_4); > + g_assert_false(get_irq(0)); > + > + qmp_tmp105_set_temperature(TMP105_TEST_ID, 85000); > + g_assert_false(get_irq(0)); > + > + for (i = 0; i < 8; i++) { > + i2c_set8(i2cdev, TMP105_REG_CONFIG, > + TMP105_CONFIG_POL | TMP105_CONFIG_FQ_4); > + i2c_set16(i2cdev, TMP105_REG_T_HIGH, 0x5000); > + i2c_set16(i2cdev, TMP105_REG_T_LOW, 0x4b00); > + g_assert_false(get_irq(0)); > + } > + > + for (i = 0; i < 2; i++) { > + qmp_tmp105_set_temperature(TMP105_TEST_ID, 85000); > + g_assert_false(get_irq(0)); > + } > + qmp_tmp105_set_temperature(TMP105_TEST_ID, 85000); > + g_assert_true(get_irq(0)); > +} > + > +/* > + * Leaving shutdown (SD 1->0) resumes continuous conversion, which must > + * re-evaluate the current temperature against the limits. > + */ > +static void test_wake_from_shutdown(void *obj, void *data, > + QGuestAllocator *alloc) > +{ > + QI2CDevice *i2cdev = (QI2CDevice *)obj; > + > + qtest_irq_intercept_out(global_qtest, TMP105_TEST_PATH); > + > + i2c_set8(i2cdev, TMP105_REG_CONFIG, TMP105_CONFIG_POL | TMP105_CONFIG_FQ_1); > + g_assert_false(get_irq(0)); > + > + qmp_tmp105_set_temperature(TMP105_TEST_ID, 85000); > + g_assert_true(get_irq(0)); > + > + i2c_set8(i2cdev, TMP105_REG_CONFIG, > + TMP105_CONFIG_POL | TMP105_CONFIG_FQ_1 | TMP105_CONFIG_SD); > + g_assert_true(get_irq(0)); > + > + qmp_tmp105_set_temperature(TMP105_TEST_ID, 70000); > + g_assert_true(get_irq(0)); > + > + i2c_set8(i2cdev, TMP105_REG_CONFIG, TMP105_CONFIG_POL | TMP105_CONFIG_FQ_1); > + g_assert_false(get_irq(0)); > +} > + > /* The TMP75 maps F1:F0 = 10b to 3 consecutive faults. */ > static void test_tmp75_fault_queue(void *obj, void *data, > QGuestAllocator *alloc) > @@ -282,6 +380,10 @@ static void tmp105_register_nodes(void) > qos_add_test("tx-rx", "tmp105", send_and_receive, NULL); > qos_add_test("alert-single-fault", "tmp105", test_alert_single_fault, NULL); > qos_add_test("fault-queue", "tmp105", test_fault_queue, NULL); > + qos_add_test("fault-queue-ignores-writes", "tmp105", > + test_fault_queue_ignores_writes, NULL); > + qos_add_test("one-shot", "tmp105", test_one_shot, NULL); > + qos_add_test("wake-from-shutdown", "tmp105", test_wake_from_shutdown, NULL); > > /* TMP75: register-compatible, but with a 1/2/3/4 fault queue. */ > QOSGraphEdgeOptions tmp75_opts = { > Reviewed-by: Cédric Le Goater Thanks, C.