From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] intel-dri: Fix initialization if startup happens in interlaced mode Date: Mon, 14 Nov 2011 10:10:48 +0000 Message-ID: References: <4EC031D9.80204@digadd.de> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id A13649E97B for ; Mon, 14 Nov 2011 02:10:56 -0800 (PST) In-Reply-To: <4EC031D9.80204@digadd.de> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: Christian Schmidt , dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org On Sun, 13 Nov 2011 22:08:41 +0100, Christian Schmidt wrote: > My EFI BIOS starts the graphics card up in my projector's preferred EDID > mode, 1080@60i. The Intel driver does not clear the interlaced bit: > > #define PIPECONF_PROGRESSIVE (0 << 21) > #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) > #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) > > Likewise, I suppose that this bit is not set for interlaced modes > either, however interlaced modes are discarded anyway. The patch is correct, we do need to clear all 3 bits to restore progressive mode. However it would be better to add a new #define PIPECONF_INTERLACE_MASK (7 << 21) so that we do not confuse clearing all interlace bits with unsetting a particular mode. -Chris -- Chris Wilson, Intel Open Source Technology Centre