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diff for duplicates of <e10be3d24de889e9e80d2fd76de9dcd8@mail.gmail.com>

diff --git a/a/1.txt b/N1/1.txt
index 782782f..816ed46 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -24,127 +24,101 @@ Bluestone board.
 
 > +static int apm821xx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
 > +{
-> + =A0 =A0 =A0 u32 val;
-> + =A0 =A0 =A0 u32 utlset1;
-> + =A0 =A0 =A0 u32 timeout;
+> +       u32 val;
+> +       u32 utlset1;
+> +       u32 timeout;
 > +
-> + =A0 =A0 =A0 /*
-> + =A0 =A0 =A0 =A0* Do a software reset on PCIe ports.
-> + =A0 =A0 =A0 =A0* This code is to fix the issue that pci drivers doesn't
+> +       /*
+> +        * Do a software reset on PCIe ports.
+> +        * This code is to fix the issue that pci drivers doesn't
 re-assign
-> + =A0 =A0 =A0 =A0* bus number for PCIE devices after Uboot
-> + =A0 =A0 =A0 =A0* scanned and configured all the buses (eg. PCIE NIC
+> +        * bus number for PCIE devices after Uboot
+> +        * scanned and configured all the buses (eg. PCIE NIC
 IntelPro/1000
-> + =A0 =A0 =A0 =A0* PT quad port, SAS LSI 1064E)
-> + =A0 =A0 =A0 =A0*/
+> +        * PT quad port, SAS LSI 1064E)
+> +        */
 > +
-> + =A0 =A0 =A0 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST + (port->index * 0x55=
-),
+> +       mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST + (port->index * 0x55),
 0x0);
-> + =A0 =A0 =A0 mdelay(10);
+> +       mdelay(10);
 > +
-> + =A0 =A0 =A0 if (port->endpoint)
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 val =3D PTYPE_LEGACY_ENDPOINT << 20;
-> + =A0 =A0 =A0 else
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 val =3D PTYPE_ROOT_PORT << 20;
+> +       if (port->endpoint)
+> +               val = PTYPE_LEGACY_ENDPOINT << 20;
+> +       else
+> +               val = PTYPE_ROOT_PORT << 20;
 > +
-> + =A0 =A0 =A0 if (port->index =3D=3D 0) {
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 val |=3D LNKW_X1 << 12;
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 utlset1 =3D 0x00000000;
-> + =A0 =A0 =A0 } else {
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 val |=3D LNKW_X4 << 12;
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 utlset1 =3D 0x20101101;
-> + =A0 =A0 =A0 }
+> +       if (port->index == 0) {
+> +               val |= LNKW_X1 << 12;
+> +               utlset1 = 0x00000000;
+> +       } else {
+> +               val |= LNKW_X4 << 12;
+> +               utlset1 = 0x20101101;
+> +       }
 > +
-> + =A0 =A0 =A0 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
-> + =A0 =A0 =A0 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
-> + =A0 =A0 =A0 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
+> +       mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
+> +       mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
+> +       mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
 > +
-> + =A0 =A0 =A0 switch (port->index) {
-> + =A0 =A0 =A0 case 0:
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003=
-230);
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130=
-);
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006=
-);
+> +       switch (port->index) {
+> +       case 0:
+> +               mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
+> +               mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
+> +               mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
 > +
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10=
-000000);
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mdelay(50);
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30=
-000000);
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 break;
+> +               mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
+> +               mdelay(50);
+> +               mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
+> +               break;
 > +
-> + =A0 =A0 =A0 case 1:
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003=
-230);
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003=
-230);
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003=
-230);
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003=
-230);
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130=
-);
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130=
-);
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130=
-);
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130=
-);
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006=
-);
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006=
-);
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006=
-);
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006=
-);
+> +       case 1:
+> +               mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
+> +               mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
+> +               mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
+> +               mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
+> +               mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130);
+> +               mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130);
+> +               mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130);
+> +               mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130);
+> +               mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
+> +               mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
+> +               mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
+> +               mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
 > +
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST, 0x10=
-000000);
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 break;
-> + =A0 =A0 =A0 }
+> +               mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST, 0x10000000);
+> +               break;
+> +       }
 
 Do we need a default case here to catch oddness and exit the function?
 [Vinh Nguyen] we've already checked the port->index before calling this
 function, so we assume that the port->index never exceed the checked
 values.
 > +
-> + =A0 =A0 =A0 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET=
-) |
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN=
-));
+> +       mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
+> +               mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
+> +               (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
 > +
-> + =A0 =A0 =A0 /* Poll for PHY reset */
-> + =A0 =A0 =A0 timeout =3D 0;
-> + =A0 =A0 =A0 while ((!(mfdcri(SDR0, PESDR0_460EX_RSTSTA +
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (port->index * 0x55)) & 0x1=
-)) &&
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(timeout < PCIE_PHY_RESET_TIMEOUT)) {
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 udelay(10);
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 timeout++;
-> + =A0 =A0 =A0 }
+> +       /* Poll for PHY reset */
+> +       timeout = 0;
+> +       while ((!(mfdcri(SDR0, PESDR0_460EX_RSTSTA +
+> +                       (port->index * 0x55)) & 0x1)) &&
+> +                (timeout < PCIE_PHY_RESET_TIMEOUT)) {
+> +               udelay(10);
+> +               timeout++;
+> +       }
 > +
-> + =A0 =A0 =A0 if (timeout < PCIE_PHY_RESET_TIMEOUT) {
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET=
-,
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (mfdcri(SDR0, port->sdr_bas=
-e + PESDRn_RCSSET) &
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ~(PESDRx_RCSSET_RSTGU | PES=
-DRx_RCSSET_RSTDL)) |
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PESDRx_RCSSET_RSTPYN);
+> +       if (timeout < PCIE_PHY_RESET_TIMEOUT) {
+> +               mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
+> +                       (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
+> +                       ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
+> +                       PESDRx_RCSSET_RSTPYN);
 > +
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 port->has_ibpre =3D 1;
+> +               port->has_ibpre = 1;
 > +
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 return 0;
-> + =A0 =A0 =A0 } else {
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 printk(KERN_INFO "PCIE: Can't reset PHY\n")=
-;
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 return -1;
-> + =A0 =A0 =A0 }
+> +               return 0;
+> +       } else {
+> +               printk(KERN_INFO "PCIE: Can't reset PHY\n");
+> +               return -1;
+> +       }
 
 If we can't reset the PHY, does this whole function essentially fail?
 Do the devices not get renumbered, etc?  If so, you probably want to
@@ -153,26 +127,18 @@ make that KERN_ERR.
 properly. I will update codes to return the error in case PHY can't reset.
 > @@ -1751,9 +1856,9 @@ static void __init
 ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
-> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 * if it works
-> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 */
-> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0out_le32(mbase + PECFG_PIM0LAL, 0x00000000=
-);
-> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_le32(mbase + PECFG_PIM0LAH, 0x00000000)=
-;
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_le32(mbase + PECFG_PIM0LAH, 0x00000008)=
-; /* Moving
+>                 * if it works
+>                 */
+>                out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
+> -               out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
+> +               out_le32(mbase + PECFG_PIM0LAH, 0x00000008); /* Moving
 on HB */
-> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0out_le32(mbase + PECFG_PIM1LAL, 0x00000000=
-);
-> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_le32(mbase + PECFG_PIM1LAH, 0x00000000)=
-;
-> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_le32(mbase + PECFG_PIM1LAH, 0x0000000c)=
-; /* Moving
+>                out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
+> -               out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
+> +               out_le32(mbase + PECFG_PIM1LAH, 0x0000000c); /* Moving
 on HB */
-> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0out_le32(mbase + PECFG_PIM01SAH, 0xffff000=
-0);
-> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0out_le32(mbase + PECFG_PIM01SAL, 0x0000000=
-0);
+>                out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
+>                out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
 
 Why are these values changed, and are those changes only needed on
 APM821xx?
@@ -186,24 +152,24 @@ b/arch/powerpc/sysdev/ppc4xx_pci.h
 > --- a/arch/powerpc/sysdev/ppc4xx_pci.h
 > +++ b/arch/powerpc/sysdev/ppc4xx_pci.h
 > @@ -441,6 +441,7 @@
-> =A0/*
-> =A0* Config space register offsets
-> =A0*/
-> +#define PECFG_ECDEVCTL =A0 =A0 =A0 =A0 0x060
-> =A0#define PECFG_ECRTCTL =A0 =A0 =A0 =A0 =A00x074
+>  /*
+>  * Config space register offsets
+>  */
+> +#define PECFG_ECDEVCTL         0x060
+>  #define PECFG_ECRTCTL          0x074
 >
-> =A0#define PECFG_BAR0LMPA =A0 =A0 =A0 =A0 0x210
+>  #define PECFG_BAR0LMPA         0x210
 > @@ -448,6 +449,7 @@
-> =A0#define PECFG_BAR1MPA =A0 =A0 =A0 =A0 =A00x218
-> =A0#define PECFG_BAR2LMPA =A0 =A0 =A0 =A0 0x220
-> =A0#define PECFG_BAR2HMPA =A0 =A0 =A0 =A0 0x224
-> +#define PECFG_ECDEVCAPPA =A0 =A0 =A0 0x25c
+>  #define PECFG_BAR1MPA          0x218
+>  #define PECFG_BAR2LMPA         0x220
+>  #define PECFG_BAR2HMPA         0x224
+> +#define PECFG_ECDEVCAPPA       0x25c
 >
-> =A0#define PECFG_PIMEN =A0 =A0 =A0 =A0 =A0 =A00x33c
-> =A0#define PECFG_PIM0LAL =A0 =A0 =A0 =A0 =A00x340
+>  #define PECFG_PIMEN            0x33c
+>  #define PECFG_PIM0LAL          0x340
 > @@ -494,5 +496,7 @@ enum
-> =A0 =A0 =A0 =A0LNKW_X8 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D 0x8
-> =A0};
+>        LNKW_X8                 = 0x8
+>  };
 >
 > +/* Timout for reset phy */
 > +#define PCIE_PHY_RESET_TIMEOUT 10
diff --git a/a/content_digest b/N1/content_digest
index d9b1bad..ff3758d 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -4,14 +4,19 @@
  "Subject\0RE: [PATCH 3/3] powerpc/44x: Add support PCI-E for APM821xx SoC and Bluestone board\0"
  "Date\0Wed, 21 Dec 2011 11:47:07 +0700\0"
  "To\0Josh Boyer <jwboyer@gmail.com>\0"
- "Cc\0Ayman El-Khashab <ayman@elkhashab.com>"
-  Dave Kleikamp <shaggy@linux.vnet.ibm.com>
-  Lucas De Marchi <lucas.demarchi@profusion.mobi>
-  Rob Herring <rob.herring@calxeda.com>
-  Paul Gortmaker <paul.gortmaker@windriver.com>
+ "Cc\0Benjamin Herrenschmidt <benh@kernel.crashing.org>"
   Paul Mackerras <paulus@samba.org>
+  Matt Porter <mporter@kernel.crashing.org>
+  Kumar Gala <galak@kernel.crashing.org>
+  Paul Gortmaker <paul.gortmaker@windriver.com>
   Anton Blanchard <anton@samba.org>
+  Dave Kleikamp <shaggy@linux.vnet.ibm.com>
+  Grant Likely <grant.likely@secretlab.ca>
+  Tony Breeds <tony@bakeyournoodle.com>
+  Rob Herring <rob.herring@calxeda.com>
   Jiri Kosina <jkosina@suse.cz>
+  Lucas De Marchi <lucas.demarchi@profusion.mobi>
+  Ayman El-Khashab <ayman@elkhashab.com>
   linuxppc-dev@lists.ozlabs.org
  " linux-kernel@vger.kernel.org\0"
  "\00:1\0"
@@ -42,127 +47,101 @@
  "\n"
  "> +static int apm821xx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)\n"
  "> +{\n"
- "> + =A0 =A0 =A0 u32 val;\n"
- "> + =A0 =A0 =A0 u32 utlset1;\n"
- "> + =A0 =A0 =A0 u32 timeout;\n"
+ "> + \302\240 \302\240 \302\240 u32 val;\n"
+ "> + \302\240 \302\240 \302\240 u32 utlset1;\n"
+ "> + \302\240 \302\240 \302\240 u32 timeout;\n"
  "> +\n"
- "> + =A0 =A0 =A0 /*\n"
- "> + =A0 =A0 =A0 =A0* Do a software reset on PCIe ports.\n"
- "> + =A0 =A0 =A0 =A0* This code is to fix the issue that pci drivers doesn't\n"
+ "> + \302\240 \302\240 \302\240 /*\n"
+ "> + \302\240 \302\240 \302\240 \302\240* Do a software reset on PCIe ports.\n"
+ "> + \302\240 \302\240 \302\240 \302\240* This code is to fix the issue that pci drivers doesn't\n"
  "re-assign\n"
- "> + =A0 =A0 =A0 =A0* bus number for PCIE devices after Uboot\n"
- "> + =A0 =A0 =A0 =A0* scanned and configured all the buses (eg. PCIE NIC\n"
+ "> + \302\240 \302\240 \302\240 \302\240* bus number for PCIE devices after Uboot\n"
+ "> + \302\240 \302\240 \302\240 \302\240* scanned and configured all the buses (eg. PCIE NIC\n"
  "IntelPro/1000\n"
- "> + =A0 =A0 =A0 =A0* PT quad port, SAS LSI 1064E)\n"
- "> + =A0 =A0 =A0 =A0*/\n"
+ "> + \302\240 \302\240 \302\240 \302\240* PT quad port, SAS LSI 1064E)\n"
+ "> + \302\240 \302\240 \302\240 \302\240*/\n"
  "> +\n"
- "> + =A0 =A0 =A0 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST + (port->index * 0x55=\n"
- "),\n"
+ "> + \302\240 \302\240 \302\240 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST + (port->index * 0x55),\n"
  "0x0);\n"
- "> + =A0 =A0 =A0 mdelay(10);\n"
+ "> + \302\240 \302\240 \302\240 mdelay(10);\n"
  "> +\n"
- "> + =A0 =A0 =A0 if (port->endpoint)\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 val =3D PTYPE_LEGACY_ENDPOINT << 20;\n"
- "> + =A0 =A0 =A0 else\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 val =3D PTYPE_ROOT_PORT << 20;\n"
+ "> + \302\240 \302\240 \302\240 if (port->endpoint)\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 val = PTYPE_LEGACY_ENDPOINT << 20;\n"
+ "> + \302\240 \302\240 \302\240 else\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 val = PTYPE_ROOT_PORT << 20;\n"
  "> +\n"
- "> + =A0 =A0 =A0 if (port->index =3D=3D 0) {\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 val |=3D LNKW_X1 << 12;\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 utlset1 =3D 0x00000000;\n"
- "> + =A0 =A0 =A0 } else {\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 val |=3D LNKW_X4 << 12;\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 utlset1 =3D 0x20101101;\n"
- "> + =A0 =A0 =A0 }\n"
+ "> + \302\240 \302\240 \302\240 if (port->index == 0) {\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 val |= LNKW_X1 << 12;\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 utlset1 = 0x00000000;\n"
+ "> + \302\240 \302\240 \302\240 } else {\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 val |= LNKW_X4 << 12;\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 utlset1 = 0x20101101;\n"
+ "> + \302\240 \302\240 \302\240 }\n"
  "> +\n"
- "> + =A0 =A0 =A0 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);\n"
- "> + =A0 =A0 =A0 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);\n"
- "> + =A0 =A0 =A0 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);\n"
+ "> + \302\240 \302\240 \302\240 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);\n"
+ "> + \302\240 \302\240 \302\240 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);\n"
+ "> + \302\240 \302\240 \302\240 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);\n"
  "> +\n"
- "> + =A0 =A0 =A0 switch (port->index) {\n"
- "> + =A0 =A0 =A0 case 0:\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003=\n"
- "230);\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130=\n"
- ");\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006=\n"
- ");\n"
+ "> + \302\240 \302\240 \302\240 switch (port->index) {\n"
+ "> + \302\240 \302\240 \302\240 case 0:\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);\n"
  "> +\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10=\n"
- "000000);\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mdelay(50);\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30=\n"
- "000000);\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 break;\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mdelay(50);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 break;\n"
  "> +\n"
- "> + =A0 =A0 =A0 case 1:\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003=\n"
- "230);\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003=\n"
- "230);\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003=\n"
- "230);\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003=\n"
- "230);\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130=\n"
- ");\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130=\n"
- ");\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130=\n"
- ");\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130=\n"
- ");\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006=\n"
- ");\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006=\n"
- ");\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006=\n"
- ");\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006=\n"
- ");\n"
+ "> + \302\240 \302\240 \302\240 case 1:\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);\n"
  "> +\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST, 0x10=\n"
- "000000);\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 break;\n"
- "> + =A0 =A0 =A0 }\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST, 0x10000000);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 break;\n"
+ "> + \302\240 \302\240 \302\240 }\n"
  "\n"
  "Do we need a default case here to catch oddness and exit the function?\n"
  "[Vinh Nguyen] we've already checked the port->index before calling this\n"
  "function, so we assume that the port->index never exceed the checked\n"
  "values.\n"
  "> +\n"
- "> + =A0 =A0 =A0 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET=\n"
- ") |\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN=\n"
- "));\n"
+ "> + \302\240 \302\240 \302\240 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));\n"
  "> +\n"
- "> + =A0 =A0 =A0 /* Poll for PHY reset */\n"
- "> + =A0 =A0 =A0 timeout =3D 0;\n"
- "> + =A0 =A0 =A0 while ((!(mfdcri(SDR0, PESDR0_460EX_RSTSTA +\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (port->index * 0x55)) & 0x1=\n"
- ")) &&\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(timeout < PCIE_PHY_RESET_TIMEOUT)) {\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 udelay(10);\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 timeout++;\n"
- "> + =A0 =A0 =A0 }\n"
+ "> + \302\240 \302\240 \302\240 /* Poll for PHY reset */\n"
+ "> + \302\240 \302\240 \302\240 timeout = 0;\n"
+ "> + \302\240 \302\240 \302\240 while ((!(mfdcri(SDR0, PESDR0_460EX_RSTSTA +\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 (port->index * 0x55)) & 0x1)) &&\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240(timeout < PCIE_PHY_RESET_TIMEOUT)) {\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 udelay(10);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 timeout++;\n"
+ "> + \302\240 \302\240 \302\240 }\n"
  "> +\n"
- "> + =A0 =A0 =A0 if (timeout < PCIE_PHY_RESET_TIMEOUT) {\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET=\n"
- ",\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (mfdcri(SDR0, port->sdr_bas=\n"
- "e + PESDRn_RCSSET) &\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ~(PESDRx_RCSSET_RSTGU | PES=\n"
- "DRx_RCSSET_RSTDL)) |\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PESDRx_RCSSET_RSTPYN);\n"
+ "> + \302\240 \302\240 \302\240 if (timeout < PCIE_PHY_RESET_TIMEOUT) {\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 PESDRx_RCSSET_RSTPYN);\n"
  "> +\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 port->has_ibpre =3D 1;\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 port->has_ibpre = 1;\n"
  "> +\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 return 0;\n"
- "> + =A0 =A0 =A0 } else {\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 printk(KERN_INFO \"PCIE: Can't reset PHY\\n\")=\n"
- ";\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 return -1;\n"
- "> + =A0 =A0 =A0 }\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return 0;\n"
+ "> + \302\240 \302\240 \302\240 } else {\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 printk(KERN_INFO \"PCIE: Can't reset PHY\\n\");\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return -1;\n"
+ "> + \302\240 \302\240 \302\240 }\n"
  "\n"
  "If we can't reset the PHY, does this whole function essentially fail?\n"
  "Do the devices not get renumbered, etc?  If so, you probably want to\n"
@@ -171,26 +150,18 @@
  "properly. I will update codes to return the error in case PHY can't reset.\n"
  "> @@ -1751,9 +1856,9 @@ static void __init\n"
  "ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,\n"
- "> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 * if it works\n"
- "> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 */\n"
- "> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0out_le32(mbase + PECFG_PIM0LAL, 0x00000000=\n"
- ");\n"
- "> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_le32(mbase + PECFG_PIM0LAH, 0x00000000)=\n"
- ";\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_le32(mbase + PECFG_PIM0LAH, 0x00000008)=\n"
- "; /* Moving\n"
+ "> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 * if it works\n"
+ "> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 */\n"
+ "> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240out_le32(mbase + PECFG_PIM0LAL, 0x00000000);\n"
+ "> - \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 out_le32(mbase + PECFG_PIM0LAH, 0x00000000);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 out_le32(mbase + PECFG_PIM0LAH, 0x00000008); /* Moving\n"
  "on HB */\n"
- "> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0out_le32(mbase + PECFG_PIM1LAL, 0x00000000=\n"
- ");\n"
- "> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_le32(mbase + PECFG_PIM1LAH, 0x00000000)=\n"
- ";\n"
- "> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_le32(mbase + PECFG_PIM1LAH, 0x0000000c)=\n"
- "; /* Moving\n"
+ "> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240out_le32(mbase + PECFG_PIM1LAL, 0x00000000);\n"
+ "> - \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 out_le32(mbase + PECFG_PIM1LAH, 0x00000000);\n"
+ "> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 out_le32(mbase + PECFG_PIM1LAH, 0x0000000c); /* Moving\n"
  "on HB */\n"
- "> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0out_le32(mbase + PECFG_PIM01SAH, 0xffff000=\n"
- "0);\n"
- "> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0out_le32(mbase + PECFG_PIM01SAL, 0x0000000=\n"
- "0);\n"
+ "> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);\n"
+ "> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240out_le32(mbase + PECFG_PIM01SAL, 0x00000000);\n"
  "\n"
  "Why are these values changed, and are those changes only needed on\n"
  "APM821xx?\n"
@@ -204,24 +175,24 @@
  "> --- a/arch/powerpc/sysdev/ppc4xx_pci.h\n"
  "> +++ b/arch/powerpc/sysdev/ppc4xx_pci.h\n"
  "> @@ -441,6 +441,7 @@\n"
- "> =A0/*\n"
- "> =A0* Config space register offsets\n"
- "> =A0*/\n"
- "> +#define PECFG_ECDEVCTL =A0 =A0 =A0 =A0 0x060\n"
- "> =A0#define PECFG_ECRTCTL =A0 =A0 =A0 =A0 =A00x074\n"
+ "> \302\240/*\n"
+ "> \302\240* Config space register offsets\n"
+ "> \302\240*/\n"
+ "> +#define PECFG_ECDEVCTL \302\240 \302\240 \302\240 \302\240 0x060\n"
+ "> \302\240#define PECFG_ECRTCTL \302\240 \302\240 \302\240 \302\240 \302\2400x074\n"
  ">\n"
- "> =A0#define PECFG_BAR0LMPA =A0 =A0 =A0 =A0 0x210\n"
+ "> \302\240#define PECFG_BAR0LMPA \302\240 \302\240 \302\240 \302\240 0x210\n"
  "> @@ -448,6 +449,7 @@\n"
- "> =A0#define PECFG_BAR1MPA =A0 =A0 =A0 =A0 =A00x218\n"
- "> =A0#define PECFG_BAR2LMPA =A0 =A0 =A0 =A0 0x220\n"
- "> =A0#define PECFG_BAR2HMPA =A0 =A0 =A0 =A0 0x224\n"
- "> +#define PECFG_ECDEVCAPPA =A0 =A0 =A0 0x25c\n"
+ "> \302\240#define PECFG_BAR1MPA \302\240 \302\240 \302\240 \302\240 \302\2400x218\n"
+ "> \302\240#define PECFG_BAR2LMPA \302\240 \302\240 \302\240 \302\240 0x220\n"
+ "> \302\240#define PECFG_BAR2HMPA \302\240 \302\240 \302\240 \302\240 0x224\n"
+ "> +#define PECFG_ECDEVCAPPA \302\240 \302\240 \302\240 0x25c\n"
  ">\n"
- "> =A0#define PECFG_PIMEN =A0 =A0 =A0 =A0 =A0 =A00x33c\n"
- "> =A0#define PECFG_PIM0LAL =A0 =A0 =A0 =A0 =A00x340\n"
+ "> \302\240#define PECFG_PIMEN \302\240 \302\240 \302\240 \302\240 \302\240 \302\2400x33c\n"
+ "> \302\240#define PECFG_PIM0LAL \302\240 \302\240 \302\240 \302\240 \302\2400x340\n"
  "> @@ -494,5 +496,7 @@ enum\n"
- "> =A0 =A0 =A0 =A0LNKW_X8 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D 0x8\n"
- "> =A0};\n"
+ "> \302\240 \302\240 \302\240 \302\240LNKW_X8 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 = 0x8\n"
+ "> \302\240};\n"
  ">\n"
  "> +/* Timout for reset phy */\n"
  "> +#define PCIE_PHY_RESET_TIMEOUT 10\n"
@@ -230,4 +201,4 @@
  "[Vinh Nguyen] At this time, we only checked this on APM821xx chips.\n"
  josh
 
-d0b5d355725e8ef5940c3ef2b2407e258c3bf3616c3c4d1046acdad5259e611e
+16f90c1b9dbe26a3de75b789e4cc6d96e9f094e9c067ae46d40b1cad9db6b5b9

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