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[216.71.219.44]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-302978ad18asm7531719eec.26.2026.05.15.10.10.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 May 2026 10:10:04 -0700 (PDT) Message-ID: Date: Fri, 15 May 2026 10:10:02 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 12/20] target/arm: Extract common code related to 'max' CPU To: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?Q?C=C3=A9dric_Le_Goate?= =?UTF-8?Q?r?= , Richard Henderson , qemu-arm@nongnu.org, Joel Stanley , Kane Chen , Troy Lee , Jamin Lin , Steven Lee , Andrew Jeffery , Manos Pitsidianakis References: <20260515141032.3271-1-philmd@linaro.org> <20260515141032.3271-13-philmd@linaro.org> From: Pierrick Bouvier Content-Language: en-US In-Reply-To: <20260515141032.3271-13-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE1MDE3NSBTYWx0ZWRfX6MOycvgp93i5 afcpKVayOonmgClDEbR8R74nix4wCemuwgDcptbVx9Qq6kVs6Jq3JtIdCvJCoyLb1j9loys+F06 m5OfxiXxp7cdndHINRTS8U2ypth+++bkjxGp3jD52oTWJu6huFjAte8zM47bSeM6+ZCSMs2NjUM L0bVwbdcTdHC4Kahc7Vdx98AZ4sFdawvg15IkdyBNQcwHabtzUb1c/87CD5C4WPlnHgvKFzPCod m+A1XjOrLQ7hWx4q2GNZQsJlOkjCw+nsE3nbPHFQXukGTGaV7ui0zS/z3tcMW1KqHma3HTT64jT /GOeMggVhTmNQ+0I1SourlGLkwsx1CH1jAjEdQLnro6Y91T/n/Kl+bps4j0dA7k18TRuyxKR5CL iQPMphG7gbMPKktHj5vMhu7Uz3B7RJ1JH8fGKNDKCIlnj16L/pv4K71jejV6N32jP2tVQc0LL31 sqbnBLVjAcggS+caEPw== X-Proofpoint-GUID: piTFa9jEKLM6vr7lU_s0mbBRGFC_PJUJ X-Proofpoint-ORIG-GUID: piTFa9jEKLM6vr7lU_s0mbBRGFC_PJUJ X-Authority-Analysis: v=2.4 cv=HJ7z0Itv c=1 sm=1 tr=0 ts=6a07536e cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=iLqgmErQAxjCjdq5jj1Aqg==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=bcbY33BGdfAjHCA2VuMA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-15_04,2026-05-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 phishscore=0 spamscore=0 clxscore=1015 impostorscore=0 adultscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605150175 Received-SPF: pass client-ip=205.220.180.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On 5/15/2026 7:10 AM, Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé > --- > target/arm/cpu-max.c | 106 +++++++++++++++++++++++++++++++++++++++++ > target/arm/tcg/cpu32.c | 96 ------------------------------------- > target/arm/meson.build | 1 + > 3 files changed, 107 insertions(+), 96 deletions(-) > create mode 100644 target/arm/cpu-max.c > > diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c > new file mode 100644 > index 00000000000..9fd48ce46e2 > --- /dev/null > +++ b/target/arm/cpu-max.c > @@ -0,0 +1,106 @@ > +/* > + * QEMU ARM 'max' CPU > + * > + * Copyright (c) 2018 Linaro Ltd > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include "qemu/osdep.h" > +#include "target/arm/internals.h" > + > +/* Share AArch32 -cpu max features with AArch64. */ > +void aa32_max_features(ARMCPU *cpu) > +{ > + uint32_t t; > + ARMISARegisters *isar = &cpu->isar; > + > + /* Add additional features supported by QEMU */ > + t = GET_IDREG(isar, ID_ISAR5); > + t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ > + t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ > + t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ > + t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); > + t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ > + t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ > + SET_IDREG(isar, ID_ISAR5, t); > + > + t = GET_IDREG(isar, ID_ISAR6); > + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ > + t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ > + t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ > + t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ > + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ > + t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ > + t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ > + SET_IDREG(isar, ID_ISAR6, t); > + > + t = cpu->isar.mvfr1; > + t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ > + t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ > + cpu->isar.mvfr1 = t; > + > + t = cpu->isar.mvfr2; > + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ > + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ > + cpu->isar.mvfr2 = t; > + > + FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ > + > + t = GET_IDREG(isar, ID_MMFR4); > + t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ > + t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ > + t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ > + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ > + t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */ > + SET_IDREG(isar, ID_MMFR4, t); > + > + FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ > + > + t = GET_IDREG(isar, ID_PFR0); > + t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ > + t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ > + t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ > + SET_IDREG(isar, ID_PFR0, t); > + > + t = GET_IDREG(isar, ID_PFR2); > + t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ > + t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ > + SET_IDREG(isar, ID_PFR2, t); > + > + t = GET_IDREG(isar, ID_DFR0); > + t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ > + t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ > + t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ > + SET_IDREG(isar, ID_DFR0, t); > + > + /* Debug ID registers. */ > + > + /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */ > + t = 0x00008000; > + t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1); > + t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); > + t = FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */ > + t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); > + t = FIELD_DP32(t, DBGDIDR, BRPS, 5); > + t = FIELD_DP32(t, DBGDIDR, WRPS, 3); > + cpu->isar.dbgdidr = t; > + > + t = 0; > + t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3); > + t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1); > + t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15); > + t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0); > + t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1); > + t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1); > + t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0); > + t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0); > + cpu->isar.dbgdevid = t; > + > + /* Bits[31:4] are RES0. */ > + t = 0; > + t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); > + cpu->isar.dbgdevid1 = t; > + > + FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ > +} > diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c > index 73d21c6cf7d..919ed8a6cf8 100644 > --- a/target/arm/tcg/cpu32.c > +++ b/target/arm/tcg/cpu32.c > @@ -18,102 +18,6 @@ > #include "cpregs.h" > > > -/* Share AArch32 -cpu max features with AArch64. */ > -void aa32_max_features(ARMCPU *cpu) > -{ > - uint32_t t; > - ARMISARegisters *isar = &cpu->isar; > - > - /* Add additional features supported by QEMU */ > - t = GET_IDREG(isar, ID_ISAR5); > - t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ > - t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ > - t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ > - t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); > - t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ > - t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ > - SET_IDREG(isar, ID_ISAR5, t); > - > - t = GET_IDREG(isar, ID_ISAR6); > - t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ > - t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ > - t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ > - t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ > - t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ > - t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ > - t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ > - SET_IDREG(isar, ID_ISAR6, t); > - > - t = cpu->isar.mvfr1; > - t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ > - t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ > - cpu->isar.mvfr1 = t; > - > - t = cpu->isar.mvfr2; > - t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ > - t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ > - cpu->isar.mvfr2 = t; > - > - FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ > - > - t = GET_IDREG(isar, ID_MMFR4); > - t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ > - t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ > - t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ > - t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ > - t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */ > - SET_IDREG(isar, ID_MMFR4, t); > - > - FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ > - > - t = GET_IDREG(isar, ID_PFR0); > - t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ > - t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ > - t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ > - SET_IDREG(isar, ID_PFR0, t); > - > - t = GET_IDREG(isar, ID_PFR2); > - t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ > - t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ > - SET_IDREG(isar, ID_PFR2, t); > - > - t = GET_IDREG(isar, ID_DFR0); > - t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ > - t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ > - t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ > - SET_IDREG(isar, ID_DFR0, t); > - > - /* Debug ID registers. */ > - > - /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */ > - t = 0x00008000; > - t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1); > - t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); > - t = FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */ > - t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); > - t = FIELD_DP32(t, DBGDIDR, BRPS, 5); > - t = FIELD_DP32(t, DBGDIDR, WRPS, 3); > - cpu->isar.dbgdidr = t; > - > - t = 0; > - t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3); > - t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1); > - t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15); > - t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0); > - t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1); > - t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1); > - t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0); > - t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0); > - cpu->isar.dbgdevid = t; > - > - /* Bits[31:4] are RES0. */ > - t = 0; > - t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); > - cpu->isar.dbgdevid1 = t; > - > - FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ > -} > - > /* CPU models. These are not needed for the AArch64 linux-user build. */ > #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) > > diff --git a/target/arm/meson.build b/target/arm/meson.build > index 5376be2e3bc..3e02941d0d5 100644 > --- a/target/arm/meson.build > +++ b/target/arm/meson.build > @@ -9,6 +9,7 @@ arm_user_ss = ss.source_set() > arm_common_system_ss.add(files('gdbstub.c')) > arm_user_ss.add(files('gdbstub.c')) > > +arm_ss.add(files('cpu-max.c')) > arm_ss.add(when: 'TARGET_AARCH64', if_true: files( > 'cpu64.c', > )) Some bikeshedding: maybe name this cpu32-max.c for consistency? No strong opinion though, just a feeling. Reviewed-by: Pierrick Bouvier Regards, Pierrick