From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
To: Ivan Vecera <ivecera@redhat.com>, netdev@vger.kernel.org
Cc: Vincent Jardin <vjardin@free.fr>, Min Li <min.li@microchip.com>,
Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
Jiri Pirko <jiri@resnulli.us>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH net-next] dpll: zl3073x: add chip-specific minimum input reference frequency
Date: Sat, 15 Aug 2026 23:31:05 +0100 [thread overview]
Message-ID: <e1243e9c-2f8d-4e80-aa35-b6b9b5341bc7@linux.dev> (raw)
In-Reply-To: <20260814153253.900280-1-ivecera@redhat.com>
On 14/08/2026 16:32, Ivan Vecera wrote:
> Commit 24e4aff8983fe6 ("dpll: zl3073x: recognize the ZL30643 chip ID
> (0x0E3B)") added support for the ZL30643, a ZL3064x line-card variant
> that is register-compatible with ZL3073x. However, ZL3064x chips
> require a minimum input reference frequency of 1 kHz, not 1 Hz like
> other ZL3073x parts.
>
> Add a min_ref_freq field to zl3073x_chip_info and validate it in both
> the DT property parser and the ref-sync pair configuration to prevent
> configuring unsupported frequencies on ZL3064x parts.
>
> Signed-off-by: Ivan Vecera <ivecera@redhat.com>
> ---
> drivers/dpll/zl3073x/core.c | 43 +++++++++++++++++++------------------
> drivers/dpll/zl3073x/core.h | 2 ++
> drivers/dpll/zl3073x/dpll.c | 10 +++++----
> drivers/dpll/zl3073x/prop.c | 10 ++++++---
> 4 files changed, 37 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/dpll/zl3073x/core.c b/drivers/dpll/zl3073x/core.c
> index 5b2d77f2c2288e..c0b3b0d579d524 100644
> --- a/drivers/dpll/zl3073x/core.c
> +++ b/drivers/dpll/zl3073x/core.c
> @@ -20,29 +20,30 @@
> #include "dpll.h"
> #include "regs.h"
>
> -#define ZL_CHIP_INFO(_id, _nchannels, _flags) \
> - { .id = (_id), .num_channels = (_nchannels), .flags = (_flags) }
> +#define ZL_CHIP_INFO(_id, _nchannels, _flags, _min_freq) \
> + { .id = (_id), .num_channels = (_nchannels), .flags = (_flags), \
> + .min_ref_freq = (_min_freq) }
>
> static const struct zl3073x_chip_info zl3073x_chip_ids[] = {
> - ZL_CHIP_INFO(0x0E30, 2, ZL3073X_FLAG_REF_PHASE_COMP_32),
> - ZL_CHIP_INFO(0x0E3B, 3, ZL3073X_FLAG_REF_PHASE_COMP_32),
> - ZL_CHIP_INFO(0x0E93, 1, ZL3073X_FLAG_REF_PHASE_COMP_32),
> - ZL_CHIP_INFO(0x0E94, 2, ZL3073X_FLAG_REF_PHASE_COMP_32),
> - ZL_CHIP_INFO(0x0E95, 3, ZL3073X_FLAG_REF_PHASE_COMP_32),
> - ZL_CHIP_INFO(0x0E96, 4, ZL3073X_FLAG_REF_PHASE_COMP_32),
> - ZL_CHIP_INFO(0x0E97, 5, ZL3073X_FLAG_REF_PHASE_COMP_32),
> - ZL_CHIP_INFO(0x1E93, 1, ZL3073X_FLAG_DIE_TEMP),
> - ZL_CHIP_INFO(0x1E94, 2, ZL3073X_FLAG_DIE_TEMP),
> - ZL_CHIP_INFO(0x1E95, 3, ZL3073X_FLAG_DIE_TEMP),
> - ZL_CHIP_INFO(0x1E96, 4, ZL3073X_FLAG_DIE_TEMP),
> - ZL_CHIP_INFO(0x1E97, 5, ZL3073X_FLAG_DIE_TEMP),
> - ZL_CHIP_INFO(0x1F60, 2, ZL3073X_FLAG_REF_PHASE_COMP_32),
> - ZL_CHIP_INFO(0x2E93, 1, ZL3073X_FLAG_DIE_TEMP),
> - ZL_CHIP_INFO(0x2E94, 2, ZL3073X_FLAG_DIE_TEMP),
> - ZL_CHIP_INFO(0x2E95, 3, ZL3073X_FLAG_DIE_TEMP),
> - ZL_CHIP_INFO(0x2E96, 4, ZL3073X_FLAG_DIE_TEMP),
> - ZL_CHIP_INFO(0x2E97, 5, ZL3073X_FLAG_DIE_TEMP),
> - ZL_CHIP_INFO(0x3FC4, 2, ZL3073X_FLAG_DIE_TEMP),
> + ZL_CHIP_INFO(0x0E30, 2, ZL3073X_FLAG_REF_PHASE_COMP_32, 1),
> + ZL_CHIP_INFO(0x0E3B, 3, ZL3073X_FLAG_REF_PHASE_COMP_32, 1000),
> + ZL_CHIP_INFO(0x0E93, 1, ZL3073X_FLAG_REF_PHASE_COMP_32, 1),
> + ZL_CHIP_INFO(0x0E94, 2, ZL3073X_FLAG_REF_PHASE_COMP_32, 1),
> + ZL_CHIP_INFO(0x0E95, 3, ZL3073X_FLAG_REF_PHASE_COMP_32, 1),
> + ZL_CHIP_INFO(0x0E96, 4, ZL3073X_FLAG_REF_PHASE_COMP_32, 1),
> + ZL_CHIP_INFO(0x0E97, 5, ZL3073X_FLAG_REF_PHASE_COMP_32, 1),
> + ZL_CHIP_INFO(0x1E93, 1, ZL3073X_FLAG_DIE_TEMP, 1),
> + ZL_CHIP_INFO(0x1E94, 2, ZL3073X_FLAG_DIE_TEMP, 1),
> + ZL_CHIP_INFO(0x1E95, 3, ZL3073X_FLAG_DIE_TEMP, 1),
> + ZL_CHIP_INFO(0x1E96, 4, ZL3073X_FLAG_DIE_TEMP, 1),
> + ZL_CHIP_INFO(0x1E97, 5, ZL3073X_FLAG_DIE_TEMP, 1),
> + ZL_CHIP_INFO(0x1F60, 2, ZL3073X_FLAG_REF_PHASE_COMP_32, 1),
> + ZL_CHIP_INFO(0x2E93, 1, ZL3073X_FLAG_DIE_TEMP, 1),
> + ZL_CHIP_INFO(0x2E94, 2, ZL3073X_FLAG_DIE_TEMP, 1),
> + ZL_CHIP_INFO(0x2E95, 3, ZL3073X_FLAG_DIE_TEMP, 1),
> + ZL_CHIP_INFO(0x2E96, 4, ZL3073X_FLAG_DIE_TEMP, 1),
> + ZL_CHIP_INFO(0x2E97, 5, ZL3073X_FLAG_DIE_TEMP, 1),
> + ZL_CHIP_INFO(0x3FC4, 2, ZL3073X_FLAG_DIE_TEMP, 1),
> };
>
> #define ZL_RANGE_OFFSET 0x80
> diff --git a/drivers/dpll/zl3073x/core.h b/drivers/dpll/zl3073x/core.h
> index 78dc208f3eea2a..51014463377356 100644
> --- a/drivers/dpll/zl3073x/core.h
> +++ b/drivers/dpll/zl3073x/core.h
> @@ -42,11 +42,13 @@ enum zl3073x_flags {
> * @id: chip ID
> * @num_channels: number of DPLL channels supported by this variant
> * @flags: chip variant flags
> + * @min_ref_freq: minimum input reference frequency in Hz
> */
> struct zl3073x_chip_info {
> u16 id;
> u8 num_channels;
> unsigned long flags;
> + u32 min_ref_freq;
> };
>
> /**
> diff --git a/drivers/dpll/zl3073x/dpll.c b/drivers/dpll/zl3073x/dpll.c
> index 83bd3027dbaa1e..ee077c3e68da83 100644
> --- a/drivers/dpll/zl3073x/dpll.c
> +++ b/drivers/dpll/zl3073x/dpll.c
> @@ -281,7 +281,8 @@ zl3073x_dpll_input_pin_ref_sync_set(const struct dpll_pin *dpll_pin,
> sync_freq = zl3073x_ref_freq_get(sync_ref);
>
> /* Sync signal must be 8 kHz or less and clock reference
> - * must be 1 kHz or more and higher than the sync signal.
> + * must meet the chip's minimum frequency requirement and be
> + * higher than the sync signal.
> */
> if (sync_freq > 8000) {
> NL_SET_ERR_MSG(extack,
> @@ -289,9 +290,10 @@ zl3073x_dpll_input_pin_ref_sync_set(const struct dpll_pin *dpll_pin,
> rc = -EINVAL;
> goto unlock;
> }
> - if (ref_freq < 1000) {
> - NL_SET_ERR_MSG(extack,
> - "clock frequency must be 1 kHz or more");
> + if (ref_freq < zldev->info->min_ref_freq) {
> + NL_SET_ERR_MSG_FMT(extack,
> + "clock frequency must be %u Hz or more",
> + zldev->info->min_ref_freq);
> rc = -EINVAL;
> goto unlock;
> }
> diff --git a/drivers/dpll/zl3073x/prop.c b/drivers/dpll/zl3073x/prop.c
> index ac9d41d0f978ef..cdceddcf353e46 100644
> --- a/drivers/dpll/zl3073x/prop.c
> +++ b/drivers/dpll/zl3073x/prop.c
> @@ -20,9 +20,9 @@
> * @freq: frequency to check
> *
> * The function checks the given frequency is valid for the device. For input
> - * pins it checks that the frequency can be factorized using supported base
> - * frequencies. For output pins it checks that the frequency divides connected
> - * synth frequency without remainder.
> + * pins it checks that the frequency is above the chip's minimum and can be
> + * factorized using supported base frequencies. For output pins it checks that
> + * the frequency divides connected synth frequency without remainder.
> *
> * Return: true if the frequency is valid, false if not.
> */
> @@ -36,6 +36,10 @@ zl3073x_pin_check_freq(struct zl3073x_dev *zldev, enum dpll_pin_direction dir,
> if (dir == DPLL_PIN_DIRECTION_INPUT) {
> int rc;
>
> + /* Check minimum frequency */
> + if (freq < zldev->info->min_ref_freq)
> + goto err_inv_freq;
> +
> /* Check if the frequency can be factorized */
> rc = zl3073x_ref_freq_factorize(freq, NULL, NULL);
> if (rc)
>
> base-commit: 4f93b12cf7b25fbf8e73d222722805b049f0a6d3
LGTM,
Reviewed-by: Vadim Fedorenko <vadim.fedorenko@linux.dev>
next prev parent reply other threads:[~2026-08-15 22:31 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-14 15:32 [PATCH net-next] dpll: zl3073x: add chip-specific minimum input reference frequency Ivan Vecera
2026-08-15 22:31 ` Vadim Fedorenko [this message]
2026-08-16 11:04 ` Vincent Jardin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=e1243e9c-2f8d-4e80-aa35-b6b9b5341bc7@linux.dev \
--to=vadim.fedorenko@linux.dev \
--cc=arkadiusz.kubalewski@intel.com \
--cc=ivecera@redhat.com \
--cc=jiri@resnulli.us \
--cc=linux-kernel@vger.kernel.org \
--cc=min.li@microchip.com \
--cc=netdev@vger.kernel.org \
--cc=vjardin@free.fr \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.