Re: [Patch v8 19/23] perf/x86: Support SSP sampling using sample_regs_* fields

["Mi, Dapeng" <dapeng1.mi@linux.intel.com>]

On 5/29/2026 6:03 PM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] The uAPI header addition for PERF_REG_X86_SSP is not synchronized with the perf tool's copy, and the perf tool lacks support for formatting or synthesizing the new register.
> --
>
> commit b3c69baea8c8d8c919d96ea56a7caf694d17f469
> Author: Dapeng Mi <dapeng1.mi@linux.intel.com>
>
> perf/x86: Support SSP sampling using sample_regs_* fields
>
> This patch supports sampling of the CET SSP register via the sample_regs_*
> fields by using spare space reclaimed from the XMM space. It updates the
> register extraction logic and enables arch-PEBS-based SSP sampling on
> x86_64.
>
>> diff --git a/arch/x86/include/uapi/asm/perf_regs.h b/arch/x86/include/uapi/asm/perf_regs.h
>> index 8774a1290fbef..31a025cb9dbaf 100644
>> --- a/arch/x86/include/uapi/asm/perf_regs.h
>> +++ b/arch/x86/include/uapi/asm/perf_regs.h
> [ ... ]
>
>> @@ -51,10 +51,11 @@ enum perf_event_x86_regs {
>>  	PERF_REG_X86_R29,
>>  	PERF_REG_X86_R30,
>>  	PERF_REG_X86_R31,
>> +	PERF_REG_X86_SSP,
> [Severity: Medium]
> Should the corresponding UAPI header for the perf tool in
> tools/arch/x86/include/uapi/asm/perf_regs.h be updated in sync with this
> change?
>
> Also, does the perf tool require additional updates to support this new
> register? Without adding a string representation mapping for SSP, the
> tool might not be able to parse '--user-regs=ssp' or print the register
> name.

The corresponding tools support is introduced in later commit '1c10c9dfab27
("perf headers: Sync perf_event.h/perf_regs.h with the kernel headers"'.


>
> Furthermore, tools/perf/util/intel-pt.c relies on PERF_REG_X86_64_MAX
> and a hardcoded pebs_gp_regs array that does not currently include SSP.
> Will this cause the SSP register to be silently dropped from synthesized
> PT PEBS samples?

Yeah, PT support would be added independently.

Thanks.


>
>>  	/* These are the limits for the GPRs. */
>>  	PERF_REG_X86_32_MAX = PERF_REG_X86_GS + 1,
>>  	PERF_REG_X86_64_MAX = PERF_REG_X86_R15 + 1,
>> -	PERF_REG_MISC_MAX = PERF_REG_X86_R31 + 1,
>> +	PERF_REG_MISC_MAX = PERF_REG_X86_SSP + 1,
>>  
>>  	/* These all need two bits set because they are 128bit */
>>  	PERF_REG_X86_XMM0  = 32,