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Tue, 4 Feb 2025 15:57:14 +0000 Content-Type: multipart/alternative; boundary="------------QNvNAvIhwgd1hbD2IfZozzn3" Message-ID: Date: Tue, 4 Feb 2025 10:57:09 -0500 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 07/44] drm/amdgpu/vcn5.0.1: split code along instances To: Alex Deucher , amd-gfx@lists.freedesktop.org References: <20250131165741.1798488-1-alexander.deucher@amd.com> <20250131165741.1798488-8-alexander.deucher@amd.com> Content-Language: en-US From: Boyuan Zhang In-Reply-To: <20250131165741.1798488-8-alexander.deucher@amd.com> X-ClientProxiedBy: YQBPR01CA0030.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:c01::38) To CY8PR12MB7491.namprd12.prod.outlook.com (2603:10b6:930:92::15) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY8PR12MB7491:EE_|LV3PR12MB9266:EE_ X-MS-Office365-Filtering-Correlation-Id: 192a5e93-fdda-4d06-799f-08dd453497aa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|366016|1800799024|8096899003; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 2025-01-31 11:57, Alex Deucher wrote: > Split the code on a per instance basis. This will allow > us to use the per instance functions in the future to > handle more things per instance. > > Signed-off-by: Alex Deucher Reviewed-by: Boyuan Zhang > --- > drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 352 ++++++++++++------------ > 1 file changed, 174 insertions(+), 178 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c > index 8b463c977d08f..25abb303d6698 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c > @@ -568,149 +568,145 @@ static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b > * > * Start VCN block > */ > -static int vcn_v5_0_1_start(struct amdgpu_device *adev) > +static int vcn_v5_0_1_start(struct amdgpu_device *adev, int i) > { > volatile struct amdgpu_vcn4_fw_shared *fw_shared; > struct amdgpu_ring *ring; > uint32_t tmp; > - int i, j, k, r, vcn_inst; > + int j, k, r, vcn_inst; > > if (adev->pm.dpm_enabled) > amdgpu_dpm_enable_uvd(adev, true); > > - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { > - fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; > + fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; > > - if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { > - r = vcn_v5_0_1_start_dpg_mode(adev, i, adev->vcn.indirect_sram); > - continue; > - } > + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) > + return vcn_v5_0_1_start_dpg_mode(adev, i, adev->vcn.indirect_sram); > > - vcn_inst = GET_INST(VCN, i); > + vcn_inst = GET_INST(VCN, i); > > - /* set VCN status busy */ > - tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; > - WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); > - > - /* enable VCPU clock */ > - WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), > - UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); > - > - /* disable master interrupt */ > - WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, > - ~UVD_MASTINT_EN__VCPU_EN_MASK); > - > - /* enable LMI MC and UMC channels */ > - WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0, > - ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); > - > - tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); > - tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; > - tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; > - WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); > - > - /* setup regUVD_LMI_CTRL */ > - tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); > - WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, tmp | > - UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | > - UVD_LMI_CTRL__MASK_MC_URGENT_MASK | > - UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | > - UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); > - > - vcn_v5_0_1_mc_resume(adev, i); > - > - /* VCN global tiling registers */ > - WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, > - adev->gfx.config.gb_addr_config); > - > - /* unblock VCPU register access */ > - WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0, > - ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); > - > - /* release VCPU reset to boot */ > - WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, > - ~UVD_VCPU_CNTL__BLK_RST_MASK); > - > - for (j = 0; j < 10; ++j) { > - uint32_t status; > - > - for (k = 0; k < 100; ++k) { > - status = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); > - if (status & 2) > - break; > - mdelay(100); > - if (amdgpu_emu_mode == 1) > - msleep(20); > - } > + /* set VCN status busy */ > + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; > + WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); > + > + /* enable VCPU clock */ > + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), > + UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); > + > + /* disable master interrupt */ > + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, > + ~UVD_MASTINT_EN__VCPU_EN_MASK); > + > + /* enable LMI MC and UMC channels */ > + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0, > + ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); > + > + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); > + tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; > + tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; > + WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); > + > + /* setup regUVD_LMI_CTRL */ > + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); > + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, tmp | > + UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | > + UVD_LMI_CTRL__MASK_MC_URGENT_MASK | > + UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | > + UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); > + > + vcn_v5_0_1_mc_resume(adev, i); > + > + /* VCN global tiling registers */ > + WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, > + adev->gfx.config.gb_addr_config); > + > + /* unblock VCPU register access */ > + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0, > + ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); > + > + /* release VCPU reset to boot */ > + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, > + ~UVD_VCPU_CNTL__BLK_RST_MASK); > + > + for (j = 0; j < 10; ++j) { > + uint32_t status; > + > + for (k = 0; k < 100; ++k) { > + status = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); > + if (status & 2) > + break; > + mdelay(100); > + if (amdgpu_emu_mode == 1) > + msleep(20); > + } > > - if (amdgpu_emu_mode == 1) { > - r = -1; > - if (status & 2) { > - r = 0; > - break; > - } > - } else { > + if (amdgpu_emu_mode == 1) { > + r = -1; > + if (status & 2) { > r = 0; > - if (status & 2) > - break; > - > - dev_err(adev->dev, > - "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); > - WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), > - UVD_VCPU_CNTL__BLK_RST_MASK, > - ~UVD_VCPU_CNTL__BLK_RST_MASK); > - mdelay(10); > - WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, > - ~UVD_VCPU_CNTL__BLK_RST_MASK); > - > - mdelay(10); > - r = -1; > + break; > } > + } else { > + r = 0; > + if (status & 2) > + break; > + > + dev_err(adev->dev, > + "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); > + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), > + UVD_VCPU_CNTL__BLK_RST_MASK, > + ~UVD_VCPU_CNTL__BLK_RST_MASK); > + mdelay(10); > + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, > + ~UVD_VCPU_CNTL__BLK_RST_MASK); > + > + mdelay(10); > + r = -1; > } > + } > > - if (r) { > - dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); > - return r; > - } > + if (r) { > + dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); > + return r; > + } > > - /* enable master interrupt */ > - WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), > - UVD_MASTINT_EN__VCPU_EN_MASK, > - ~UVD_MASTINT_EN__VCPU_EN_MASK); > + /* enable master interrupt */ > + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), > + UVD_MASTINT_EN__VCPU_EN_MASK, > + ~UVD_MASTINT_EN__VCPU_EN_MASK); > > - /* clear the busy bit of VCN_STATUS */ > - WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, > - ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); > + /* clear the busy bit of VCN_STATUS */ > + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, > + ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); > > - ring = &adev->vcn.inst[i].ring_enc[0]; > + ring = &adev->vcn.inst[i].ring_enc[0]; > > - WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, > - ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | > - VCN_RB1_DB_CTRL__EN_MASK); > + WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, > + ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | > + VCN_RB1_DB_CTRL__EN_MASK); > > - /* Read DB_CTRL to flush the write DB_CTRL command. */ > - RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); > + /* Read DB_CTRL to flush the write DB_CTRL command. */ > + RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); > > - WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, ring->gpu_addr); > - WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); > - WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring->ring_size / 4); > + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, ring->gpu_addr); > + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); > + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring->ring_size / 4); > > - tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); > - tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); > - WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); > - fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; > - WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); > - WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); > + tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); > + tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); > + WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); > + fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; > + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); > + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); > > - tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR); > - WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp); > - ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); > + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR); > + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp); > + ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); > > - tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); > - tmp |= VCN_RB_ENABLE__RB1_EN_MASK; > - WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); > - fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); > - } > + tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); > + tmp |= VCN_RB_ENABLE__RB1_EN_MASK; > + WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); > + fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); > > return 0; > } > @@ -750,71 +746,69 @@ static void vcn_v5_0_1_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) > * > * Stop VCN block > */ > -static int vcn_v5_0_1_stop(struct amdgpu_device *adev) > +static int vcn_v5_0_1_stop(struct amdgpu_device *adev, int i) > { > volatile struct amdgpu_vcn4_fw_shared *fw_shared; > uint32_t tmp; > - int i, r = 0, vcn_inst; > + int r = 0, vcn_inst; > > - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { > - vcn_inst = GET_INST(VCN, i); > + vcn_inst = GET_INST(VCN, i); > > - fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; > - fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; > + fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; > + fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; > > - if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { > - vcn_v5_0_1_stop_dpg_mode(adev, i); > - continue; > - } > + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { > + vcn_v5_0_1_stop_dpg_mode(adev, i); > + return 0; > + } > > - /* wait for vcn idle */ > - r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); > - if (r) > - return r; > + /* wait for vcn idle */ > + r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); > + if (r) > + return r; > > - tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | > - UVD_LMI_STATUS__READ_CLEAN_MASK | > - UVD_LMI_STATUS__WRITE_CLEAN_MASK | > - UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; > - r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); > - if (r) > - return r; > + tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | > + UVD_LMI_STATUS__READ_CLEAN_MASK | > + UVD_LMI_STATUS__WRITE_CLEAN_MASK | > + UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; > + r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); > + if (r) > + return r; > > - /* disable LMI UMC channel */ > - tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2); > - tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; > - WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp); > - tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | > - UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; > - r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); > - if (r) > - return r; > + /* disable LMI UMC channel */ > + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2); > + tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; > + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp); > + tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | > + UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; > + r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); > + if (r) > + return r; > > - /* block VCPU register access */ > - WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), > - UVD_RB_ARB_CTRL__VCPU_DIS_MASK, > - ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); > - > - /* reset VCPU */ > - WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), > - UVD_VCPU_CNTL__BLK_RST_MASK, > - ~UVD_VCPU_CNTL__BLK_RST_MASK); > - > - /* disable VCPU clock */ > - WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, > - ~(UVD_VCPU_CNTL__CLK_EN_MASK)); > - > - /* apply soft reset */ > - tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); > - tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; > - WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); > - tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); > - tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; > - WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); > - > - /* clear status */ > - WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); > - } > + /* block VCPU register access */ > + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), > + UVD_RB_ARB_CTRL__VCPU_DIS_MASK, > + ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); > + > + /* reset VCPU */ > + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), > + UVD_VCPU_CNTL__BLK_RST_MASK, > + ~UVD_VCPU_CNTL__BLK_RST_MASK); > + > + /* disable VCPU clock */ > + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, > + ~(UVD_VCPU_CNTL__CLK_EN_MASK)); > + > + /* apply soft reset */ > + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); > + tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; > + WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); > + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); > + tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; > + WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); > + > + /* clear status */ > + WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); > > if (adev->pm.dpm_enabled) > amdgpu_dpm_enable_uvd(adev, false); > @@ -1010,15 +1004,17 @@ static int vcn_v5_0_1_set_powergating_state(struct amdgpu_ip_block *ip_block, > enum amd_powergating_state state) > { > struct amdgpu_device *adev = ip_block->adev; > - int ret; > + int ret = 0, i; > > if (state == adev->vcn.cur_state) > return 0; > > - if (state == AMD_PG_STATE_GATE) > - ret = vcn_v5_0_1_stop(adev); > - else > - ret = vcn_v5_0_1_start(adev); > + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { > + if (state == AMD_PG_STATE_GATE) > + ret = vcn_v5_0_1_stop(adev, i); > + else > + ret = vcn_v5_0_1_start(adev, i); > + } > > if (!ret) > adev->vcn.cur_state = state; --------------QNvNAvIhwgd1hbD2IfZozzn3 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 7bit


On 2025-01-31 11:57, Alex Deucher wrote:
Split the code on a per instance basis.  This will allow
us to use the per instance functions in the future to
handle more things per instance.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>


Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>


---
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 352 ++++++++++++------------
 1 file changed, 174 insertions(+), 178 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
index 8b463c977d08f..25abb303d6698 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
@@ -568,149 +568,145 @@ static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
  *
  * Start VCN block
  */
-static int vcn_v5_0_1_start(struct amdgpu_device *adev)
+static int vcn_v5_0_1_start(struct amdgpu_device *adev, int i)
 {
 	volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 	struct amdgpu_ring *ring;
 	uint32_t tmp;
-	int i, j, k, r, vcn_inst;
+	int j, k, r, vcn_inst;
 
 	if (adev->pm.dpm_enabled)
 		amdgpu_dpm_enable_uvd(adev, true);
 
-	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
-		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
+	fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 
-		if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
-			r = vcn_v5_0_1_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
-			continue;
-		}
+	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
+		return vcn_v5_0_1_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
 
-		vcn_inst = GET_INST(VCN, i);
+	vcn_inst = GET_INST(VCN, i);
 
-		/* set VCN status busy */
-		tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
-		WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp);
-
-		/* enable VCPU clock */
-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
-			UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
-
-		/* disable master interrupt */
-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0,
-			~UVD_MASTINT_EN__VCPU_EN_MASK);
-
-		/* enable LMI MC and UMC channels */
-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,
-			~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
-
-		tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
-		tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
-		tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
-		WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
-
-		/* setup regUVD_LMI_CTRL */
-		tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);
-		WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, tmp |
-			UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
-			UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
-			UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
-			UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
-
-		vcn_v5_0_1_mc_resume(adev, i);
-
-		/* VCN global tiling registers */
-		WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG,
-			adev->gfx.config.gb_addr_config);
-
-		/* unblock VCPU register access */
-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0,
-			~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
-
-		/* release VCPU reset to boot */
-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
-			~UVD_VCPU_CNTL__BLK_RST_MASK);
-
-		for (j = 0; j < 10; ++j) {
-			uint32_t status;
-
-			for (k = 0; k < 100; ++k) {
-				status = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);
-				if (status & 2)
-					break;
-				mdelay(100);
-				if (amdgpu_emu_mode == 1)
-					msleep(20);
-			}
+	/* set VCN status busy */
+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
+	WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp);
+
+	/* enable VCPU clock */
+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
+		 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
+
+	/* disable master interrupt */
+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0,
+		 ~UVD_MASTINT_EN__VCPU_EN_MASK);
+
+	/* enable LMI MC and UMC channels */
+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,
+		 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+
+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
+	tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+	tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+	WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
+
+	/* setup regUVD_LMI_CTRL */
+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);
+	WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, tmp |
+		     UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+		     UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
+		     UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+		     UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
+
+	vcn_v5_0_1_mc_resume(adev, i);
+
+	/* VCN global tiling registers */
+	WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG,
+		     adev->gfx.config.gb_addr_config);
+
+	/* unblock VCPU register access */
+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0,
+		 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+
+	/* release VCPU reset to boot */
+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
+		 ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+	for (j = 0; j < 10; ++j) {
+		uint32_t status;
+
+		for (k = 0; k < 100; ++k) {
+			status = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);
+			if (status & 2)
+				break;
+			mdelay(100);
+			if (amdgpu_emu_mode == 1)
+				msleep(20);
+		}
 
-			if (amdgpu_emu_mode == 1) {
-				r = -1;
-				if (status & 2) {
-					r = 0;
-					break;
-				}
-			} else {
+		if (amdgpu_emu_mode == 1) {
+			r = -1;
+			if (status & 2) {
 				r = 0;
-				if (status & 2)
-					break;
-
-				dev_err(adev->dev,
-				    "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);
-				WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
-							UVD_VCPU_CNTL__BLK_RST_MASK,
-							~UVD_VCPU_CNTL__BLK_RST_MASK);
-				mdelay(10);
-				WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
-							~UVD_VCPU_CNTL__BLK_RST_MASK);
-
-				mdelay(10);
-				r = -1;
+				break;
 			}
+		} else {
+			r = 0;
+			if (status & 2)
+				break;
+
+			dev_err(adev->dev,
+				"VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);
+			WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
+				 UVD_VCPU_CNTL__BLK_RST_MASK,
+				 ~UVD_VCPU_CNTL__BLK_RST_MASK);
+			mdelay(10);
+			WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
+				 ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+			mdelay(10);
+			r = -1;
 		}
+	}
 
-		if (r) {
-			dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
-			return r;
-		}
+	if (r) {
+		dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
+		return r;
+	}
 
-		/* enable master interrupt */
-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN),
-				UVD_MASTINT_EN__VCPU_EN_MASK,
-				~UVD_MASTINT_EN__VCPU_EN_MASK);
+	/* enable master interrupt */
+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN),
+		 UVD_MASTINT_EN__VCPU_EN_MASK,
+		 ~UVD_MASTINT_EN__VCPU_EN_MASK);
 
-		/* clear the busy bit of VCN_STATUS */
-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,
-			~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
+	/* clear the busy bit of VCN_STATUS */
+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,
+		 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 
-		ring = &adev->vcn.inst[i].ring_enc[0];
+	ring = &adev->vcn.inst[i].ring_enc[0];
 
-		WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL,
-			ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
-			VCN_RB1_DB_CTRL__EN_MASK);
+	WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL,
+		     ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
+		     VCN_RB1_DB_CTRL__EN_MASK);
 
-		/* Read DB_CTRL to flush the write DB_CTRL command. */
-		RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL);
+	/* Read DB_CTRL to flush the write DB_CTRL command. */
+	RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL);
 
-		WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, ring->gpu_addr);
-		WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
-		WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring->ring_size / 4);
+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, ring->gpu_addr);
+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring->ring_size / 4);
 
-		tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
-		tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
-		WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
-		fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
-		WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);
-		WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);
+	tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
+	tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
+	WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
+	fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);
+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);
 
-		tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR);
-		WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp);
-		ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR);
+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp);
+	ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
 
-		tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
-		tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
-		WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
-		fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
-	}
+	tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
+	tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
+	WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
+	fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
 
 	return 0;
 }
@@ -750,71 +746,69 @@ static void vcn_v5_0_1_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
  *
  * Stop VCN block
  */
-static int vcn_v5_0_1_stop(struct amdgpu_device *adev)
+static int vcn_v5_0_1_stop(struct amdgpu_device *adev, int i)
 {
 	volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 	uint32_t tmp;
-	int i, r = 0, vcn_inst;
+	int r = 0, vcn_inst;
 
-	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
-		vcn_inst = GET_INST(VCN, i);
+	vcn_inst = GET_INST(VCN, i);
 
-		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
-		fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
+	fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
+	fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
 
-		if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
-			vcn_v5_0_1_stop_dpg_mode(adev, i);
-			continue;
-		}
+	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+		vcn_v5_0_1_stop_dpg_mode(adev, i);
+		return 0;
+	}
 
-		/* wait for vcn idle */
-		r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
-		if (r)
-			return r;
+	/* wait for vcn idle */
+	r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
+	if (r)
+		return r;
 
-		tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
-		      UVD_LMI_STATUS__READ_CLEAN_MASK |
-		      UVD_LMI_STATUS__WRITE_CLEAN_MASK |
-		      UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
-		r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp);
-		if (r)
-			return r;
+	tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
+		UVD_LMI_STATUS__READ_CLEAN_MASK |
+		UVD_LMI_STATUS__WRITE_CLEAN_MASK |
+		UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
+	r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp);
+	if (r)
+		return r;
 
-		/* disable LMI UMC channel */
-		tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);
-		tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
-		WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp);
-		tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
-		      UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
-		r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp);
-		if (r)
-			return r;
+	/* disable LMI UMC channel */
+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);
+	tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
+	WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp);
+	tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
+		UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
+	r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp);
+	if (r)
+		return r;
 
-		/* block VCPU register access */
-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL),
-			UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
-			~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
-
-		/* reset VCPU */
-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
-			UVD_VCPU_CNTL__BLK_RST_MASK,
-			~UVD_VCPU_CNTL__BLK_RST_MASK);
-
-		/* disable VCPU clock */
-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
-			~(UVD_VCPU_CNTL__CLK_EN_MASK));
-
-		/* apply soft reset */
-		tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
-		tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
-		WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
-		tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
-		tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
-		WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
-
-		/* clear status */
-		WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0);
-	}
+	/* block VCPU register access */
+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL),
+		 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
+		 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+
+	/* reset VCPU */
+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
+		 UVD_VCPU_CNTL__BLK_RST_MASK,
+		 ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+	/* disable VCPU clock */
+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
+		 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
+
+	/* apply soft reset */
+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
+	tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+	WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
+	tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+	WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
+
+	/* clear status */
+	WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0);
 
 	if (adev->pm.dpm_enabled)
 		amdgpu_dpm_enable_uvd(adev, false);
@@ -1010,15 +1004,17 @@ static int vcn_v5_0_1_set_powergating_state(struct amdgpu_ip_block *ip_block,
 					    enum amd_powergating_state state)
 {
 	struct amdgpu_device *adev = ip_block->adev;
-	int ret;
+	int ret = 0, i;
 
 	if (state == adev->vcn.cur_state)
 		return 0;
 
-	if (state == AMD_PG_STATE_GATE)
-		ret = vcn_v5_0_1_stop(adev);
-	else
-		ret = vcn_v5_0_1_start(adev);
+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+		if (state == AMD_PG_STATE_GATE)
+			ret = vcn_v5_0_1_stop(adev, i);
+		else
+			ret = vcn_v5_0_1_start(adev, i);
+	}
 
 	if (!ret)
 		adev->vcn.cur_state = state;
--------------QNvNAvIhwgd1hbD2IfZozzn3--