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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4395a06b1ddsm17519645e9.22.2025.02.12.03.44.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Feb 2025 03:44:24 -0800 (PST) Message-ID: Date: Wed, 12 Feb 2025 12:44:23 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 02/11] hw/intc/xilinx_intc: Make device endianness configurable To: Thomas Huth , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, "Edgar E. Iglesias" , Alistair Francis , Richard Henderson , Markus Armbruster , qemu-arm@nongnu.org, =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= References: <20250212112413.37553-1-philmd@linaro.org> <20250212112413.37553-3-philmd@linaro.org> <125a3dac-8ef9-4748-a3ce-f8fb97d8cb59@redhat.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <125a3dac-8ef9-4748-a3ce-f8fb97d8cb59@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 12/2/25 12:42, Thomas Huth wrote: > On 12/02/2025 12.24, Philippe Mathieu-Daudé wrote: >> Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair >> of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. >> Add the "little-endian" property to select the device >> endianness, defaulting to little endian. >> Set the proper endianness for each machine using the device. >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >>   hw/intc/xilinx_intc.c                    | 60 ++++++++++++++++++------ >>   hw/microblaze/petalogix_ml605_mmu.c      |  1 + >>   hw/microblaze/petalogix_s3adsp1800_mmu.c |  3 ++ >>   hw/ppc/virtex_ml507.c                    |  1 + >>   hw/riscv/microblaze-v-generic.c          |  1 + >>   5 files changed, 52 insertions(+), 14 deletions(-) >> >> diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c >> index 6930f83907a..523402b688c 100644 >> --- a/hw/intc/xilinx_intc.c >> +++ b/hw/intc/xilinx_intc.c >> @@ -3,6 +3,9 @@ >>    * >>    * Copyright (c) 2009 Edgar E. Iglesias. >>    * >> + * https://docs.amd.com/v/u/en-US/xps_intc >> + * DS572: LogiCORE IP XPS Interrupt Controller (v2.01a) >> + * >>    * Permission is hereby granted, free of charge, to any person >> obtaining a copy >>    * of this software and associated documentation files (the >> "Software"), to deal >>    * in the Software without restriction, including without limitation >> the rights >> @@ -23,10 +26,12 @@ >>    */ >>   #include "qemu/osdep.h" >> +#include "qapi/error.h" >>   #include "hw/sysbus.h" >>   #include "qemu/module.h" >>   #include "hw/irq.h" >>   #include "hw/qdev-properties.h" >> +#include "hw/qdev-properties-system.h" >>   #include "qom/object.h" >>   #define D(x) >> @@ -49,6 +54,7 @@ struct XpsIntc >>   { >>       SysBusDevice parent_obj; >> +    EndianMode model_endianness; >>       MemoryRegion mmio; >>       qemu_irq parent_irq; >> @@ -140,18 +146,29 @@ static void pic_write(void *opaque, hwaddr addr, >>       update_irq(p); >>   } >> -static const MemoryRegionOps pic_ops = { >> -    .read = pic_read, >> -    .write = pic_write, >> -    .endianness = DEVICE_NATIVE_ENDIAN, >> -    .impl = { >> -        .min_access_size = 4, >> -        .max_access_size = 4, >> +static const MemoryRegionOps pic_ops[2] = { >> +    [0 ... 1] = { > > Hmm, ok, so here we have now an assumption that ENDIAN_MODE_BIG and > ENDIAN_MODE_LITTLE match 0 and 1, which would not work anymore when > using 0 as unspecified... a little bit ugly ... so maybe instead of > changing pic_ops into an array .... > >> +        .read = pic_read, >> +        .write = pic_write, >> +        .endianness = DEVICE_BIG_ENDIAN, >> +        .impl = { >> +            .min_access_size = 4, >> +            .max_access_size = 4, >> +        }, >> +        .valid = { >> +            /* >> +             * All XPS INTC registers are accessed through the PLB >> interface. >> +             * The base address for these registers is provided by the >> +             * configuration parameter, C_BASEADDR. Each register is >> 32 bits >> +             * although some bits may be unused and is accessed on a >> 4-byte >> +             * boundary offset from the base address. >> +             */ >> +            .min_access_size = 4, >> +            .max_access_size = 4, >> +        }, >>       }, >> -    .valid = { >> -        .min_access_size = 4, >> -        .max_access_size = 4 >> -    } >> +    [ENDIAN_MODE_BIG].endianness = DEVICE_BIG_ENDIAN, >> +    [ENDIAN_MODE_LITTLE].endianness = DEVICE_LITTLE_ENDIAN, >>   }; >>   static void irq_handler(void *opaque, int irq, int level) >> @@ -174,13 +191,27 @@ static void xilinx_intc_init(Object *obj) >>       qdev_init_gpio_in(DEVICE(obj), irq_handler, 32); >>       sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq); >> - >> -    memory_region_init_io(&p->mmio, obj, &pic_ops, p, "xlnx.xps-intc", >> -                          R_MAX * 4); >>       sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio); >>   } >> +static void xilinx_intc_realize(DeviceState *dev, Error **errp) >> +{ >> +    XpsIntc *p = XILINX_INTC(dev); >> + >> +    if (p->model_endianness == ENDIAN_MODE_UNSPECIFIED) { >> +        error_setg(errp, TYPE_XILINX_INTC " property 'endianness'" >> +                         " must be set to 'big' or 'little'"); >> +        return; >> +    } > > ... would it be possible to patch in the right value for pic_ops.endianness > here instead? Ah, clever than my reply on the previous patch. I'll give it a try, thanks! > >  Thomas