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Fri, 4 Sep 2026 12:43:57 +0000 Message-ID: Date: Fri, 4 Sep 2026 14:43:46 +0200 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] spi: xilinx_spi: fix premature transfer termination at low SCK To: Suraj Kakade , u-boot@lists.u-boot-project.org Cc: git@amd.com, padmarao.begari@amd.com, Tom Rini , Jagan Teki , Siva Durga Prasad Paladugu References: <20260813120718.1707573-1-suraj.hanumantkakade@amd.com> Content-Language: en-US From: Michal Simek Autocrypt: addr=michal.simek@amd.com; keydata= xsFNBFFuvDEBEAC9Amu3nk79+J+4xBOuM5XmDmljuukOc6mKB5bBYOa4SrWJZTjeGRf52VMc howHe8Y9nSbG92obZMqsdt+d/hmRu3fgwRYiiU97YJjUkCN5paHXyBb+3IdrLNGt8I7C9RMy svSoH4WcApYNqvB3rcMtJIna+HUhx8xOk+XCfyKJDnrSuKgx0Svj446qgM5fe7RyFOlGX/wF Ae63Hs0RkFo3I/+hLLJP6kwPnOEo3lkvzm3FMMy0D9VxT9e6Y3afe1UTQuhkg8PbABxhowzj SEnl0ICoqpBqqROV/w1fOlPrm4WSNlZJunYV4gTEustZf8j9FWncn3QzRhnQOSuzTPFbsbH5 WVxwDvgHLRTmBuMw1sqvCc7CofjsD1XM9bP3HOBwCxKaTyOxbPJh3D4AdD1u+cF/lj9Fj255 Es9aATHPvoDQmOzyyRNTQzupN8UtZ+/tB4mhgxWzorpbdItaSXWgdDPDtssJIC+d5+hskys8 B3jbv86lyM+4jh2URpnL1gqOPwnaf1zm/7sqoN3r64cml94q68jfY4lNTwjA/SnaS1DE9XXa XQlkhHgjSLyRjjsMsz+2A4otRLrBbumEUtSMlPfhTi8xUsj9ZfPIUz3fji8vmxZG/Da6jx/c a0UQdFFCL4Ay/EMSoGbQouzhC69OQLWNH3rMQbBvrRbiMJbEZwARAQABzSlNaWNoYWwgU2lt ZWsgKEFNRCkgPG1pY2hhbC5zaW1la0BhbWQuY29tPsLBlAQTAQgAPgIbAwULCQgHAgYVCgkI CwIEFgIDAQIeAQIXgBYhBGc1DJv1zO6bU2Q1ajd8fyH+PR+RBQJn8lwDBQkaRgbLAAoJEDd8 fyH+PR+RCNAP/iHkKbpP0XXfgfWqf8yyrFHjGPJSknERzxw0glxPztfC3UqeusQ0CPnbI85n uQdm5/zRgWr7wi8H2UMqFlfMW8/NH5Da7GOPc26NMTPA2ZG5S2SG2SGZj1Smq8mL4iueePiN x1qfWhVm7TfkDHUEmMAYq70sjFcvygyqHUCumpw36CMQSMyrxyEkbYm1NKORlnySAFHy2pOx nmXKSaL1yfof3JJLwNwtaBj76GKQILnlYx9QNnt6adCtrZLIhB3HGh4IRJyuiiM0aZi1G8ei 2ILx2n2LxUw7X6aAD0sYHtNKUCQMCBGQHzJLDYjEyy0kfYoLXV2P6K+7WYnRP+uV8g77Gl9a IuGvxgEUITjMakX3e8RjyZ5jmc5ZAsegfJ669oZJOzQouw/W9Qneb820rhA2CKK8BnmlkHP+ WB5yDks3gSHE/GlOWqRkVZ05sUjVmq/tZ1JEdOapWQovRQsueDjxXcMjgNo5e8ttCyMo44u1 pKXRJpR5l7/hBYWeMlcKvLwByep+FOGtKsv0xadMKr1M6wPZXkV83jMKxxRE9HlqWJLLUE1Q 0pDvn1EvlpDj9eED73iMBsrHu9cIk8aweTEbQ4bcKRGfGkXrCwle6xRiKSjXCdzWpOglNhjq 1g8Ak+G+ZR6r7QarL01BkdE2/WUOLHdGHB1hJxARbP2E3l46zsFNBFFuvDEBEACXqiX5h4IA 03fJOwh+82aQWeHVAEDpjDzK5hSSJZDE55KP8br1FZrgrjvQ9Ma7thSu1mbr+ydeIqoO1/iM fZA+DDPpvo6kscjep11bNhVa0JpHhwnMfHNTSHDMq9OXL9ZZpku/+OXtapISzIH336p4ZUUB 5asad8Ux70g4gmI92eLWBzFFdlyR4g1Vis511Nn481lsDO9LZhKyWelbif7FKKv4p3FRPSbB vEgh71V3NDCPlJJoiHiYaS8IN3uasV/S1+cxVbwz2WcUEZCpeHcY2qsQAEqp4GM7PF2G6gtz IOBUMk7fjku1mzlx4zP7uj87LGJTOAxQUJ1HHlx3Li+xu2oF9Vv101/fsCmptAAUMo7KiJgP Lu8TsP1migoOoSbGUMR0jQpUcKF2L2jaNVS6updvNjbRmFojK2y6A/Bc6WAKhtdv8/e0/Zby iVA7/EN5phZ1GugMJxOLHJ1eqw7DQ5CHcSQ5bOx0Yjmhg4PT6pbW3mB1w+ClAnxhAbyMsfBn XxvvcjWIPnBVlB2Z0YH/gizMDdM0Sa/HIz+q7JR7XkGL4MYeAM15m6O7hkCJcoFV7LMzkNKk OiCZ3E0JYDsMXvmh3S4EVWAG+buA+9beElCmXDcXPI4PinMPqpwmLNcEhPVMQfvAYRqQp2fg 1vTEyK58Ms+0a9L1k5MvvbFg9QARAQABwsF8BBgBCAAmAhsMFiEEZzUMm/XM7ptTZDVqN3x/ If49H5EFAmfyXCkFCRpGBvgACgkQN3x/If49H5GY5xAAoKWHRO/OlI7eMA8VaUgFInmphBAj fAgQbW6Zxl9ULaCcNSoJc2D0zYWXftDOJeXyVk5Gb8cMbLA1tIMSM/BgSAnT7As2KfcZDTXQ DJSZYWgYKc/YywLgUlpv4slFv5tjmoUvHK9w2DuFLW254pnUuhrdyTEaknEM+qOmPscWOs0R dR6mMTN0vBjnLUeYdy0xbaoefjT+tWBybXkVwLDd3d/+mOa9ZiAB7ynuVWu2ow/uGJx0hnRI LGfLsiPu47YQrQXu79r7RtVeAYwRh3ul7wx5LABWI6n31oEHxDH+1czVjKsiozRstEaUxuDZ jWRHq+AEIq79BTTopj2dnW+sZAsnVpQmc+nod6xR907pzt/HZL0WoWwRVkbg7hqtzKOBoju3 hftqVr0nx77oBZD6mSJsxM/QuJoaXaTX/a/QiB4Nwrja2jlM0lMUA/bGeM1tQwS7rJLaT3cT RBGSlJgyWtR8IQvX3rqHd6QrFi1poQ1/wpLummWO0adWes2U6I3GtD9vxO/cazWrWBDoQ8Da otYa9+7v0j0WOBTJaj16LFxdSRq/jZ1y/EIHs3Ysd85mUWXOB8xZ6h+WEMzqAvOt02oWJVbr ZLqxG/3ScDXZEUJ6EDJVoLAK50zMk87ece2+4GWGOKfFsiDfh7fnEMXQcykxuowBYUD0tMd2 mpwx1d8= In-Reply-To: <20260813120718.1707573-1-suraj.hanumantkakade@amd.com> Content-Type: text/plain; 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SPISR_TX_EMPTY only indicates that the TX FIFO has drained; > the final byte may still be in the shift pipeline and actively > transmitting on the SPI bus. At low SCK frequencies the gap between > FIFO-empty and the last bit finishing its shift-out becomes wide > enough that MASTER_INHIBIT gets asserted before the transfer actually > completes, truncating the last byte and leaving the clock generation > logic in an error state. > > Switch to polling IPISR_DTR_EMPTY instead, which is only set once the > last byte has genuinely finished shifting out to the slave, and only > assert MASTER_INHIBIT afterwards. Clear any stale DTR_EMPTY before > starting a transfer and after detecting completion, since IPISR is > toggle-on-write. This fix works correctly at both high and low SCK > frequencies. > > Fixes: 0c0de58f7b30 ("spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() function") > Signed-off-by: Padmarao Begari > Signed-off-by: Suraj Kakade > --- > drivers/spi/xilinx_spi.c | 21 ++++++++++++++++++++- > 1 file changed, 20 insertions(+), 1 deletion(-) > > diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c > index b2af17ebae9..011bbc93076 100644 > --- a/drivers/spi/xilinx_spi.c > +++ b/drivers/spi/xilinx_spi.c > @@ -53,6 +53,8 @@ > #define SPISR_RX_FULL BIT(1) > #define SPISR_RX_EMPTY BIT(0) > > +#define IPISR_DTR_EMPTY BIT(2) > + > /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */ > #define SPIDTR_8BIT_MASK GENMASK(7, 0) > #define SPIDTR_16BIT_MASK GENMASK(15, 0) > @@ -256,6 +258,13 @@ static int start_transfer(struct udevice *dev, const void *dout, void *din, u32 > reg = readl(®s->spicr) | SPICR_MASTER_INHIBIT; > writel(reg, ®s->spicr); > count = xilinx_spi_fill_txfifo(bus, txp, txbytes); > + /* > + * Clear any stale DTR_EMPTY before starting. IPISR is > + * toggle-on-write, so only write (toggle) the bit when it is > + * actually set, otherwise the write would spuriously set it. > + */ > + if (readl(®s->ipisr) & IPISR_DTR_EMPTY) > + writel(IPISR_DTR_EMPTY, ®s->ipisr); > /* Enable master transaction */ > reg = readl(®s->spicr) & ~SPICR_MASTER_INHIBIT; > writel(reg, ®s->spicr); > @@ -263,12 +272,22 @@ static int start_transfer(struct udevice *dev, const void *dout, void *din, u32 > if (txp) > txp += count; > > - ret = wait_for_bit_le32(®s->spisr, SPISR_TX_EMPTY, true, > + /* > + * Wait for the transfer to fully complete before inhibiting > + * the master. The final byte may still be in the shift > + * pipeline. Poll IPISR_DTR_EMPTY, which is set only once the > + * last byte has been shifted out to the slave. Asserting > + * MASTER_INHIBIT before this stops SCK and truncates the last > + * byte, which is observable at low SCK frequencies. > + */ > + ret = wait_for_bit_le32(®s->ipisr, IPISR_DTR_EMPTY, true, > XILINX_SPISR_TIMEOUT, false); > if (ret < 0) { > printf("XILSPI error: Xfer timeout\n"); > return ret; > } > + /* IPISR is toggle-on-write; write 1 to clear DTR_EMPTY */ > + writel(IPISR_DTR_EMPTY, ®s->ipisr); > > reg = readl(®s->spicr) | SPICR_MASTER_INHIBIT; > writel(reg, ®s->spicr); Applied. M