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([2a01:e0a:c:37e0:ced3:55bd:f454:e722]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-437c753bee8sm195408755e9.34.2025.01.20.02.35.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Jan 2025 02:35:35 -0800 (PST) Message-ID: Date: Mon, 20 Jan 2025 11:35:34 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/8] drm/ast: Refactor ast_post_gpu() by Gen To: Thomas Zimmermann , airlied@redhat.com Cc: dri-devel@lists.freedesktop.org References: <20250117103450.28692-1-tzimmermann@suse.de> <20250117103450.28692-4-tzimmermann@suse.de> From: Jocelyn Falempe In-Reply-To: <20250117103450.28692-4-tzimmermann@suse.de> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: 4f5n6n_iVSxcna-cL2btyJP0lhy9Md7oRgWK9NRZEnU_1737369336 X-Mimecast-Originator: redhat.com Content-Language: en-US, fr Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 17/01/2025 11:29, Thomas Zimmermann wrote: > Reorganize ast_post_gpu() so that it first branches by Gen and then > by config mode and TX chip. This will later make it possible to split > up the function by Gen. > > The helper ast_init_3rdtx() only handles Gen4 and Gen5, so leave it > out from the other Gens. Thanks, it looks good to me. Reviewed-by: Jocelyn Falempe > > Signed-off-by: Thomas Zimmermann > --- > drivers/gpu/drm/ast/ast_post.c | 36 ++++++++++++++++++++++++---------- > 1 file changed, 26 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c > index 364030f97571d..49f661760f9e5 100644 > --- a/drivers/gpu/drm/ast/ast_post.c > +++ b/drivers/gpu/drm/ast/ast_post.c > @@ -344,21 +344,37 @@ void ast_post_gpu(struct ast_device *ast) > { > ast_set_def_ext_reg(ast); > > - if (IS_AST_GEN7(ast)) { > + if (AST_GEN(ast) >= 7) { > if (ast->tx_chip == AST_TX_ASTDP) > ast_dp_launch(ast); > - } else if (ast->config_mode == ast_use_p2a) { > - if (IS_AST_GEN6(ast)) > + } else if (AST_GEN(ast) >= 6) { > + if (ast->config_mode == ast_use_p2a) { > ast_post_chip_2500(ast); > - else if (IS_AST_GEN5(ast) || IS_AST_GEN4(ast)) > + } else { > + if (ast->tx_chip == AST_TX_SIL164) { > + /* Enable DVO */ > + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80); > + } > + } > + } else if (AST_GEN(ast) >= 4) { > + if (ast->config_mode == ast_use_p2a) { > ast_post_chip_2300(ast); > - else > + ast_init_3rdtx(ast); > + } else { > + if (ast->tx_chip == AST_TX_SIL164) { > + /* Enable DVO */ > + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80); > + } > + } > + } else { > + if (ast->config_mode == ast_use_p2a) { > ast_init_dram_reg(ast); > - > - ast_init_3rdtx(ast); > - } else { > - if (ast->tx_chip == AST_TX_SIL164) > - ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80); /* Enable DVO */ > + } else { > + if (ast->tx_chip == AST_TX_SIL164) { > + /* Enable DVO */ > + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80); > + } > + } > } > } >