From: Chris Wilson <chris@chris-wilson.co.uk>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: fix swizzling on gen6+
Date: Mon, 12 Sep 2011 22:27:10 +0100 [thread overview]
Message-ID: <e39f63$1hp48p@fmsmga002.fm.intel.com> (raw)
In-Reply-To: <20110912203714.GC2830@phenom.ffwll.local>
On Mon, 12 Sep 2011 22:37:14 +0200, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Mon, Sep 12, 2011 at 09:13:39PM +0100, Chris Wilson wrote:
> > On Mon, 12 Sep 2011 20:49:16 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> > > Fixes tests/gem_tiled_pread on my snb. I know, mesa doesn't use this
> > > on gen6+, but I also hate failing testcases.
> >
> > Hmm, I thought gen6 also has DRAM configuration registers that we were
> > meant to set and to follow. Not that I could actually find the
> > cross-references! I've been surprised that it works and scared
> > to poke too hard just in case it was broken underneath. ;-)
>
> Well, I've checked with my ilk and snb, and now it works for both. ymmv.
> The other options is to return SWIZZLE_UNKOWN back to userspace and
> disable the tests on gen5+. I don't care too much either way, but I think
> making it work is less risky. And now that qa actually runs our tests, we
> might even catch this earlier.
I suspect we are missing some code to handle atypical configurations.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2011-09-12 21:27 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-12 18:49 [PATCH] drm/i915: fix swizzling on gen6+ Daniel Vetter
2011-09-12 20:02 ` Ben Widawsky
2011-09-12 20:13 ` Chris Wilson
2011-09-12 20:37 ` Daniel Vetter
2011-09-12 21:27 ` Chris Wilson [this message]
2011-09-23 16:11 ` Daniel Vetter
-- strict thread matches above, loose matches on Subject: below --
2012-03-02 20:33 Daniel Vetter
2012-03-02 20:40 ` Daniel Vetter
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