From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+. Date: Thu, 06 Oct 2011 00:36:03 +0100 Message-ID: References: <1317708160-1761-1-git-send-email-kenneth@whitecape.org> <1317708160-1761-3-git-send-email-kenneth@whitecape.org> <20111005155713.6e2f0c6c@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id C62879E812 for ; Wed, 5 Oct 2011 16:36:07 -0700 (PDT) In-Reply-To: <20111005155713.6e2f0c6c@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ben Widawsky , Kenneth Graunke Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, 5 Oct 2011 15:57:13 -0700, Ben Widawsky wrote: > I think we also want a TLB invalidate here, bit 18. This requires another > workaround before issuing this flush: We need 2 Store Data Commands (such as > MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX) before sending PIPE_CONTROL w/ stall > (20) and TLB inv bit (18) set Isn't that workaround itself rather hand-wavy? As in it gives the hardware sufficient time to complete outstanding writes, but not necessarily. Or am I thinking of yet another workaround... -Chris -- Chris Wilson, Intel Open Source Technology Centre