From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 3/5] drm/i915: implement SNB workaround for lazy global gtt Date: Wed, 15 Feb 2012 23:10:08 +0000 Message-ID: References: <1329346225-14795-1-git-send-email-daniel.vetter@ffwll.ch> <1329346225-14795-4-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 500F29EB93 for ; Wed, 15 Feb 2012 15:10:12 -0800 (PST) In-Reply-To: <1329346225-14795-4-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org On Wed, 15 Feb 2012 23:50:23 +0100, Daniel Vetter wrote: > + /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and > + * pipe_control writes because the gpu doesn't properly redirect them > + * through the ppgtt for non_secure batchbuffers. */ > + if (unlikely(IS_GEN6(dev) && > + reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && > + !target_i915_obj->has_global_gtt_mapping)) { > + i915_gem_gtt_bind_object(target_i915_obj, > + target_i915_obj->cache_level); > + target_i915_obj->has_global_gtt_mapping = 1; i915_gem_gtt_bind_object() sets has_global_gtt_mapping, so no need to repeat ourselves here. I guess that was the easy one you throw in to make sure people are reading your patches? A little uneasy still with that heuristic, but I have to agree that it is the lesser of the evils, meh. I'm pretty happy now with this series as I've been beating upon it ever since it landed in danvet/my-next, so Reviewed-and-tested-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre