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From: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
To: Imre Deak <imre.deak@intel.com>, <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 2/6] drm/i915/adlp: Add MST short HBlank WA (Wa_14014143976)
Date: Wed, 31 Jan 2024 10:45:13 +0530	[thread overview]
Message-ID: <e3a3dd15-9e98-4916-9ffd-97ff1bd8e2ee@intel.com> (raw)
In-Reply-To: <20240129175533.904590-3-imre.deak@intel.com>


On 1/29/2024 11:25 PM, Imre Deak wrote:
> Add a workaround to fix BS jitter issues on MST links if the HBLANK
> period is less than 1 MTP. The WA applies only to UHBR rates while on
> non-UHBR the specification requires disabling it explicitly - presumedly
> because the register's reset value has the WA enabled.
>
> Bspec: 50050, 55424
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
LGTM.


Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++
>   drivers/gpu/drm/i915/i915_reg.h             | 1 +
>   2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 22c1759f912db..23f3f7fab9d0b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -1122,6 +1122,14 @@ static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state)
>   	if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
>   		set |= DP_MST_FEC_BS_JITTER_WA(crtc_state->cpu_transcoder);
>   
> +	/* Wa_14014143976:adlp */
> +	if (IS_DISPLAY_STEP(i915, STEP_E0, STEP_FOREVER)) {
> +		if (intel_dp_is_uhbr(crtc_state))
> +			set |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
> +		else if (crtc_state->fec_enable)
> +			clear |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
> +	}
> +
>   	if (!clear && !set)
>   		return;
>   
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 67b7d02ea37bf..091edc1071e0e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4556,6 +4556,7 @@
>   #define   GLK_CL0_PWR_DOWN		REG_BIT(10)
>   
>   #define CHICKEN_MISC_3		_MMIO(0x42088)
> +#define   DP_MST_SHORT_HBLANK_WA(trans)		REG_BIT(5 + (trans) - TRANSCODER_A)
>   #define   DP_MST_FEC_BS_JITTER_WA(trans)	REG_BIT(0 + (trans) - TRANSCODER_A)
>   
>   #define CHICKEN_MISC_4		_MMIO(0x4208c)

  reply	other threads:[~2024-01-31  5:15 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-29 17:55 [PATCH 0/6] drm/i915/dp: Add jitter WAs for MST/FEC/DSC links Imre Deak
2024-01-29 17:55 ` [PATCH 1/6] drm/i915/adlp: Add MST FEC BS jitter WA (Wa_14013163432) Imre Deak
2024-01-30 13:48   ` Nautiyal, Ankit K
2024-01-30 14:05     ` Imre Deak
2024-01-31  5:05       ` Nautiyal, Ankit K
2024-01-29 17:55 ` [PATCH 2/6] drm/i915/adlp: Add MST short HBlank WA (Wa_14014143976) Imre Deak
2024-01-31  5:15   ` Nautiyal, Ankit K [this message]
2024-01-29 17:55 ` [PATCH 3/6] drm/i915/adlp: Add DP MST DPT/DPTP alignment " Imre Deak
2024-01-31  5:27   ` Nautiyal, Ankit K
2024-01-29 17:55 ` [PATCH 4/6] drm/i915/adlp+: Add DSC early pixel count scaling WA (Wa_1409098942) Imre Deak
2024-01-31  5:41   ` Nautiyal, Ankit K
2024-01-29 17:55 ` [PATCH 5/6] drm/i915/mtl+: Disable DP/DSC SF insertion at EOL WA Imre Deak
2024-01-31  5:58   ` Nautiyal, Ankit K
2024-01-29 17:55 ` [PATCH 6/6] drm/i915/mtl: Add DP FEC BS jitter WA Imre Deak
2024-01-31  6:04   ` Nautiyal, Ankit K
2024-01-29 18:42 ` ✓ Fi.CI.BAT: success for drm/i915/dp: Add jitter WAs for MST/FEC/DSC links Patchwork
2024-04-10 16:30   ` Imre Deak

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