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Mon, 09 Nov 2026 09:30:13 -0800 (PST) Received: from [127.0.0.1] ([85.204.204.133]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-49835858f58sm155598f8f.13.2026.11.09.09.30.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Nov 2026 09:30:13 -0800 (PST) From: Ana Bobillo To: u-boot@lists.u-boot-project.org Cc: Tom Rini , Anatolij Gustschin , Simon Glass , Kever Yang , Quentin Schulz , Andre Przywara , Thierry Reding , Svyatoslav Ryhel , Tom Warren , Patrick Delaunay , Patrice Chotard , uboot-stm32@st-md-mailman.stormreply.com, Neil Armstrong , =?UTF-8?Q?Jonas_Schw=C3=B6bel?= Subject: [PATCH 11/11] video: tegra124: dp: Limit the lane count to four Date: Mon, 09 Nov 2026 17:30:12 +0000 Message-ID: In-Reply-To: <2399d63c-ddd0-44b0-bb81-d5d9d2a8a8b4@gmail.com> References: <2399d63c-ddd0-44b0-bb81-d5d9d2a8a8b4@gmail.com> X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Archive: List-Post: List-Help: List-Subscribe: , X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 X-Archived-By: From: Ana Bobillo tegra_dc_dp_init_max_link_cfg() takes the lane count from the sink's MAX_LANE_COUNT DPCD register, masked to 5 bits, and link training uses it to fill the four-entry pe[], vs[] and pc[] arrays on the stack. A sink reporting more than four lanes makes tegra_dp_lt_adjust() write past them. Limit the lane count to the four lanes the SOR has. Fixes: 59dd5aa8fa51 ("tegra: video: Add Embedded DisplayPort driver") Signed-off-by: Ana Bobillo --- drivers/video/tegra/tegra124/dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/video/tegra/tegra124/dp.c b/drivers/video/tegra/tegra124/dp.c index 611bf2f81a6..22e9a4b15f7 100644 --- a/drivers/video/tegra/tegra124/dp.c +++ b/drivers/video/tegra/tegra124/dp.c @@ -664,6 +664,9 @@ static int tegra_dc_dp_init_max_link_cfg( if (ret) return ret; link_cfg->max_lane_count = dpcd_data & DP_MAX_LANE_COUNT_MASK; + /* The sink may report more lanes than the SOR has */ + if (link_cfg->max_lane_count > DP_MAX_LANE_COUNT_LANE_4) + link_cfg->max_lane_count = DP_MAX_LANE_COUNT_LANE_4; link_cfg->tps3_supported = (dpcd_data & DP_MAX_LANE_COUNT_TPS3_SUPPORTED_YES) ? 1 : 0;