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From: Julien Grall <julien.grall@arm.com>
To: Manish Jaggi <manish.jaggi@cavium.com>,
	xen-devel@lists.xenproject.org, sstabellini@kernel.org,
	marc.zyngier@arm.com, andre.przywara@arm.com
Subject: Re: [PATCH v1 01/15] arm64: cputype: Add MIDR values for Cavium ThunderX1 CPU family
Date: Tue, 20 Mar 2018 07:38:49 +0000	[thread overview]
Message-ID: <e4cf4764-5e84-01cd-e1de-5d4a31d2b8a0@arm.com> (raw)
In-Reply-To: <9089246786c2c1200b0da113436eae250fcba8ee.1521200294.git.manish.jaggi@cavium.com>

Hi Manish,

On 03/16/2018 11:58 AM, Manish Jaggi wrote:
> Add MIDR values for Cavium ThunderX1 SoC family.

Did you intend to use a : instead of .?

> ThunderX1, 81XX, 83XX.
> 
> Signed-off-by: Manish Jaggi <manish.jaggi@cavium.com>
> 
> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
> index 65eb1071e1..62ad244785 100644
> --- a/xen/include/asm-arm/processor.h
> +++ b/xen/include/asm-arm/processor.h
> @@ -43,15 +43,24 @@
>   })
>   
>   #define ARM_CPU_IMP_ARM             0x41
> +#define ARM_CPU_IMP_CAVIUM          0x43
>   
>   #define ARM_CPU_PART_CORTEX_A15     0xC0F
>   #define ARM_CPU_PART_CORTEX_A53     0xD03
>   #define ARM_CPU_PART_CORTEX_A57     0xD07
>   
> +#define CAVIUM_CPU_PART_THUNDERX      0x0A1
> +#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
> +#define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
> +
>   #define MIDR_CORTEX_A15 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A15)
>   #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
>   #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
>   
> +#define MIDR_THUNDERX      MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
> +#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
> +#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
> +
>   /* MPIDR Multiprocessor Affinity Register */
>   #define _MPIDR_UP           (30)
>   #define MPIDR_UP            (_AC(1,U) << _MPIDR_UP)
> 

-- 
Julien Grall

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  reply	other threads:[~2018-03-20  7:38 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-16 11:58 [PATCH v1 00/15] arm64: Mediate access to GICv3 sysregs at EL2 Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 01/15] arm64: cputype: Add MIDR values for Cavium ThunderX1 CPU family Manish Jaggi
2018-03-20  7:38   ` Julien Grall [this message]
2018-03-16 11:58 ` [PATCH v1 02/15] arm64: Add config for Cavium Thunder erratum 30115 Manish Jaggi
2018-03-20  7:43   ` Julien Grall
2018-03-21  5:06     ` Manish Jaggi
2018-03-21  7:49       ` Julien Grall
2018-03-16 11:58 ` [PATCH v1 03/15] arm: Placeholder for handling Group0/1 traps for Cavium Erratum 30115 Manish Jaggi
2018-03-20  8:08   ` Julien Grall
2018-03-16 11:58 ` [PATCH v1 04/15] arm64: vgic-v3: Add ICV_BPR1_EL1 handler Manish Jaggi
2018-03-21  8:11   ` Julien Grall
2018-03-26 13:11     ` Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 05/15] arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler Manish Jaggi
2018-03-21  8:38   ` Julien Grall
2018-03-26 13:09     ` Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 06/15] arm64: Add accessors for the ICH_APxRn_EL2 registers Manish Jaggi
2018-03-26 13:19   ` Manish Jaggi
2018-03-26 14:36     ` Marc Zyngier
2018-03-16 11:58 ` [PATCH v1 07/15] Expose ich_read/write_lr in vgic-v3-sr.c Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 08/15] arm64: Add ICV_IAR1_EL1 handler Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 09/15] arm64: vgic-v3: Add ICV_EOIR1_EL1 handler Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 10/15] arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 11/15] arm64: vgic-v3: Add ICV_BPR0_EL1 handler Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 12/15] arm64: vgic-v3: Add ICV_IGNREN0_EL1 handler Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 13/15] arm64: vgic-v3: Add misc Group-0 handlers Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 14/15] arm64: vgic-v3: Add ICV_AP(0/1)Rn_EL1 handler Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 15/15] Enable Group0/1 Traps by default for Cavium ThunderX1 Manish Jaggi
2018-03-20  7:46 ` [PATCH v1 00/15] arm64: Mediate access to GICv3 sysregs at EL2 Julien Grall
2018-03-21  4:58   ` Manish Jaggi
2018-03-21  5:02     ` Julien Grall
2018-03-21  8:45     ` Julien Grall
2018-03-21  9:38       ` Manish Jaggi
2018-03-21  9:56         ` Julien Grall
2018-03-23  6:42           ` Manish Jaggi
2018-03-23  6:58             ` Julien Grall
2018-03-26  4:43               ` Manish Jaggi
2018-03-26  8:24                 ` Marc Zyngier

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