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Mon, 17 Aug 2026 15:44:16 GMT Received: from smtprelay06.wdc07v.mail.ibm.com ([172.16.1.73]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 4g33xgxk36-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 17 Aug 2026 15:44:16 +0000 (GMT) Received: from smtpav02.wdc07v.mail.ibm.com (smtpav02.wdc07v.mail.ibm.com [10.39.53.229]) by smtprelay06.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 67HFiENJ25756160 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 17 Aug 2026 15:44:15 GMT Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DC98C58059; Mon, 17 Aug 2026 15:44:14 +0000 (GMT) Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2C13D58058; Mon, 17 Aug 2026 15:44:14 +0000 (GMT) Received: from mambor8.rchland.ibm.com (unknown [9.10.239.198]) by smtpav02.wdc07v.mail.ibm.com (Postfix) with ESMTP; Mon, 17 Aug 2026 15:44:14 +0000 (GMT) Message-ID: Subject: Re: [PATCH 6/7] target/ppc: Reorder PPC2 flags From: Miles Glenn To: Chinmay Rath , Shivang Upadhyay , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, tommusta@gmail.com Cc: richard.henderson@linaro.org Date: Mon, 17 Aug 2026 10:44:13 -0500 In-Reply-To: <728087c8-b350-4993-a64a-45aba38a616f@linux.ibm.com> References: <20260715125634.2107320-1-rathc@linux.ibm.com> <20260715125634.2107320-7-rathc@linux.ibm.com> <728087c8-b350-4993-a64a-45aba38a616f@linux.ibm.com> Organization: IBM Content-Type: text/plain; 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envelope-from=milesg@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: milesg@linux.ibm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org I don't have a strong opinion on this either way, but I don't think we need a decision on this before allowing this patch set to proceed either. Therefore... Reviewed-by: Glenn Miles Thanks, Glenn On Mon, 2026-07-20 at 18:35 +0530, Chinmay Rath wrote: > On 7/15/26 20:11, Shivang Upadhyay wrote: > > On Wed, 2026-07-15 at 18:26 +0530, Chinmay Rath wrote: > > > + PPC2_BCDA_ISA206 = 0x0000000000040000ULL, > > > /* PPE42 > > > instructions */ > > > - PPC2_PPE42 = 0x0000000000800000ULL, > > > + PPC2_PPE42 = 0x0000000000080000ULL, > > > /* PPE42X > > > instructions */ > > > - PPC2_PPE42X = 0x0000000001000000ULL, > > > + PPC2_PPE42X = 0x0000000000100000ULL, > > > /* PPE42XM > > > instructions */ > > > - PPC2_PPE42XM = 0x0000000002000000ULL, > > > + PPC2_PPE42XM = 0x0000000000200000ULL, > > > > > Hi Chinmay, > > > > Would it be fine if we can do something like this instead? > > > > PPC2_PPE42XM = (1ull << 21); > > > > It would be easy to see where the gaps are from next time. > Hi Shivang, > Thanks for the suggestion. I agree with you. Looking at the shift > numbers and making sure they are in consecutive incremental order would > make gaps less likely. However if we are to switch to this way, there > are about 40 such flags in cpu.h which will have to be reset in this > fashion. Hence should be a different patch in itself as the objective of > this series is different. Plus it would also bring in the risk of > someone shifting a bit by a value that might cause an overflow. So one > would have to take care of that while adding a new flag. So this way or > the original way, one does need to take care of couple things while > adding future flags. > > Regards, > Chinmay > > > ~Shivang. > >