From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E748C07E9D for ; Thu, 29 Sep 2022 07:56:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232166AbiI2H4P (ORCPT ); Thu, 29 Sep 2022 03:56:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232120AbiI2H4O (ORCPT ); Thu, 29 Sep 2022 03:56:14 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B921F128714 for ; Thu, 29 Sep 2022 00:56:13 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id a2so1043374lfb.6 for ; Thu, 29 Sep 2022 00:56:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date; bh=5I0KFer6CMq9bS+qb57rtF7Jxe3pkwXN2psBdqfUQXI=; b=Ck6MPZt5fmCodIEyDLh6E41lYpwwhdGCmZyvW+lbk2zOEhdtQQncjNQxhIZmAQ0qjG TeUEaPob21B1EMB28Uh742fObyVjUHI7G8/goo6JIe6jQFrLj493AJTbV6r8KQfjRpbw q4/SpWuUHNMw/PNhjUIORx+/r1CG2oxz3d43fivIIhQLoEYwPpy3hOZTXvvhM2ebtG8P j+GAvQBoQwLYtff6fXJdKrlX2JBFTOJ+CIugNaUl9z7KdAlX6gDFDgrZPWZmcSZJfTrq N4LP+qotWxPz4A5iZeVZ0WrP7jo1nSQ9Fmh4/ATIzgnuixkHnRMeZ126/dDY/HBhfffQ qG2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date; bh=5I0KFer6CMq9bS+qb57rtF7Jxe3pkwXN2psBdqfUQXI=; b=HA3cSeMcCmqSvT/vwp6+ykhvPD1jD0B7uOuhZXrAWXWCmoCrvXgxGD8+D5Yi3dlAnK FlamyXdf8lgdTdkUCMX6a0alxhzG1sy7RG0Of+FzbRDO0V4pS601tyhaNxwM7d+bb0N0 tNQVQgzZdzypKd444KoRtXwP9E5AjyQKPYFirgk7XnXwKKw5Ipk4CVOyAeP3Ol3mhlXn G7a6sZzquQxY+h1LuB0ytHhxVHCG/4gZi/QKpxAVO8onK2QaNrFyi5p3PfK2KX2XaRVC WLo1KyA6i2jIUUG6s3VHbk8X/Cq7fQK4TBeVSbFqdne2s1Sph+4zDxQIZrMFZZVVs6st 6z7w== X-Gm-Message-State: ACrzQf16sKazCKqkkgQnT7ITlpn+s6jkcpDluLjgPgy0s7MJIWCRmdP4 vxjMMGuHbEZf4KvnzgMz7eTLVg== X-Google-Smtp-Source: AMsMyM4ESrsuCcFeLMKwFM4lzuOI4iKNeMYoJjszgvxbAOlpQrqJOj4oMRQ2+lGzJESEEKyHlT8fJQ== X-Received: by 2002:a05:6512:31cb:b0:49f:c2dc:9986 with SMTP id j11-20020a05651231cb00b0049fc2dc9986mr812354lfe.549.1664438172091; Thu, 29 Sep 2022 00:56:12 -0700 (PDT) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id cf33-20020a056512282100b00498fbec3f8asm707549lfb.129.2022.09.29.00.56.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 29 Sep 2022 00:56:11 -0700 (PDT) Message-ID: Date: Thu, 29 Sep 2022 10:56:11 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.0 Subject: Re: [PATCH 06/13] phy: qcom-qmp-pcie: drop bogus register update Content-Language: en-GB To: Johan Hovold Cc: Johan Hovold , Vinod Koul , Andy Gross , Bjorn Andersson , Konrad Dybcio , Kishon Vijay Abraham I , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org References: <20220928152822.30687-1-johan+linaro@kernel.org> <20220928152822.30687-7-johan+linaro@kernel.org> <2bc50ea4-ec29-cacc-216b-1c21d2d2f0bc@linaro.org> From: Dmitry Baryshkov In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 29/09/2022 10:12, Johan Hovold wrote: > On Wed, Sep 28, 2022 at 10:48:40PM +0300, Dmitry Baryshkov wrote: >> On 28/09/2022 22:10, Dmitry Baryshkov wrote: >>> On 28/09/2022 18:28, Johan Hovold wrote: >>>> Since commit 0d58280cf1e6 ("phy: Update PHY power control sequence") the >>>> PHY is powered on before configuring the registers and only the MSM8996 >>>> PCIe PHY, which includes the POWER_DOWN_CONTROL register in its PCS >>>> initialisation table, may possibly require a second update afterwards. >>>> >>>> To make things worse, the POWER_DOWN_CONTROL register lies at a >>>> different offset on more recent SoCs so that the second update, which >>>> still used a hard-coded offset, would write to an unrelated register >>>> (e.g. a revision-id register on SC8280XP). >>>> >>>> As the MSM8996 PCIe PHY is now handled by a separate driver, simply drop >>>> the bogus register update. >>>> >>>> Fixes: e4d8b05ad5f9 ("phy: qcom-qmp: Use proper PWRDOWN offset for >>>> sm8150 USB") added support >>> >>> I'm not sure about the particular fixes tag. Backporting from the split >>> driver into old qmp driver would be a complete pain. >>> >>>> Signed-off-by: Johan Hovold >>> >>> Reviewed-by: Dmitry Baryshkov >> >> After digging some more, I stumbled upon the commit 0d58280cf1e6 ("phy: >> Update PHY power control sequence"), which puts explicit register write >> here, telling that 'PCIe PHYs need an extra power control before >> deasserts reset state'. > > That's the commit I'm referring to above. > >> I can confirm this with the register tables from downstream dtsi. E.g. >> consider sdm845-pcie.dts, pcie0 table. The PCS_POWER_DOWN_CONTROL is the >> register 0x804. >> >> The programmings starts with <0x804 0x1 0x0>, writing 1 to >> PCS_POWER_DOWN_CONTROL (which if I'm not mistaken we do not do at this >> moment). Then after writing all the serdes/tx/rx/pcs/pcs_misc tables >> comes the write <0x804 0x3 0x0> (which you are trying to remove here). > > The PHY would already have been powered on with the mainline driver, that > write has already happened. > > Whether or not PCIe support for SDM845 has been broken since it was > first mainlined almost three years ago is a separate issue. I assume > Bjorn tested it before sending it upstream. > > 421c9a0e9731 ("phy: qcom: qmp: Add SDM845 PCIe QMP PHY support") On SDM845 PCIe0 is used for the WiFi, e.g. on the RB3 (dragonboard845) device. The PHY definitely works with the upstream kernels. > >> Same sequence applies to the PCIe PHY on msm8998. >> >> Most newer PHYs have the expected sequence (of writing 0x3 to >> PCS_POWER_DOWN_CONTROL) before writing all registers. >> >> As a short summary: unless we get any additional information that 8998 >> and sdm845 tables are incorrect, I'd suggest adding a conditional here >> (ugh) and using it here and in qmp_pcie_init() call. > > I see little point in doing that unless you dig out an SDM845, confirm > that it has never worked with upstream, and update the init sequence > first. Digging out an sdm845 is not a problem per se. It works, but it also has an additional regwrite that this patch tries to remove. I will try checking whether it works with this register write being removed or not. > >> Vinod, Bjorn, do you have any additional info? > > An explanation of the split POWER_DOWN_CONTROL updates on MSM8996 would > be good to have either way -- With best wishes Dmitry From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1908EC6FA82 for ; Thu, 29 Sep 2022 07:56:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Thu, 29 Sep 2022 00:56:12 -0700 (PDT) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id cf33-20020a056512282100b00498fbec3f8asm707549lfb.129.2022.09.29.00.56.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 29 Sep 2022 00:56:11 -0700 (PDT) Message-ID: Date: Thu, 29 Sep 2022 10:56:11 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.0 Subject: Re: [PATCH 06/13] phy: qcom-qmp-pcie: drop bogus register update Content-Language: en-GB To: Johan Hovold Cc: Johan Hovold , Vinod Koul , Andy Gross , Bjorn Andersson , Konrad Dybcio , Kishon Vijay Abraham I , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org References: <20220928152822.30687-1-johan+linaro@kernel.org> <20220928152822.30687-7-johan+linaro@kernel.org> <2bc50ea4-ec29-cacc-216b-1c21d2d2f0bc@linaro.org> From: Dmitry Baryshkov In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220929_005615_988023_42FFA275 X-CRM114-Status: GOOD ( 28.52 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 29/09/2022 10:12, Johan Hovold wrote: > On Wed, Sep 28, 2022 at 10:48:40PM +0300, Dmitry Baryshkov wrote: >> On 28/09/2022 22:10, Dmitry Baryshkov wrote: >>> On 28/09/2022 18:28, Johan Hovold wrote: >>>> Since commit 0d58280cf1e6 ("phy: Update PHY power control sequence") the >>>> PHY is powered on before configuring the registers and only the MSM8996 >>>> PCIe PHY, which includes the POWER_DOWN_CONTROL register in its PCS >>>> initialisation table, may possibly require a second update afterwards. >>>> >>>> To make things worse, the POWER_DOWN_CONTROL register lies at a >>>> different offset on more recent SoCs so that the second update, which >>>> still used a hard-coded offset, would write to an unrelated register >>>> (e.g. a revision-id register on SC8280XP). >>>> >>>> As the MSM8996 PCIe PHY is now handled by a separate driver, simply drop >>>> the bogus register update. >>>> >>>> Fixes: e4d8b05ad5f9 ("phy: qcom-qmp: Use proper PWRDOWN offset for >>>> sm8150 USB") added support >>> >>> I'm not sure about the particular fixes tag. Backporting from the split >>> driver into old qmp driver would be a complete pain. >>> >>>> Signed-off-by: Johan Hovold >>> >>> Reviewed-by: Dmitry Baryshkov >> >> After digging some more, I stumbled upon the commit 0d58280cf1e6 ("phy: >> Update PHY power control sequence"), which puts explicit register write >> here, telling that 'PCIe PHYs need an extra power control before >> deasserts reset state'. > > That's the commit I'm referring to above. > >> I can confirm this with the register tables from downstream dtsi. E.g. >> consider sdm845-pcie.dts, pcie0 table. The PCS_POWER_DOWN_CONTROL is the >> register 0x804. >> >> The programmings starts with <0x804 0x1 0x0>, writing 1 to >> PCS_POWER_DOWN_CONTROL (which if I'm not mistaken we do not do at this >> moment). Then after writing all the serdes/tx/rx/pcs/pcs_misc tables >> comes the write <0x804 0x3 0x0> (which you are trying to remove here). > > The PHY would already have been powered on with the mainline driver, that > write has already happened. > > Whether or not PCIe support for SDM845 has been broken since it was > first mainlined almost three years ago is a separate issue. I assume > Bjorn tested it before sending it upstream. > > 421c9a0e9731 ("phy: qcom: qmp: Add SDM845 PCIe QMP PHY support") On SDM845 PCIe0 is used for the WiFi, e.g. on the RB3 (dragonboard845) device. The PHY definitely works with the upstream kernels. > >> Same sequence applies to the PCIe PHY on msm8998. >> >> Most newer PHYs have the expected sequence (of writing 0x3 to >> PCS_POWER_DOWN_CONTROL) before writing all registers. >> >> As a short summary: unless we get any additional information that 8998 >> and sdm845 tables are incorrect, I'd suggest adding a conditional here >> (ugh) and using it here and in qmp_pcie_init() call. > > I see little point in doing that unless you dig out an SDM845, confirm > that it has never worked with upstream, and update the init sequence > first. Digging out an sdm845 is not a problem per se. It works, but it also has an additional regwrite that this patch tries to remove. I will try checking whether it works with this register write being removed or not. > >> Vinod, Bjorn, do you have any additional info? > > An explanation of the split POWER_DOWN_CONTROL updates on MSM8996 would > be good to have either way -- With best wishes Dmitry -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy