From: Dave Jiang <dave.jiang@intel.com>
To: Alison Schofield <alison.schofield@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Jonathan Cameron <jic23@kernel.org>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <iweiny@kernel.org>, Li Ming <ming.li@zohomail.com>,
Richard Cheng <icheng@nvidia.com>,
Robert Richter <rrichter@amd.com>
Cc: linux-cxl@vger.kernel.org
Subject: Re: [PATCH 3/7] cxl/region: Factor out cxl_port_peer_distance()
Date: Fri, 9 Oct 2026 15:27:39 -0700 [thread overview]
Message-ID: <e63056bb-ded8-42d2-9443-77b379496fcf@intel.com> (raw)
In-Reply-To: <2a4d99ac07511575950f6cd83df39742d1747861.1791575481.git.alison.schofield@intel.com>
On 10/9/26 1:24 PM, Alison Schofield wrote:
> cxl_port_setup_targets() is nearly 200 lines long and open codes each step
> of adding an endpoint to a port's decoder. One of those steps calculates
> the distance between region positions that share a downstream port.
>
> Move that calculation to a new helper, cxl_port_peer_distance().
>
> No functional change.
>
> Assisted-by: LLM
> Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/core/region.c | 50 +++++++++++++++++++++++----------------
> 1 file changed, 29 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 1a42753fda48..80c40716c368 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -1432,6 +1432,33 @@ static int check_interleave_cap(struct cxl_decoder *cxld, int iw, int ig)
> return 0;
> }
>
> +static int cxl_port_peer_distance(struct cxl_port *port, struct cxl_region *cxlr)
> +{
> + struct cxl_root_decoder *cxlrd = cxlr->cxlrd;
> + struct cxl_region_ref *cxl_rr_iter;
> + struct cxl_port *iter = port;
> + int distance = 1;
> +
> + /*
> + * The "distance" between peer downstream ports represents which
> + * endpoint positions in the region interleave a given port can
> + * host.
> + *
> + * For example, at the root of a hierarchy the distance is
> + * always 1 as every index targets a different host-bridge. At
> + * each subsequent switch level those ports map every Nth region
> + * position where N is the width of the switch == distance.
> + */
> + do {
> + cxl_rr_iter = cxl_rr_load(iter, cxlr);
> + distance *= cxl_rr_iter->nr_targets;
> + iter = to_cxl_port(iter->dev.parent);
> + } while (!is_cxl_root(iter));
> + distance *= cxlrd->cxlsd.cxld.interleave_ways;
> +
> + return distance;
> +}
> +
> static int cxl_port_setup_targets(struct cxl_port *port,
> struct cxl_region *cxlr,
> struct cxl_endpoint_decoder *cxled)
> @@ -1445,7 +1472,6 @@ static int cxl_port_setup_targets(struct cxl_port *port,
> struct cxl_region_params *p = &cxlr->params;
> struct cxl_decoder *cxld = cxl_rr->decoder;
> struct cxl_switch_decoder *cxlsd;
> - struct cxl_port *iter = port;
>
> /*
> * While root level decoders support x3, x6, x12, switch level
> @@ -1460,27 +1486,9 @@ static int cxl_port_setup_targets(struct cxl_port *port,
>
> cxlsd = to_cxl_switch_decoder(&cxld->dev);
> if (cxl_rr->nr_targets_set) {
> - int i, distance = 1;
> - struct cxl_region_ref *cxl_rr_iter;
> + int distance = cxl_port_peer_distance(port, cxlr);
>
> - /*
> - * The "distance" between peer downstream ports represents which
> - * endpoint positions in the region interleave a given port can
> - * host.
> - *
> - * For example, at the root of a hierarchy the distance is
> - * always 1 as every index targets a different host-bridge. At
> - * each subsequent switch level those ports map every Nth region
> - * position where N is the width of the switch == distance.
> - */
> - do {
> - cxl_rr_iter = cxl_rr_load(iter, cxlr);
> - distance *= cxl_rr_iter->nr_targets;
> - iter = to_cxl_port(iter->dev.parent);
> - } while (!is_cxl_root(iter));
> - distance *= cxlrd->cxlsd.cxld.interleave_ways;
> -
> - for (i = 0; i < cxl_rr->nr_targets_set; i++)
> + for (int i = 0; i < cxl_rr->nr_targets_set; i++)
> if (ep->dport == cxlsd->target[i]) {
> rc = check_last_peer(cxled, ep, cxl_rr,
> distance);
next prev parent reply other threads:[~2026-10-09 22:27 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-09 20:24 [PATCH 0/7] cxl/region: Refactor cxl_port_setup_targets() Alison Schofield
2026-10-09 20:24 ` [PATCH 1/7] cxl: Add interleave encoding validity helpers Alison Schofield
2026-10-09 22:14 ` Dave Jiang
2026-10-09 20:24 ` [PATCH 2/7] cxl/region: Name the interleave locals in cxl_port_setup_targets() Alison Schofield
2026-10-09 22:23 ` Dave Jiang
2026-10-09 20:24 ` [PATCH 3/7] cxl/region: Factor out cxl_port_peer_distance() Alison Schofield
2026-10-09 22:27 ` Dave Jiang [this message]
2026-10-09 20:24 ` [PATCH 4/7] cxl/region: Factor out cxl_port_parent_interleave() Alison Schofield
2026-10-09 22:39 ` Dave Jiang
2026-10-10 0:33 ` Alison Schofield
2026-10-09 20:24 ` [PATCH 5/7] cxl/region: Factor out cxl_port_calc_interleave() Alison Schofield
2026-10-09 22:45 ` Dave Jiang
2026-10-09 20:24 ` [PATCH 6/7] cxl/region: Factor out cxl_port_setup_decoder() Alison Schofield
2026-10-09 22:46 ` Dave Jiang
2026-10-09 20:24 ` [PATCH 7/7] cxl/region: Factor out cxl_port_add_target() Alison Schofield
2026-10-09 22:48 ` Dave Jiang
2026-10-10 0:36 ` Alison Schofield
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