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Tue, 18 Feb 2025 19:24:54 -0800 Received: from [10.110.48.28] (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Tue, 18 Feb 2025 19:24:54 -0800 Message-ID: Date: Tue, 18 Feb 2025 19:24:53 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC 1/3] rust: add useful ops for u64 To: Alexandre Courbot , Timur Tabi , "daniel.almeida@collabora.com" CC: "dri-devel@lists.freedesktop.org" , "rust-for-linux@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "nouveau@lists.freedesktop.org" , "dakr@kernel.org" , "airlied@gmail.com" , Ben Skeggs References: <20250217-nova_timer-v1-0-78c5ace2d987@nvidia.com> <20250217-nova_timer-v1-1-78c5ace2d987@nvidia.com> <1b8921d46f7d70c7467ea0940d60220f05cccc5d.camel@nvidia.com> Content-Language: en-US From: John Hubbard In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C6:EE_|DM6PR12MB4153:EE_ X-MS-Office365-Filtering-Correlation-Id: 87bdf88a-8523-4053-4081-08dd509500b2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Feb 2025 03:25:04.7415 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 87bdf88a-8523-4053-4081-08dd509500b2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4153 X-BeenThere: nouveau@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Nouveau development list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: nouveau-bounces@lists.freedesktop.org Sender: "Nouveau" On 2/18/25 5:21 PM, Alexandre Courbot wrote: > On Wed Feb 19, 2025 at 5:51 AM JST, Timur Tabi wrote: >> On Tue, 2025-02-18 at 22:16 +0900, Alexandre Courbot wrote: ... > More likely this would be something like: > > let SplitU64 { high: some_u32, .. } = some_u64; > > Which is still a bit verbose, but a single-liner. > > Actually. How about adding methods to this trait that return either > component? > > let some_u32 = some_u64.high_half(); > let another_u32 = some_u64.low_half(); > > These should be used most of the times, and using destructuring/tuple > would only be useful for a few select cases. I think I like this approach best so far, because that is actually how drivers tend to use these values: one or the other 32 bits at a time. Registers are often grouped into 32-bit named registers, and driver code wants to refer to them one at a time (before breaking some of them down into smaller named fields)> The .high_half() and .low_half() approach matches that very closely. And it's simpler to read than the SplitU64 API, without losing anything we need, right? thanks, -- John Hubbard